watchdog: f71808e_wdt: Add F81865 support

PATCH Superseded Knud Poulsen 2 participants 7 messages Apr 22, 2016 Watchdog device drivers

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Knud Poulsen

author

2016-04-22 11:48 UTC #0 lore raw

PATCH v2 1/1 watchdog: f71808e_wdt: Add F81865 support

Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)

Tested and verified on Lanner LEC-3030 Industrial PC

Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html

Signed-off-by Knud Poulsen <[email protected]>

---
 drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

drivers/watchdog/f71808e_wdt.c +27 -4

index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
 #define SIO_F71869A_ID		0x1007	/* Chipset ID */
 #define SIO_F71882_ID		0x0541	/* Chipset ID */
 #define SIO_F71889_ID		0x0723	/* Chipset ID */
+#define SIO_F81865_ID		0x0704	/* Chipset ID */
 
 #define F71808FG_REG_WDO_CONF		0xf0
 #define F71808FG_REG_WDT_CONF		0xf5

@@ -71,6 +72,10 @@
 #define F71808FG_FLAG_WD_PULSE		4
 #define F71808FG_FLAG_WD_UNIT		3
 
+#define F81865_REG_WDO_CONF		0xfa
+#define F81865_FLAG_WDOUT_EN		0
+#define F81865_FLAG_WDTMOUT_STS		6
+
 /* Default values */
 #define WATCHDOG_TIMEOUT	60	/* 1 minute default timeout */
 #define WATCHDOG_MAX_TIMEOUT	(60 * 255)

@@ -112,7 +117,7 @@ module_param(start_withtimeout, uint, 0);
 MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
 	" given initial timeout. Zero (default) disables this feature.");
 
-enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg };
+enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg, f81865 };
 
 static const char *f71808e_names[] = {
 	"f71808fg",

@@ -121,6 +126,7 @@ static const char *f71808e_names[] = {
 	"f71869",
 	"f71882fg",
 	"f71889fg",
+	"f81865",
 };
 
 /* Super-I/O Function prototypes */

@@ -360,6 +366,11 @@ static int watchdog_start(void)
 			superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
 		break;
 
+	case f81865:
+		/* Set pin 70 to WDTRST# */
+		superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
+		break;
+
 	default:
 		/*
 		 * 'default' label to shut up the compiler and catch

@@ -371,8 +382,13 @@ static int watchdog_start(void)
 
 	superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
 	superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
-	superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
-			F71808FG_FLAG_WDOUT_EN);
+
+	if (watchdog.type == f81865)
+		superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
+				F81865_FLAG_WDOUT_EN);
+	else
+		superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
+				F71808FG_FLAG_WDOUT_EN);
 
 	superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
 			F71808FG_FLAG_WD_EN);

@@ -655,7 +671,11 @@ static int __init watchdog_init(int sioaddr)
 	superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
 
 	wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
-	watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+	if (watchdog.type == f81865)
+		watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+	else
+		watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
 
 	superio_exit(sioaddr);

@@ -770,6 +790,9 @@ static int __init f71808e_find(int sioaddr)
 		/* Confirmed (by datasheet) not to have a watchdog. */
 		err = -ENODEV;
 		goto exit;
+	case SIO_F81865_ID:
+		watchdog.type = f81865;
+		break;
 	default:
 		pr_info("Unrecognized Fintek device: %04x\n",
 			(unsigned int)devid);

Signature · 1 line

2.5.5

Guenter Roeck

maintainer

2016-04-22 13:51 UTC #1 lore raw

Quoted 83 lines · Knud Poulsen

Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)

Tested and verified on Lanner LEC-3030 Industrial PC

Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html

Signed-off-by Knud Poulsen <[email protected]>

---
  drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
  1 file changed, 27 insertions(+), 4 deletions(-)

drivers/watchdog/f71808e_wdt.c +19 -3

index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
  #define SIO_F71869A_ID		0x1007	/* Chipset ID */
  #define SIO_F71882_ID		0x0541	/* Chipset ID */
  #define SIO_F71889_ID		0x0723	/* Chipset ID */
+#define SIO_F81865_ID		0x0704	/* Chipset ID */
 
  #define F71808FG_REG_WDO_CONF		0xf0
  #define F71808FG_REG_WDT_CONF		0xf5

@@ -71,6 +72,10 @@
  #define F71808FG_FLAG_WD_PULSE		4
  #define F71808FG_FLAG_WD_UNIT		3
 
+#define F81865_REG_WDO_CONF		0xfa
+#define F81865_FLAG_WDOUT_EN		0
+#define F81865_FLAG_WDTMOUT_STS		6
+
  /* Default values */
  #define WATCHDOG_TIMEOUT	60	/* 1 minute default timeout */
  #define WATCHDOG_MAX_TIMEOUT	(60 * 255)

@@ -112,7 +117,7 @@ module_param(start_withtimeout, uint, 0);
  MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
  	" given initial timeout. Zero (default) disables this feature.");
 
-enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg };
+enum chips { f71808fg, f71858fg, f71862fg, f71869, f71882fg, f71889fg, f81865 };
 
  static const char *f71808e_names[] = {
  	"f71808fg",

@@ -121,6 +126,7 @@ static const char *f71808e_names[] = {
  	"f71869",
  	"f71882fg",
  	"f71889fg",
+	"f81865",
  };
 
  /* Super-I/O Function prototypes */

@@ -360,6 +366,11 @@ static int watchdog_start(void)
  			superio_inb(watchdog.sioaddr, SIO_REG_MFUNCT3) & 0xcf);
  		break;
 
+	case f81865:
+		/* Set pin 70 to WDTRST# */
+		superio_clear_bit(watchdog.sioaddr, SIO_REG_MFUNCT3, 5);
+		break;
+
  	default:
  		/*
  		 * 'default' label to shut up the compiler and catch

@@ -371,8 +382,13 @@ static int watchdog_start(void)
 
  	superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
  	superio_set_bit(watchdog.sioaddr, SIO_REG_ENABLE, 0);
-	superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
-			F71808FG_FLAG_WDOUT_EN);
+
+	if (watchdog.type == f81865)
+		superio_set_bit(watchdog.sioaddr, F81865_REG_WDO_CONF,
+				F81865_FLAG_WDOUT_EN);
+	else
+		superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDO_CONF,
+				F71808FG_FLAG_WDOUT_EN);
 
  	superio_set_bit(watchdog.sioaddr, F71808FG_REG_WDT_CONF,
  			F71808FG_FLAG_WD_EN);

drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 679

Quoted 10 lines

drivers/watchdog/f71808e_wdt.c +5 -1

@@ -655,7 +671,11 @@ static int __init watchdog_init(int sioaddr)
  	superio_select(watchdog.sioaddr, SIO_F71808FG_LD_WDT);
 
  	wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
-	watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+	if (watchdog.type == f81865)
+		watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+	else
+		watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;

Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.

Am I missing something here ?

Thanks,
Guenter

Quoted 13 lines

drivers/watchdog/f71808e_wdt.c +3 -0

  	superio_exit(sioaddr);

@@ -770,6 +790,9 @@ static int __init f71808e_find(int sioaddr)
  		/* Confirmed (by datasheet) not to have a watchdog. */
  		err = -ENODEV;
  		goto exit;
+	case SIO_F81865_ID:
+		watchdog.type = f81865;
+		break;
  	default:
  		pr_info("Unrecognized Fintek device: %04x\n",
  			(unsigned int)devid);

Guenter Roeck

maintainer

2016-04-22 13:59 UTC #2 lore raw

Quoted 35 lines · Guenter Roeck

Quoted 34 lines · Knud Poulsen

Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)

Tested and verified on Lanner LEC-3030 Industrial PC

Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html

Signed-off-by Knud Poulsen <[email protected]>

---
  drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
  1 file changed, 27 insertions(+), 4 deletions(-)

drivers/watchdog/f71808e_wdt.c +5 -0

index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
  #define SIO_F71869A_ID        0x1007    /* Chipset ID */
  #define SIO_F71882_ID        0x0541    /* Chipset ID */
  #define SIO_F71889_ID        0x0723    /* Chipset ID */
+#define SIO_F81865_ID        0x0704    /* Chipset ID */
 
  #define F71808FG_REG_WDO_CONF        0xf0
  #define F71808FG_REG_WDT_CONF        0xf5

@@ -71,6 +72,10 @@
  #define F71808FG_FLAG_WD_PULSE        4
  #define F71808FG_FLAG_WD_UNIT        3
 
+#define F81865_REG_WDO_CONF        0xfa
+#define F81865_FLAG_WDOUT_EN        0
+#define F81865_FLAG_WDTMOUT_STS        6
+

[ ... ]

Quoted 9 lines

drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 678

Quoted 9 lines

      wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);

drivers/watchdog/f71808e_wdt.c +5 -1

-    watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+    if (watchdog.type == f81865)
+        watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+    else
+        watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;

Quoted 8 lines

Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.
Am I missing something here ?

After another look, I am even more confused. F81865_FLAG_WDTMOUT_STS and F71808FG_FLAG_WDTMOUT_STS are bit maps, not bits.

5 = 0b0101, 6 = 0b0110. Bit 0/1 select the pulse width, bit 2 selects the output polarity of RSTOUT. What does this have to do with the reboot cause ?

Thanks,
Guenter

Knud Poulsen

author

2016-04-22 14:19 UTC #3 lore raw

Quoted 53 lines · Guenter Roeck

Quoted 35 lines · Guenter Roeck
Quoted 34 lines · Knud Poulsen
Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)
Tested and verified on Lanner LEC-3030 Industrial PC
Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html
Signed-off-by Knud Poulsen <[email protected]>
---
  drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
  1 file changed, 27 insertions(+), 4 deletions(-)
drivers/watchdog/f71808e_wdt.c +5 -0
index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
  #define SIO_F71869A_ID        0x1007    /* Chipset ID */
  #define SIO_F71882_ID        0x0541    /* Chipset ID */
  #define SIO_F71889_ID        0x0723    /* Chipset ID */
+#define SIO_F81865_ID        0x0704    /* Chipset ID */
 
  #define F71808FG_REG_WDO_CONF        0xf0
  #define F71808FG_REG_WDT_CONF        0xf5
@@ -71,6 +72,10 @@
  #define F71808FG_FLAG_WD_PULSE        4
  #define F71808FG_FLAG_WD_UNIT        3
 
+#define F81865_REG_WDO_CONF        0xfa
+#define F81865_FLAG_WDOUT_EN        0
+#define F81865_FLAG_WDTMOUT_STS        6
+
[ ... ]
Quoted 15 lines
drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 678
Quoted 9 lines
      wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
drivers/watchdog/f71808e_wdt.c +5 -1
-    watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+    if (watchdog.type == f81865)
+        watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+    else
+        watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.

Quoted 7 lines

Quoted 2 lines
Am I missing something here ?
After another look, I am even more confused. F81865_FLAG_WDTMOUT_STS and F71808FG_FLAG_WDTMOUT_STS are bit maps, not bits.
5 = 0b0101, 6 = 0b0110. Bit 0/1 select the pulse width, bit 2 selects the output polarity of RSTOUT. What does this have to do with the reboot cause ?

You're right, great catch!!, I didn't grok the bit-map, not bit-index part here and got thrown by the 6 vs 5 in the datasheet vs the existing code, *Doh*

ps3 en route.

BR,
Knud

Quoted 4 lines

Thanks,
Guenter

Knud Poulsen

author

2016-04-22 14:47 UTC #4 lore raw

Quoted 61 lines · Knud Poulsen

Quoted 58 lines · Guenter Roeck
Quoted 35 lines · Guenter Roeck
Quoted 34 lines · Knud Poulsen
Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)
Tested and verified on Lanner LEC-3030 Industrial PC
Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html
Signed-off-by Knud Poulsen <[email protected]>
---
  drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
  1 file changed, 27 insertions(+), 4 deletions(-)
drivers/watchdog/f71808e_wdt.c +5 -0
index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
  #define SIO_F71869A_ID        0x1007    /* Chipset ID */
  #define SIO_F71882_ID        0x0541    /* Chipset ID */
  #define SIO_F71889_ID        0x0723    /* Chipset ID */
+#define SIO_F81865_ID        0x0704    /* Chipset ID */
 
  #define F71808FG_REG_WDO_CONF        0xf0
  #define F71808FG_REG_WDT_CONF        0xf5
@@ -71,6 +72,10 @@
  #define F71808FG_FLAG_WD_PULSE        4
  #define F71808FG_FLAG_WD_UNIT        3
 
+#define F81865_REG_WDO_CONF        0xfa
+#define F81865_FLAG_WDOUT_EN        0
+#define F81865_FLAG_WDTMOUT_STS        6
+
[ ... ]
Quoted 9 lines
drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 678
Quoted 9 lines
      wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
drivers/watchdog/f71808e_wdt.c +5 -1
-    watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+    if (watchdog.type == f81865)
+        watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+    else
+        watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
Quoted 8 lines
Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.
Am I missing something here ?
After another look, I am even more confused. F81865_FLAG_WDTMOUT_STS and F71808FG_FLAG_WDTMOUT_STS are bit maps, not bits.

Quoted 7 lines

Quoted 2 lines
5 = 0b0101, 6 = 0b0110. Bit 0/1 select the pulse width, bit 2 selects the output polarity of RSTOUT. What does this have to do with the reboot cause ?
You're right, great catch!!, I didn't grok the bit-map, not bit-index part here and got thrown by the 6 vs 5 in the datasheet vs the existing code, *Doh*
ps3 en route.

Hi Guenter,

The coin drops... ok, I now share your confusion 110%... let me trace and test this *a lot* more on Monday when I have access to the hardware...

ps3 by ~mid next week...

Thanks !!

BR,
Knud

Quoted 8 lines

BR,
Knud
Quoted 4 lines
Thanks,
Guenter

Guenter Roeck

maintainer

2016-04-22 14:54 UTC #5 lore raw

Quoted 70 lines · Knud Poulsen

Quoted 67 lines · Knud Poulsen
Quoted 53 lines · Guenter Roeck
Quoted 35 lines · Guenter Roeck
Quoted 34 lines · Knud Poulsen
Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)
Tested and verified on Lanner LEC-3030 Industrial PC
Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html
Signed-off-by Knud Poulsen <[email protected]>
---
   drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
   1 file changed, 27 insertions(+), 4 deletions(-)
drivers/watchdog/f71808e_wdt.c +5 -0
index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
   #define SIO_F71869A_ID        0x1007    /* Chipset ID */
   #define SIO_F71882_ID        0x0541    /* Chipset ID */
   #define SIO_F71889_ID        0x0723    /* Chipset ID */
+#define SIO_F81865_ID        0x0704    /* Chipset ID */
 
   #define F71808FG_REG_WDO_CONF        0xf0
   #define F71808FG_REG_WDT_CONF        0xf5
@@ -71,6 +72,10 @@
   #define F71808FG_FLAG_WD_PULSE        4
   #define F71808FG_FLAG_WD_UNIT        3
 
+#define F81865_REG_WDO_CONF        0xfa
+#define F81865_FLAG_WDOUT_EN        0
+#define F81865_FLAG_WDTMOUT_STS        6
+
[ ... ]
Quoted 15 lines
drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 678
Quoted 9 lines
       wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
drivers/watchdog/f71808e_wdt.c +5 -1
-    watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+    if (watchdog.type == f81865)
+        watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+    else
+        watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.
Quoted 7 lines
Quoted 2 lines
Am I missing something here ?
After another look, I am even more confused. F81865_FLAG_WDTMOUT_STS and F71808FG_FLAG_WDTMOUT_STS are bit maps, not bits.
5 = 0b0101, 6 = 0b0110. Bit 0/1 select the pulse width, bit 2 selects the output polarity of RSTOUT. What does this have to do with the reboot cause ?
You're right, great catch!!, I didn't grok the bit-map, not bit-index part here and got thrown by the 6 vs 5 in the datasheet vs the existing code, *Doh*

Quoted 9 lines

Quoted 1 line
ps3 en route.
Hi Guenter,
The coin drops... ok, I now share your confusion 110%... let me trace and test this *a lot* more on Monday when I have access to the hardware...
ps3 by ~mid next week...

No problem. Yes, testing this will be important.

Thanks,
Guenter

Guenter Roeck

maintainer

2016-04-22 14:53 UTC #6 lore raw

In reply to Knud Poulsen

Quoted 61 lines · Knud Poulsen

Quoted 58 lines · Guenter Roeck
Quoted 35 lines · Guenter Roeck
Quoted 34 lines · Knud Poulsen
Adds watchdog support for Fintek F81865 Super-IO chip to Fintek wdt driver (f71808e_wdt)
Tested and verified on Lanner LEC-3030 Industrial PC
Datasheet references:
http://www.hardwaresecrets.com/datasheets/F81865_V028P.pdf
http://www.alldatasheet.com/datasheet-pdf/pdf/406317/FINTEK/F81865.html
Signed-off-by Knud Poulsen <[email protected]>
---
   drivers/watchdog/f71808e_wdt.c | 31 +++++++++++++++++++++++++++----
   1 file changed, 27 insertions(+), 4 deletions(-)
drivers/watchdog/f71808e_wdt.c +5 -0
index 016bd93..4133cd3 100644
@@ -59,6 +59,7 @@
   #define SIO_F71869A_ID        0x1007    /* Chipset ID */
   #define SIO_F71882_ID        0x0541    /* Chipset ID */
   #define SIO_F71889_ID        0x0723    /* Chipset ID */
+#define SIO_F81865_ID        0x0704    /* Chipset ID */
 
   #define F71808FG_REG_WDO_CONF        0xf0
   #define F71808FG_REG_WDT_CONF        0xf5
@@ -71,6 +72,10 @@
   #define F71808FG_FLAG_WD_PULSE        4
   #define F71808FG_FLAG_WD_UNIT        3
 
+#define F81865_REG_WDO_CONF        0xfa
+#define F81865_FLAG_WDOUT_EN        0
+#define F81865_FLAG_WDTMOUT_STS        6
+
[ ... ]
Quoted 9 lines
drivers/watchdog/f71808e_wdt.c static int __init watchdog_init(int sioaddr) · line 678
Quoted 9 lines
       wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF);
drivers/watchdog/f71808e_wdt.c +5 -1
-    watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
+
+    if (watchdog.type == f81865)
+        watchdog.caused_reboot = wdt_conf & F81865_FLAG_WDTMOUT_STS;
+    else
+        watchdog.caused_reboot = wdt_conf & F71808FG_FLAG_WDTMOUT_STS;
Quoted 8 lines
Are you sure this one is correct ? The bit configuration is exactly the same as with other chips supported by this driver. Actually, I don't see an indication in any of the datasheets I have which would suggest that reading bit 5 means that the last reboot occurred due to a watchdog timeout. As far as I can see, it just means that the watchdog is enabled.
Am I missing something here ?
After another look, I am even more confused. F81865_FLAG_WDTMOUT_STS and F71808FG_FLAG_WDTMOUT_STS are bit maps, not bits.

Quoted 8 lines

Quoted 2 lines
5 = 0b0101, 6 = 0b0110. Bit 0/1 select the pulse width, bit 2 selects the output polarity of RSTOUT. What does this have to do with the reboot cause ?
You're right, great catch!!, I didn't grok the bit-map, not bit-index part here and got thrown by the 6 vs 5 in the datasheet vs the existing code, *Doh*
ps3 en route.

I would leave that piece of code alone for now. Changing it, possibly to check for bit 6 instead of bit 5, should be a separate patch, and apply to all chips supported by the driver. You would have to confirm, though, that the bit is actually set after a watchdog triggered reset. Another question is if bit 6 is ever cleared - in order for it to be useful, it would have to be cleared after reading it.

Thanks,
Guenter