ARM: socfpga: dts: Add samtec VIN|ING board
PATCH 1/1 ARM: socfpga: dts: Add samtec VIN|ING board
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 310 +++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
arch/arm/boot/dts/Makefile +1 -0
@@ -620,6 +620,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += \ spear1310-evb.dtb \
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts new file +310 -0
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Signature · 1 line
2.7.0
PATCH 1/1 ARM: socfpga: dts: Add samtec VIN|ING board
Quoted 9 lines · Marek Vasut
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Quoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 310 +++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
Minor nit for next time. The arm-soc maintainers would like the commit head for DTS to be: "ARM: dts: <platform>".
I fixed it up and applied.
Thanks,
Dinh
PATCH 1/1 ARM: socfpga: dts: Add samtec VIN|ING board
Quoted 18 lines · Dinh Nguyen
Quoted 9 lines · Marek Vasut
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensorQuoted 7 lines
Signed-off-by Marek Vasut <[email protected]>Cc Dinh Nguyen <[email protected]>--- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 310 +++++++++++++++++++++ 2 files changed, 311 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
Quoted 2 lines
Minor nit for next time. The arm-soc maintainers would like the commit head for DTS to be: "ARM: dts: <platform>".
Ha, thanks for the update. I wasn't aware of the ordering requirement.
Quoted 5 lines
I fixed it up and applied.
Thanks,
Dinh
Signature · 2 lines
Best regards, Marek Vasut