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arm64: hisilicon: hip05 fix and update

PATCH New Kefeng Wang 2 participants 4 messages Apr 8, 2016 – Apr 27, 2016

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Device tree bindings Arm/HiSilicon SoC support
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Kefeng Wang

author
#0 lore raw

v2 cover arm64: hisilicon: hip05 fix and update

Hip05:
- Fix its node without msi-cells
- Add nor flash node

Change since v1:
- msi-cells should be #msi-cells

Kefeng Wang (2):
arm64: dts: hip05: fix its node without msi-cells
arm64: dts: hip05: Add nor flash support

 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 34 +++++++++++++++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    | 10 +++++++++
 2 files changed, 44 insertions(+)
Signature · 1 line
1.7.12.4
author
#1 lore raw

PATCH v2 1/2 arm64: dts: hip05: fix its node without msi-cells

Fix commit abf9c25d55e8 ("arm64: dts: hip05: Append all gicv3 ITS entries"), it forgets the property msi-cell, see arm,gic-v3.txt.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/hisilicon/hip05.dtsi +4 -0
index 6319ff3..52d06ab 100644
@@ -249,24 +249,28 @@
 		its_peri: interrupt-controller at 8c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
+			#msi-cells = <1>;
 			reg = <0x0 0x8c000000 0x0 0x40000>;
 		};
 
 		its_m3: interrupt-controller at a3000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
+			#msi-cells = <1>;
 			reg = <0x0 0xa3000000 0x0 0x40000>;
 		};
 
 		its_pcie: interrupt-controller at b7000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
+			#msi-cells = <1>;
 			reg = <0x0 0xb7000000 0x0 0x40000>;
 		};
 
 		its_dsa: interrupt-controller at c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
+			#msi-cells = <1>;
 			reg = <0x0 0xc6000000 0x0 0x40000>;
 		};
 	};
Signature · 1 line
1.7.12.4
author
#2 lore raw

PATCH v2 2/2 arm64: dts: hip05: Add nor flash support

In reply to Kefeng Wang

This patch is to add support nor-flash. Notice, the pre-defined partitions may not be used.

Signed-off-by Kefeng Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 34 +++++++++++++++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    |  6 +++++
 2 files changed, 40 insertions(+)
arch/arm64/boot/dts/hisilicon/hip05-d02.dts +34 -0
index e9436c0..abba750 100644
@@ -52,3 +52,37 @@
 &peri_gpio0 {
 	status = "ok";
 };
+
+&lbc {
+	status = "ok";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x0 0x90000000 0x08000000>,
+		 <1 0 0x0 0x98000000 0x08000000>;
+
+	nor-flash at 0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "numonyx,js28f00a", "cfi-flash";
+		reg = <0 0x0 0x08000000>;
+		bank-width = <2>;
+		/* The three parts may not used */
+		partition at 0 {
+			label = "BIOS";
+			reg = <0x0 0x300000>;
+		};
+		partition at 300000 {
+			label = "Linux";
+			reg = <0x300000 0xa00000>;
+		};
+		partition at 1000000 {
+			label = "Rootfs";
+			reg = <0x01000000 0x02000000>;
+		};
+	};
+
+	cpld at 1,0 {
+		compatible = "hisilicon,hip05-cpld";
+		reg = <1 0x0 0x100>;
+	};
+};
arch/arm64/boot/dts/hisilicon/hip05.dtsi +6 -0
index 52d06ab..bf322ed 100644
@@ -327,6 +327,12 @@
 			status = "disabled";
 		};
 
+		lbc: localbus at 80380000 {
+			compatible = "hisilicon,hisi-localbus", "simple-bus";
+			reg = <0x0 0x80380000 0x0 0x10000>;
+			status = "disabled";
+		};
+
 		peri_gpio0: gpio at 802e0000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
Signature · 1 line
1.7.12.4
maintainer
#3 lore raw

v2 cover arm64: hisilicon: hip05 fix and update

In reply to Kefeng Wang

Hi Kefeng,

Quoted 7 lines · Kefeng Wang

Hip05:
- Fix its node without msi-cells
- Add nor flash node

Change since v1:
- msi-cells should be #msi-cells

Quoted 8 lines

Kefeng Wang (2):
arm64: dts: hip05: fix its node without msi-cells
arm64: dts: hip05: Add nor flash support

 arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 34 +++++++++++++++++++++++++++++
 arch/arm64/boot/dts/hisilicon/hip05.dtsi    | 10 +++++++++
 2 files changed, 44 insertions(+)

Thanks!
Applied both to the hisilicon soc tree.

Best Regards,
Wei