irqchip: lpc32xx: add LPC32xx irqchip driver

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* removed introduced optional "interrupt-controller-name" property, for users the name of a controller will be constructed from mic/sic and controller physical address,
* removed introduced optional "wakeup-sources" property, a list of mappings between a hardware interrupt and its correspondent wakeup source to exit CPU STOP mode will be discussed later on,
* other negligible changes (rewording, small letters in unit address etc.)

 .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
 1 file changed, 46 insertions(+), 24 deletions(-)

Quoted 16 lines · Vladimir Zapolskiy

NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* removed introduced optional "interrupt-controller-name" property, for users the name of a controller will be constructed from mic/sic and controller physical address,
* removed introduced optional "wakeup-sources" property, a list of mappings between a hardware interrupt and its correspondent wakeup source to exit CPU STOP mode will be discussed later on,
* other negligible changes (rewording, small letters in unit address etc.)

Quoted 2 lines

 .../interrupt-controller/nxp,lpc3220-mic.txt       | 70 ++++++++++++++--------
 1 file changed, 46 insertions(+), 24 deletions(-)

Acked-by Rob Herring <[email protected]>

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The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

Hi Vladimir,

Quoted 38 lines · Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Quoted 9 lines

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

I tested the driver on a custom LPC3250 board; I was having at least 1 interrupt generated from each source (MIC/SIC1/SIC2).

Tested-by Sylvain Lemieux <[email protected]>

Quoted 53 lines · Sylvain Lemieux

Hi Vladimir,

Quoted 38 lines · Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Quoted 9 lines

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

I tested the driver on a custom LPC3250 board; I was having at least 1 interrupt generated from each source (MIC/SIC1/SIC2).

Quoted 2 lines

Tested-by Sylvain Lemieux <[email protected]>

Thomas, Marc, Jason, Russell,

in your opinion would it be still possible to accept this change v2 2/4 for v4.7?

Quoted 54 lines · Vladimir Zapolskiy

Quoted 53 lines · Sylvain Lemieux

Hi Vladimir,

Quoted 38 lines · Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Quoted 9 lines

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

I tested the driver on a custom LPC3250 board; I was having at least 1 interrupt generated from each source (MIC/SIC1/SIC2).

Quoted 6 lines

Quoted 2 lines

Tested-by Sylvain Lemieux <[email protected]>

Thomas, Marc, Jason, Russell,

in your opinion would it be still possible to accept this change v2 2/4 for v4.7?

I'll queue them.

Quoted 62 lines · Marc Zyngier

Quoted 60 lines · Vladimir Zapolskiy

Quoted 50 lines · Sylvain Lemieux

Hi Vladimir,

Quoted 38 lines · Vladimir Zapolskiy

The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers.

This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.

Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00".

The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* added chained_irq_{enter,exit} for SIC chained handler,
* use {writel,readl}_relaxed flavour of io access functions,
* changed anchor data type to access iomem from struct irq_domain to private struct lpc32xx_irq_chip,
* do not read irq status register twice on every irq event,
* resource deallocation fixes on error path of irqchip driver init,
* removed handling of "interrupt-controller-name" property, name is constructed from mic/sic type and controller's physical address,
* minor improvements (renames, __ffs instead of ffs, etc.)

Quoted 9 lines

Many kudos to Marc for review of v1.

 arch/arm/Kconfig                |   2 +
 arch/arm/mach-lpc32xx/phy3250.c |   1 -
 drivers/irqchip/Makefile        |   1 +
 drivers/irqchip/irq-lpc32xx.c   | 238 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 241 insertions(+), 1 deletion(-)
 create mode 100644 drivers/irqchip/irq-lpc32xx.c

Quoted 5 lines

I tested the driver on a custom LPC3250 board; I was having at least 1 interrupt generated from each source (MIC/SIC1/SIC2).

Tested-by Sylvain Lemieux <[email protected]>

Thomas, Marc, Jason, Russell,

in your opinion would it be still possible to accept this change v2 2/4 for v4.7?

Quoted 2 lines

I'll queue them.

Marc, thank you in advance, please note that I ask to review/pick up only 2/4 for v4.7 ("irqchip: add LPC32xx interrupt controller driver"), DT changes are merged through arm-soc and the last 4/4 clean-up can be deferred till v4.8.

The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be used (i.e. board boots with access to userspace) with old DTS file, so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 17 deletions(-)

arch/arm/boot/dts/lpc32xx.dtsi +0 -0

index 73c4746..4570ddc 100644
@@ -92,7 +92,8 @@

arch/arm/boot/dts/lpc32xx.dtsi +12 -0

 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller at 4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller at 40010000 {

Hi Vladimir,

Quoted 23 lines · Vladimir Zapolskiy

The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be used (i.e. board boots with access to userspace) with old DTS file, so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 58 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 17 deletions(-)

arch/arm/boot/dts/lpc32xx.dtsi +0 -0

index 73c4746..4570ddc 100644
@@ -92,7 +92,8 @@

...

arch/arm/boot/dts/lpc32xx.dtsi

Quoted 11 lines

arch/arm/boot/dts/lpc32xx.dtsi +0 -6

-			/*
-			 * MIC Interrupt controller includes:
-			 *   MIC @40008000
-			 *   SIC1 @4000C000
-			 *   SIC2 @40010000
-			 */
 			mic: interrupt-controller at 40008000 {
 				compatible = "nxp,lpc3220-mic";
 				interrupt-controller;

@@ -327,6 +326,28 @@

I think your are missing one change in your patch, the mic register range should be 0x4000, not 0xC000.

Everything else is OK.

Quoted 18 lines

arch/arm/boot/dts/lpc32xx.dtsi +15 -0

 				#interrupt-cells = <2>;
 			};
 
+			sic1: interrupt-controller at 4000c000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x4000c000 0x4000>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+					     <30 IRQ_TYPE_LEVEL_LOW>;
+				};
+
+			sic2: interrupt-controller at 40010000 {
+				compatible = "nxp,lpc3220-sic";
+				reg = <0x40010000 0x4000>;
+				interrupt-controller;

Quoted 7 lines

arch/arm/boot/dts/lpc32xx.dtsi +7 -0

+				#interrupt-cells = <2>;
+
+				interrupt-parent = <&mic>;
+				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+					     <31 IRQ_TYPE_LEVEL_LOW>;
+			};
+

...

The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v2 to v3:
* fix io region size for MIC controller after moving SIC1/SIC2 controllers out,
* move MIC 'reg' property up to follow 'compatible' property.

Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be used (i.e. board boots with access to userspace) with old DTS file, so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties from all interrupt controllers,
* removed outdated comment.

 arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 18 deletions(-)

Hi Vladimir,

Quoted 20 lines · Vladimir Zapolskiy

The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v2 to v3:
* fix io region size for MIC controller after moving SIC1/SIC2 controllers out,
* move MIC 'reg' property up to follow 'compatible' property.

Changes from v1 to v2:
* squashed two step change in lpc32xx.dtsi - new irqchip driver can be used (i.e. board boots with access to userspace) with old DTS file, so there is no need to fix DTS firstly and then switch to a new driver,
* removed "interrupt-controller-name" and "wakeup-sources" properties from all interrupt controllers,
* removed outdated comment.

Quoted 3 lines

 arch/arm/boot/dts/lpc32xx.dtsi | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 42 insertions(+), 18 deletions(-)

Please use capital letter for the word ARM in the patch title.

Acked-by Sylvain Lemieux <[email protected]>

New NXP LPC32xx irq chip driver is used instead of a legacy one.

Signed-off-by Vladimir Zapolskiy <[email protected]>

---
Changes from v1 to v2:
* none, this is a new change

 arch/arm/mach-lpc32xx/Makefile |   2 +-
 arch/arm/mach-lpc32xx/irq.c    | 477 -----------------------------------------
 2 files changed, 1 insertion(+), 478 deletions(-)
 delete mode 100644 arch/arm/mach-lpc32xx/irq.c