x86: Initial ACPI support for Intel BayTrail

Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/irq.c | 4 ++++
  1 file changed, 4 insertions(+)

arch/x86/cpu/irq.c +0 -0

index 2950783..ae90b0c 100644

Hi Bin,

Quoted 15 lines · Bin Meng

Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/irq.c | 4 ++++
  1 file changed, 4 insertions(+)

arch/x86/cpu/irq.c +0 -0

index 2950783..ae90b0c 100644

arch/x86/cpu/irq.c static int create_pirq_routing_table(struct udevice · line 127

Quoted 8 lines

arch/x86/cpu/irq.c +4 -0

@@ -120,6 +120,10 @@ static int create_pirq_routing_table(struct udevice
 *dev)
 
        priv->irq_mask = fdtdec_get_int(blob, node,
                                        "intel,pirq-mask", PIRQ_BITMAP);
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       /* Reserve IRQ9 for SCI */
+       priv->irq_mask &= ~(1 << 9);
+#endif

Does it make sense to change this into using IS_ENABLED()?

        if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
                /* Reserve IRQ9 for SCI */
                priv->irq_mask &= ~(1 << 9);
        }

To drop the #ifdef here?

Quoted 35 lines · Stefan Roese

Hi Bin,

Quoted 15 lines · Bin Meng

Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode.

Signed-off-by Bin Meng <[email protected]>

---

   arch/x86/cpu/irq.c | 4 ++++
   1 file changed, 4 insertions(+)

arch/x86/cpu/irq.c +0 -0

index 2950783..ae90b0c 100644

arch/x86/cpu/irq.c static int create_pirq_routing_table(struct udevice · line 127

Quoted 8 lines

arch/x86/cpu/irq.c +4 -0

@@ -120,6 +120,10 @@ static int create_pirq_routing_table(struct udevice
 *dev)
 
         priv->irq_mask = fdtdec_get_int(blob, node,
                                         "intel,pirq-mask", PIRQ_BITMAP);
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       /* Reserve IRQ9 for SCI */
+       priv->irq_mask &= ~(1 << 9);
+#endif

Does it make sense to change this into using IS_ENABLED()?

         if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
                 /* Reserve IRQ9 for SCI */
                 priv->irq_mask &= ~(1 << 9);
         }

Quoted 2 lines

To drop the #ifdef here?

Ah, this bothers me sometimes. I see some places in U-Boot uses #ifdef but IS_ENABLED somewhere else. I am not sure what the recommended guideline of U-Boot with regard to this?

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/irq.c                                 | 25 ++++++++++++++++++++++
  arch/x86/include/asm/irq.h                         |  4 ++++
  doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
  3 files changed, 34 insertions(+)

arch/x86/cpu/irq.c +21 -0

index ae90b0c..487ac23 100644
@@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice *dev)
  		priv->ibase &= ~0xf;
  	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
  	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
  	if (!cell || len % sizeof(struct pirq_routing))
  		return -EINVAL;

@@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice *dev)
  	return 0;
  }
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+#endif
+
  int irq_router_common_init(struct udevice *dev)
  {
  	int ret;

Hi Bin,

Quoted 61 lines · Bin Meng

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/irq.c                                 | 25
++++++++++++++++++++++
  arch/x86/include/asm/irq.h                         |  4 ++++
  doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
  3 files changed, 34 insertions(+)

arch/x86/cpu/irq.c +3 -0

index ae90b0c..487ac23 100644
@@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice
 *dev)
                priv->ibase &= ~0xf;
        }
 
+       priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+       priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr",
 0);
+
        cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);

        if (!cell || len % sizeof(struct pirq_routing))
                return -EINVAL;

arch/x86/cpu/irq.c +18 -0

@@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice
 *dev)
        return 0;
  }
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static void irq_enable_sci(struct udevice *dev)
+{
+       struct irq_router *priv = dev_get_priv(dev);
+
+       if (priv->actl_8bit) {
+               /* Bit7 must be turned on to enable ACPI */
+               dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+       } else {
+               /* Write 0 to enable SCI on IRQ9 */
+               if (priv->config == PIRQ_VIA_PCI)
+                       dm_pci_write_config32(dev->parent,
 priv->actl_addr, 0);
+               else
+                       writel(0, priv->ibase + priv->actl_addr);
+       }
+}
+#endif
+
  int irq_router_common_init(struct udevice *dev)

  {
        int ret;

arch/x86/cpu/irq.c +0 -0

@@ -228,6 +249,10 @@ int irq_router_common_init(struct udevice *dev)
        pirq_route_irqs(dev, pirq_routing_table->slots,
                        get_irq_slot_count(pirq_routing_table));
 

arch/x86/cpu/irq.c int irq_router_common_init(struct udevice *dev) · line 254

Quoted 3 lines

arch/x86/cpu/irq.c +3 -0

+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       irq_enable_sci(dev);
+#endif

Again, this could also use IS_ENABLED.

Quoted 65 lines · Stefan Roese

Hi Bin,

Quoted 61 lines · Bin Meng

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

   arch/x86/cpu/irq.c                                 | 25
++++++++++++++++++++++
   arch/x86/include/asm/irq.h                         |  4 ++++
   doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
   3 files changed, 34 insertions(+)

arch/x86/cpu/irq.c +3 -0

index ae90b0c..487ac23 100644
@@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice
 *dev)
                 priv->ibase &= ~0xf;
         }
 
+       priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+       priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr",
 0);
+
         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);

         if (!cell || len % sizeof(struct pirq_routing))
                 return -EINVAL;

arch/x86/cpu/irq.c +18 -0

@@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice
 *dev)
         return 0;
   }
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static void irq_enable_sci(struct udevice *dev)
+{
+       struct irq_router *priv = dev_get_priv(dev);
+
+       if (priv->actl_8bit) {
+               /* Bit7 must be turned on to enable ACPI */
+               dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+       } else {
+               /* Write 0 to enable SCI on IRQ9 */
+               if (priv->config == PIRQ_VIA_PCI)
+                       dm_pci_write_config32(dev->parent,
 priv->actl_addr, 0);
+               else
+                       writel(0, priv->ibase + priv->actl_addr);
+       }
+}
+#endif
+
   int irq_router_common_init(struct udevice *dev)

   {
         int ret;

arch/x86/cpu/irq.c +0 -0

@@ -228,6 +249,10 @@ int irq_router_common_init(struct udevice *dev)
         pirq_route_irqs(dev, pirq_routing_table->slots,
                         get_irq_slot_count(pirq_routing_table));
 

Quoted 7 lines

arch/x86/cpu/irq.c int irq_router_common_init(struct udevice *dev) · line 254

Quoted 3 lines

arch/x86/cpu/irq.c +3 -0

+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       irq_enable_sci(dev);
+#endif

Again, this could also use IS_ENABLED.

If changing to use IS_ENABLED here, buildman reports:

05: x86: irq: Enable SCI on IRQ9
x86: + coreboot-x86 cougarcanyon2 minnowmax
chromebox_panther chromebook_samus crownbay conga-qeval20-qa3-e3845 efi-x86 bayleybay galileo chromebook_link

(quoted diff) +2 -0

+   irq_enable_sci(dev);
+   ^

w+../arch/x86/cpu/irq.c: In function 'irq_router_common_init':
w+../arch/x86/cpu/irq.c:254:3: warning: implicit declaration of function 'irq_enable_sci' [-Wimplicit-function-declaration]

This is due to irq_enable_sci() is wrapped by #ifdef CONFIG_GENERATE_ACPI_TABLE and I don't think IS_ENABLED can be used there.

Hi Bin,

Quoted 92 lines · Bin Meng

Quoted 69 lines · Stefan Roese

Hi Bin,

Quoted 64 lines · Bin Meng

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

   arch/x86/cpu/irq.c                                 | 25
++++++++++++++++++++++
   arch/x86/include/asm/irq.h                         |  4 ++++
   doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
   3 files changed, 34 insertions(+)

arch/x86/cpu/irq.c +3 -0

index ae90b0c..487ac23 100644
@@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice
 *dev)
                 priv->ibase &= ~0xf;
         }
 
+       priv->actl_8bit = fdtdec_get_bool(blob, node,
 "intel,actl-8bit");
+       priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr",
 0);
+

         cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
         if (!cell || len % sizeof(struct pirq_routing))
                 return -EINVAL;

arch/x86/cpu/irq.c +18 -0

@@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice
 *dev)
         return 0;
   }
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static void irq_enable_sci(struct udevice *dev)
+{
+       struct irq_router *priv = dev_get_priv(dev);
+
+       if (priv->actl_8bit) {
+               /* Bit7 must be turned on to enable ACPI */
+               dm_pci_write_config8(dev->parent, priv->actl_addr,
 0x80);
+       } else {
+               /* Write 0 to enable SCI on IRQ9 */
+               if (priv->config == PIRQ_VIA_PCI)
+                       dm_pci_write_config32(dev->parent,
 priv->actl_addr, 0);
+               else
+                       writel(0, priv->ibase + priv->actl_addr);
+       }
+}
+#endif
+

   int irq_router_common_init(struct udevice *dev)
   {
         int ret;

arch/x86/cpu/irq.c +0 -0

@@ -228,6 +249,10 @@ int irq_router_common_init(struct udevice *dev)
         pirq_route_irqs(dev, pirq_routing_table->slots,
                         get_irq_slot_count(pirq_routing_table));
 

Quoted 8 lines

arch/x86/cpu/irq.c int irq_router_common_init(struct udevice *dev) · line 254

Quoted 3 lines

arch/x86/cpu/irq.c +3 -0

+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       irq_enable_sci(dev);
+#endif

Again, this could also use IS_ENABLED.

If changing to use IS_ENABLED here, buildman reports:

05: x86: irq: Enable SCI on IRQ9
x86: + coreboot-x86 cougarcanyon2 minnowmax
chromebox_panther chromebook_samus crownbay conga-qeval20-qa3-e3845 efi-x86 bayleybay galileo chromebook_link

(quoted diff) +2 -0

+   irq_enable_sci(dev);
+   ^

w+../arch/x86/cpu/irq.c: In function 'irq_router_common_init':
w+../arch/x86/cpu/irq.c:254:3: warning: implicit declaration of function 'irq_enable_sci' [-Wimplicit-function-declaration]

Quoted 3 lines

This is due to irq_enable_sci() is wrapped by #ifdef CONFIG_GENERATE_ACPI_TABLE and I don't think IS_ENABLED can be used there.

Right. This only works in functions. I think the general rule is, that the #ifdef in the code itself are much worse than "just" around a whole function body. Thats why its okay (I think) to do it this way.

Quoted 101 lines · Stefan Roese

Hi Bin,

Quoted 95 lines · Bin Meng

Quoted 69 lines · Stefan Roese

Hi Bin,

Quoted 64 lines · Bin Meng

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

    arch/x86/cpu/irq.c                                 | 25
++++++++++++++++++++++
    arch/x86/include/asm/irq.h                         |  4 ++++
    doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
    3 files changed, 34 insertions(+)

arch/x86/cpu/irq.c +3 -0

index ae90b0c..487ac23 100644
@@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice
 *dev)
                  priv->ibase &= ~0xf;
          }
 
+       priv->actl_8bit = fdtdec_get_bool(blob, node,
 "intel,actl-8bit");
+       priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr",
 0);
+

          cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
          if (!cell || len % sizeof(struct pirq_routing))
                  return -EINVAL;

arch/x86/cpu/irq.c +18 -0

@@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice
 *dev)
          return 0;
    }
 
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+static void irq_enable_sci(struct udevice *dev)
+{
+       struct irq_router *priv = dev_get_priv(dev);
+
+       if (priv->actl_8bit) {
+               /* Bit7 must be turned on to enable ACPI */
+               dm_pci_write_config8(dev->parent, priv->actl_addr,
 0x80);
+       } else {
+               /* Write 0 to enable SCI on IRQ9 */
+               if (priv->config == PIRQ_VIA_PCI)
+                       dm_pci_write_config32(dev->parent,
 priv->actl_addr, 0);
+               else
+                       writel(0, priv->ibase + priv->actl_addr);
+       }
+}
+#endif
+

    int irq_router_common_init(struct udevice *dev)
    {
          int ret;

arch/x86/cpu/irq.c +0 -0

@@ -228,6 +249,10 @@ int irq_router_common_init(struct udevice *dev)
          pirq_route_irqs(dev, pirq_routing_table->slots,
                          get_irq_slot_count(pirq_routing_table));
 

Quoted 8 lines

arch/x86/cpu/irq.c int irq_router_common_init(struct udevice *dev) · line 254

Quoted 3 lines

arch/x86/cpu/irq.c +3 -0

+#ifdef CONFIG_GENERATE_ACPI_TABLE
+       irq_enable_sci(dev);
+#endif

Again, this could also use IS_ENABLED.

If changing to use IS_ENABLED here, buildman reports:

05: x86: irq: Enable SCI on IRQ9
x86: + coreboot-x86 cougarcanyon2 minnowmax
chromebox_panther chromebook_samus crownbay conga-qeval20-qa3-e3845 efi-x86 bayleybay galileo chromebook_link

(quoted diff) +2 -0

+   irq_enable_sci(dev);
+   ^

w+../arch/x86/cpu/irq.c: In function 'irq_router_common_init':
w+../arch/x86/cpu/irq.c:254:3: warning: implicit declaration of function 'irq_enable_sci' [-Wimplicit-function-declaration]

This is due to irq_enable_sci() is wrapped by #ifdef CONFIG_GENERATE_ACPI_TABLE and I don't think IS_ENABLED can be used there.

Quoted 5 lines

Right. This only works in functions. I think the general rule is, that the #ifdef in the code itself are much worse than "just" around a whole function body. Thats why its okay (I think) to do it this way.

So for this commit, leave it as it was?

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by Bin Meng <[email protected]>

---

 arch/x86/cpu/irq.c                                 | 25 ++++++++++++++++++++++
 arch/x86/include/asm/irq.h                         |  4 ++++
 doc/device-tree-bindings/misc/intel,irq-router.txt |  5 +++++
 3 files changed, 34 insertions(+)

- Remove #include <> header files.
- Remove APM_CNT register defines, which should not be here as they are SMI related.
- Remove MP_IRQ_ defines as they are duplicates of the same ones in asm/mpspec.h.
- Remove ACTL register defines, which should not be here as they are chipset specific.
- Remove functional fixed hardware defines, which are not used.
- Remove dev_scope related defines, which are not used.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/include/asm/acpi_table.h | 68 ---------------------------------------
  1 file changed, 68 deletions(-)

arch/x86/include/asm/acpi_table.h +0 -61

index 9856fa6..e82752a 100644
@@ -6,11 +6,6 @@
   * SPDX-License-Identifier: GPL-2.0+
   */
 
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
  #define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
  #define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
  #define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */

@@ -19,42 +14,6 @@
  #define OEM_REVISION	42
  #define ASL_COMPILER_REVISION	42
 
-/* IO ports to generate SMIs */
-#define APM_CNT			0xb2
-#define APM_CNT_CST_CONTROL	0x85
-#define APM_CNT_PST_CONTROL	0x80
-#define APM_CNT_ACPI_DISABLE	0x1e
-#define APM_CNT_ACPI_ENABLE	0xe1
-#define APM_CNT_MBI_UPDATE	0xeb
-#define APM_CNT_GNVS_UPDATE	0xea
-#define APM_CNT_FINALIZE	0xcb
-#define APM_CNT_LEGACY		0xcc
-#define APM_ST			0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT	0x0
-#define MP_IRQ_POLARITY_HIGH	0x1
-#define MP_IRQ_POLARITY_LOW	0x3
-#define MP_IRQ_POLARITY_MASK	0x3
-#define MP_IRQ_TRIGGER_DEFAULT	0x0
-#define MP_IRQ_TRIGGER_EDGE	0x4
-#define MP_IRQ_TRIGGER_LEVEL	0xc
-#define MP_IRQ_TRIGGER_MASK	0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL		0x00
-#define SCIS_MASK	0x07
-#define SCIS_IRQ9	0x00
-#define SCIS_IRQ10	0x01
-#define SCIS_IRQ11	0x02
-#define SCIS_IRQ20	0x04
-#define SCIS_IRQ21	0x05
-#define SCIS_IRQ22	0x06
-#define SCIS_IRQ23	0x07
-
  #define ACPI_REV_ACPI_1_0	1
  #define ACPI_REV_ACPI_2_0	1
  #define ACPI_REV_ACPI_3_0	2

@@ -105,14 +64,6 @@ enum acpi_address_space_type {
  	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
  };
 
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL	1	/* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT	1	/* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT	2	/* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD	1	/* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS	2	/* BM_STS avoidance bit */
-
  /* Access size definitions for Generic address structure */
  enum acpi_address_space_size {
  	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */

@@ -172,25 +123,6 @@ struct acpi_madt {
  	u32 flags;			/* Multiple APIC flags */
  } acpi_madt_t;
 
-enum dev_scope_type {
-	SCOPE_PCI_ENDPOINT = 1,
-	SCOPE_PCI_SUB = 2,
-	SCOPE_IOAPIC = 3,
-	SCOPE_MSI_HPET = 4
-};
-
-typedef struct dev_scope {
-	u8 type;
-	u8 length;
-	u8 reserved[2];
-	u8 enumeration;

Reorder the ACPI tables appearance by following the order:
RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the table flags defines accordingly.

Rearrange the routine order a little bit, to follow the order in which ACPI table is defined in acpi_table.h.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/include/asm/acpi_table.h |  14 +--
  arch/x86/lib/acpi_table.c         | 227 +++++++++++++++++++-------------------
  2 files changed, 121 insertions(+), 120 deletions(-)

arch/x86/include/asm/acpi_table.h +7 -7

index 5a829de..ad39902 100644
@@ -305,14 +305,14 @@ struct acpi_mcfg_mmconfig {
  /* These can be used by the target port */
 
  void acpi_fill_header(struct acpi_table_header *header, char *signature);
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt);
  unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
  int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags);
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
  unsigned long acpi_fill_madt(unsigned long current);
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-			 void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
-			 u16 flags, u8 lint);
  u32 write_acpi_tables(u32 start);

arch/x86/lib/acpi_table.c +107 -113

index 97d90f7..4891f20 100644
@@ -2,6 +2,7 @@
   * Based on acpi.c from coreboot
   *
   * Copyright (C) 2015, Saket Sinha <[email protected]>
+ * Copyright (C) 2016, Bin Meng <[email protected]>
   *
   * SPDX-License-Identifier: GPL-2.0+
   */

@@ -20,10 +21,85 @@
   */
  extern const unsigned char AmlCode[];
 
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = (u32)rsdt;
+
+	/*
+	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+	 *
+	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+	 * revision 0)
+	 */
+	if (xsdt == NULL) {
+		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+	} else {
+		rsdp->xsdt_address = (u64)(u32)xsdt;
+		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+	}
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+			sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &(rsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+
+	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	header->revision = ACPI_REV_ACPI_2_0;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)rsdt,
+			sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &(xsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+
+	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	header->revision = ACPI_REV_ACPI_2_0;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)xsdt,
+			sizeof(struct acpi_xsdt));
+}
+
  /**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
  static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
  {
  	int i, entries_num;

@@ -54,12 +130,12 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 
  	/* Fix RSDT length or the kernel will assume invalid entries */
  	rsdt->header.length = sizeof(struct acpi_table_header) +
-			      (sizeof(u32) * (i + 1));
+				(sizeof(u32) * (i + 1));
 
  	/* Re-calculate checksum */
  	rsdt->header.checksum = 0;
  	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-						       rsdt->header.length);
+			rsdt->header.length);
 
  	/*
  	 * And now the same thing for the XSDT. We use the same index as for

@@ -71,7 +147,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 
  		/* Fix XSDT length */
  		xsdt->header.length = sizeof(struct acpi_table_header) +
-			 (sizeof(u64) * (i + 1));
+			(sizeof(u64) * (i + 1));
 
  		/* Re-calculate checksum */
  		xsdt->header.checksum = 0;

@@ -80,12 +156,27 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
  	}
  }
 
+static void acpi_create_facs(struct acpi_facs *facs)
+{
+	memset((void *)facs, 0, sizeof(struct acpi_facs));
+
+	memcpy(facs->signature, "FACS", 4);
+	facs->length = sizeof(struct acpi_facs);
+	facs->hardware_signature = 0;
+	facs->firmware_waking_vector = 0;
+	facs->global_lock = 0;
+	facs->flags = 0;
+	facs->x_firmware_waking_vector_l = 0;
+	facs->x_firmware_waking_vector_h = 0;
+	facs->version = 1;
+}
+
  static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
  			 u8 cpu, u8 apic)
  {
-	lapic->type = ACPI_APIC_LAPIC; /* Local APIC structure */
+	lapic->type = ACPI_APIC_LAPIC;
  	lapic->length = sizeof(struct acpi_madt_lapic);
-	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
+	lapic->flags = LOCAL_APIC_FLAG_ENABLED;
  	lapic->processor_id = cpu;
  	lapic->apic_id = apic;
 

@@ -108,8 +199,8 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
  		return current;
  }
 
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base)
  {
  	ioapic->type = ACPI_APIC_IOAPIC;
  	ioapic->length = sizeof(struct acpi_madt_ioapic);

@@ -122,7 +213,7 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
  }
 
  int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags)
+				 u8 bus, u8 source, u32 gsirq, u16 flags)
  {
  	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
  	irqoverride->length = sizeof(struct acpi_madt_irqoverride);

@@ -135,7 +226,7 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
  }
 
  int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
-			 u8 cpu, u16 flags, u8 lint)
+			       u8 cpu, u16 flags, u8 lint)
  {
  	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
  	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);

@@ -146,14 +237,6 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
  	return lapic_nmi->length;
  }
 
-void acpi_fill_header(struct acpi_table_header *header, char *signature)
-{
-	memcpy(header->signature, signature, 4);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
-	memcpy(header->aslc_id, ASLC_ID, 4);
-}
-
  static void acpi_create_madt(struct acpi_madt *madt)
  {
  	struct acpi_table_header *header = &(madt->header);

@@ -180,7 +263,7 @@ static void acpi_create_madt(struct acpi_madt *madt)
  }
 
  static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
-			 u32 base, u16 seg_nr, u8 start, u8 end)
+				     u32 base, u16 seg_nr, u8 start, u8 end)
  {
  	memset(mmconfig, 0, sizeof(*mmconfig));
  	mmconfig->base_address_l = base;

@@ -196,7 +279,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
  {
  	current += acpi_create_mcfg_mmconfig
  		((struct acpi_mcfg_mmconfig *)current,
-		 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+		CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
 
  	return current;
  }

@@ -223,88 +306,6 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
  	header->checksum = table_compute_checksum((void *)mcfg, header->length);
  }
 
-static void acpi_create_facs(struct acpi_facs *facs)
-{
-	memset((void *)facs, 0, sizeof(struct acpi_facs));
-
-	memcpy(facs->signature, "FACS", 4);
-	facs->length = sizeof(struct acpi_facs);
-	facs->hardware_signature = 0;
-	facs->firmware_waking_vector = 0;
-	facs->global_lock = 0;
-	facs->flags = 0;
-	facs->x_firmware_waking_vector_l = 0;
-	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
-	struct acpi_table_header *header = &(rsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "RSDT");
-	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
-{
-	struct acpi_table_header *header = &(xsdt->header);
-
-	/* Fill out header fields */
-	acpi_fill_header(header, "XSDT");
-	header->length = sizeof(struct acpi_xsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			 struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
-	/*
-	* Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	*
-	* Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	* If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	* revision 0)
-	*/
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
-	}
-
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
-}
-
  /*
   * QEMU's version of write_acpi_tables is defined in
   * arch/x86/cpu/qemu/fw_cfg.c

@@ -378,15 +379,6 @@ u32 write_acpi_tables(u32 start)
  	acpi_create_fadt(fadt, facs, dsdt);
  	acpi_add_table(rsdp, fadt);
 
-	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
-	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
-
  	debug("ACPI:    * MADT\n");
  	madt = (struct acpi_madt *)current;
  	acpi_create_madt(madt);

@@ -396,6 +388,15 @@ u32 write_acpi_tables(u32 start)
  	}
  	current = ALIGN(current, 16);
 
+	debug("ACPI:    * MCFG\n");
+	mcfg = (struct acpi_mcfg *)current;

FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/baytrail/Makefile |   1 +
  arch/x86/cpu/baytrail/acpi.c   | 162 +++++++++++++++++++++++++++++++++++++++++
  2 files changed, 163 insertions(+)

create mode 100644 arch/x86/cpu/baytrail/acpi.c

arch/x86/cpu/baytrail/Makefile +1 -0

index 5be5491..a0216f3 100644
@@ -8,3 +8,4 @@ obj-y += cpu.o
  obj-y += early_uart.o
  obj-y += fsp_configs.o
  obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o

arch/x86/cpu/baytrail/acpi.c new file +144 -0

new file mode 100644
index 0000000..a9c79f0
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016, Bin Meng <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 3;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD |
+		ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_SEALED_CASE |
+		ACPI_FADT_S4_RTC_WAKE |
+		ACPI_FADT_PLATFORM_CLOCK;
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 128;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+u32 acpi_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+
+	irqovr = (void *)current;
+	current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);

Hi Bin,

Quoted 178 lines · Bin Meng

FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by Bin Meng <[email protected]>

---

  arch/x86/cpu/baytrail/Makefile |   1 +
  arch/x86/cpu/baytrail/acpi.c   | 162
+++++++++++++++++++++++++++++++++++++++++
  2 files changed, 163 insertions(+)

create mode 100644 arch/x86/cpu/baytrail/acpi.c

arch/x86/cpu/baytrail/Makefile +1 -0

index 5be5491..a0216f3 100644
@@ -8,3 +8,4 @@ obj-y += cpu.o
  obj-y += early_uart.o
  obj-y += fsp_configs.o
  obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o

arch/x86/cpu/baytrail/acpi.c new file +147 -0

new file mode 100644
index 0000000..a9c79f0
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2016, Bin Meng <[email protected]>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+                     void *dsdt)
+{
+       struct acpi_table_header *header = &(fadt->header);
+       u16 pmbase = ACPI_BASE_ADDRESS;
+
+       memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+       acpi_fill_header(header, "FACP");
+       header->length = sizeof(struct acpi_fadt);
+       header->revision = 3;
+
+       fadt->firmware_ctrl = (u32)facs;
+       fadt->dsdt = (u32)dsdt;
+       fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+       fadt->sci_int = 9;
+       fadt->smi_cmd = 0;
+       fadt->acpi_enable = 0;
+       fadt->acpi_disable = 0;
+       fadt->s4bios_req = 0x0;
+       fadt->pstate_cnt = 0;
+       fadt->pm1a_evt_blk = pmbase;
+       fadt->pm1b_evt_blk = 0x0;
+       fadt->pm1a_cnt_blk = pmbase + 0x4;
+       fadt->pm1b_cnt_blk = 0x0;
+       fadt->pm2_cnt_blk = pmbase + 0x50;
+       fadt->pm_tmr_blk = pmbase + 0x8;
+       fadt->gpe0_blk = pmbase + 0x20;
+       fadt->gpe1_blk = 0;
+       fadt->pm1_evt_len = 4;
+       fadt->pm1_cnt_len = 2;
+       fadt->pm2_cnt_len = 1;
+       fadt->pm_tmr_len = 4;
+       fadt->gpe0_blk_len = 16;
+       fadt->gpe1_blk_len = 0;
+       fadt->gpe1_base = 0;
+       fadt->cst_cnt = 0;
+       fadt->p_lvl3_lat = 87;
+       fadt->flush_size = 1024;
+       fadt->flush_stride = 16;
+       fadt->duty_offset = 1;
+       fadt->day_alrm = 0xd;
+       fadt->mon_alrm = 0x00;
+       fadt->century = 0x00;
+       fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+       fadt->flags = ACPI_FADT_WBINVD |
+               ACPI_FADT_C1_SUPPORTED |
+               ACPI_FADT_SLEEP_BUTTON |
+               ACPI_FADT_RESET_REGISTER |
+               ACPI_FADT_SEALED_CASE |
+               ACPI_FADT_S4_RTC_WAKE |
+               ACPI_FADT_PLATFORM_CLOCK;
+       fadt->reset_reg.space_id = 1;
+       fadt->reset_reg.bit_width = 8;
+       fadt->reset_reg.bit_offset = 0;
+       fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+       fadt->reset_reg.addrl = 0xcf9;
+       fadt->reset_reg.addrh = 0;
+       fadt->reset_value = 6;
+       fadt->x_firmware_ctl_l = (u32)facs;
+       fadt->x_firmware_ctl_h = 0;
+       fadt->x_dsdt_l = (u32)dsdt;
+       fadt->x_dsdt_h = 0;
+
+       fadt->x_pm1a_evt_blk.space_id = 1;
+       fadt->x_pm1a_evt_blk.bit_width = 32;
+       fadt->x_pm1a_evt_blk.bit_offset = 0;
+       fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+       fadt->x_pm1a_evt_blk.addrl = pmbase;
+       fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+       fadt->x_pm1b_evt_blk.space_id = 1;
+       fadt->x_pm1b_evt_blk.bit_width = 0;
+       fadt->x_pm1b_evt_blk.bit_offset = 0;
+       fadt->x_pm1b_evt_blk.access_size = 0;
+       fadt->x_pm1b_evt_blk.addrl = 0x0;
+       fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+       fadt->x_pm1a_cnt_blk.space_id = 1;
+       fadt->x_pm1a_cnt_blk.bit_width = 16;
+       fadt->x_pm1a_cnt_blk.bit_offset = 0;
+       fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+       fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+       fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm1b_cnt_blk.space_id = 1;
+       fadt->x_pm1b_cnt_blk.bit_width = 0;
+       fadt->x_pm1b_cnt_blk.bit_offset = 0;
+       fadt->x_pm1b_cnt_blk.access_size = 0;
+       fadt->x_pm1b_cnt_blk.addrl = 0x0;
+       fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm2_cnt_blk.space_id = 1;
+       fadt->x_pm2_cnt_blk.bit_width = 8;
+       fadt->x_pm2_cnt_blk.bit_offset = 0;
+       fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+       fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+       fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm_tmr_blk.space_id = 1;
+       fadt->x_pm_tmr_blk.bit_width = 32;
+       fadt->x_pm_tmr_blk.bit_offset = 0;
+       fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+       fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+       fadt->x_pm_tmr_blk.addrh = 0x0;
+
+       fadt->x_gpe0_blk.space_id = 1;
+       fadt->x_gpe0_blk.bit_width = 128;
+       fadt->x_gpe0_blk.bit_offset = 0;
+       fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+       fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+       fadt->x_gpe0_blk.addrh = 0x0;
+
+       fadt->x_gpe1_blk.space_id = 1;
+       fadt->x_gpe1_blk.bit_width = 0;
+       fadt->x_gpe1_blk.bit_offset = 0;
+       fadt->x_gpe1_blk.access_size = 0;
+       fadt->x_gpe1_blk.addrl = 0x0;
+       fadt->x_gpe1_blk.addrh = 0x0;
+
+       header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+u32 acpi_madt_irq_overrides(u32 current)
+{
+       struct acpi_madt_irqoverride *irqovr;
+       u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+
+       irqovr = (void *)current;
+       current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+       irqovr = (void *)current;
+       current += acpi_create_madt_irqoverride(irqovr, 0, 9, 9,

sci_flags);

arch/x86/cpu/baytrail/acpi.c new file +2 -0

+
+       return current;

arch/x86/cpu/baytrail/acpi.c line 154

Quoted 5 lines

arch/x86/cpu/baytrail/acpi.c new file +5 -0

+}
+
+u32 acpi_fill_madt(u32 current)
+{
+       current = acpi_create_madt_lapics(current);

I'm not sure if you need '+=' here?

arch/x86/cpu/baytrail/acpi.c line 159

Quoted 7 lines

arch/x86/cpu/baytrail/acpi.c new file +2 -0

+
+       current += acpi_create_madt_ioapic((struct acpi_madt_ioapic

*)current,

arch/x86/cpu/baytrail/acpi.c new file +3 -0

+                       2, IO_APIC_ADDR, 0);
+
+       current = acpi_madt_irq_overrides(current);

Here '+=' definitely seems to be necessary.