imx6: cache: disable L2 before touching Auxiliary Control Register

From: Peng Fan <[email protected]>

According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang.

Signed-off-by Peng Fan <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Fabio Estevam <[email protected]>

---
 arch/arm/imx-common/cache.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

arch/arm/imx-common/cache.c +6 -0

index 54b021c..b775488 100644
@@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
 
 
 	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
 	 * accesses as Cacheable no-allocate.