tegra: Move tegra20 towards the 'new' display bindings
Subsystems (4)
v2 cover tegra: Move tegra20 towards the 'new' display bindings
The original tegra20 display driver was written before Linux had device tree bindings for display. Since then Linux has developed a robust set of bindings covering various aspects of enabling a display.
This series moves closer to those bindings by using the panel and backlight as separate drivers. The device tree files for seaboard, ventana and harmony thereby become almost the same as Linux.
Unfortunately this breaks the other boards, which will need a similar sync. So I'm not sure how easy it will be to accept this series. Still, it seems worth sending it out in the hope that board maintainers can help. I have kept this series separate so that it can progress separately.
Changes in v2:
- Add new patch to add a copyright header and header guard to errno.h
- Add new patch to allow errno_str() to be used without CONFIG_ERRNO_STR
- Rebase to master
- Update harmony and ventana also
- Don't enable CONFIG_ERRNO_STR for each board
Simon Glass (6):
errno: Add copyright header and header guard
errno: Allow errno_str() to be used without CONFIG_ERRNO_STR
tegra: dts: Sync tegra20 device tree files with Linux
video: tegra: Move to using simple-panel and pwm-backlight
tegra: video: Always use write-through cache on LCD
fdt: Drop some unused compatible strings
arch/arm/dts/tegra20-harmony.dts | 751 ++++++++++++++++++++++++++++-- arch/arm/dts/tegra20-seaboard.dts | 934 ++++++++++++++++++++++++++++++++++---- arch/arm/dts/tegra20-ventana.dts | 685 ++++++++++++++++++++++++++-- configs/colibri_t20_defconfig | 3 + configs/harmony_defconfig | 3 + configs/medcom-wide_defconfig | 3 + configs/paz00_defconfig | 3 + configs/seaboard_defconfig | 3 + configs/tec_defconfig | 3 + configs/ventana_defconfig | 3 + drivers/video/tegra.c | 333 +++----------- include/errno.h | 12 + include/fdtdec.h | 4 - lib/fdtdec.c | 4 - 14 files changed, 2312 insertions(+), 432 deletions(-)
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 1/6 errno: Add copyright header and header guard
Bring in a copyright for this file from cmd/pmic.c since this file was submitted by the same author at around the same time. Also fix the missing header guard.
---
Changes in v2:
- Add new patch to add a copyright header and header guard to errno.h
include/errno.h | 7 +++++++ 1 file changed, 7 insertions(+)
include/errno.h +7 -0
@@ -1,4 +1,11 @@ +/* +* Copyright (C) 2014 Samsung Electronics +* Przemyslaw Marczak <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ #ifndef _ERRNO_H +#define _ERRNO_H#include <asm-generic/errno.h>
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 2/6 errno: Allow errno_str() to be used without CONFIG_ERRNO_STR
In reply to Simon GlassThe pmic framework uses errno_str() and this requires board that use it to enable CONFIG_ERRNO_STR to avoid a build error. Update the header to provide a NULL error message when CONFIG_ERRNO_STR is not defined, and fix the build error.
This will show as "(null)" when U-Boot prints it.
---
Changes in v2:
- Add new patch to allow errno_str() to be used without CONFIG_ERRNO_STR
include/errno.h | 5 +++++ 1 file changed, 5 insertions(+)
include/errno.h +5 -0
@@ -15,5 +15,10 @@ extern int errno;#ifdef CONFIG_ERRNO_STR const char *errno_str (int errno); +#else +static inline const char *errno_str (int errno) +{ +return 0 ; +}#endif #endif /* _ERRNO_H */
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 3/6 tegra: dts: Sync tegra20 device tree files with Linux
In reply to Simon GlassSync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot.
---
Changes in v2:
- Rebase to master
- Update harmony and ventana also
arch/arm/dts/tegra20-harmony.dts | 703 +++++++++++++++++++++++++++++- arch/arm/dts/tegra20-seaboard.dts | 889 +++++++++++++++++++++++++++++++++++--- arch/arm/dts/tegra20-ventana.dts | 635 ++++++++++++++++++++++++++- 3 files changed, 2154 insertions(+), 73 deletions(-)
arch/arm/dts/tegra20-harmony.dts +700 -3
@@ -1,5 +1,6 @@ /dts-v1/; +#include <dt-bindings/input/input.h> #include "tegra20.dtsi" / {
@@ -11,6 +12,9 @@ }; aliases { + rtc0 = "/i2c at 7000d000/tps6586x at 34"; + rtc1 = "/rtc at 7000e000"; + serial0 = &uartd; usb0 = "/usb at c5008000"; usb1 = "/usb at c5004000"; sdhci0 = "/sdhci at c8000600";
@@ -30,12 +34,276 @@ nvidia,panel = <&lcd_panel>; }; }; + + hdmi at 54280000 { + status = "okay"; + + hdmi-supply = <&vdd_5v0_hdmi>; + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + pinmux at 70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + }; + }; + }; + + i2s at 70002800 { + status = "okay"; }; serial at 70006300 { + status = "okay"; clock-frequency = < 216000000 >; }; + pwm: pwm at 7000a000 { + status = "okay"; + }; + + i2c at 7000c000 { + status = "okay"; + clock-frequency = <400000>; + + wm8903: wm8903 at 1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; + }; + }; + nand-controller at 70008000 { nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; nvidia,width = <8>;
@@ -46,15 +314,319 @@ }; }; + hdmi_ddc: i2c at 7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c at 7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c at 7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: tps6586x at 34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_reg>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + pci_clk_reg: ldo0 { + regulator-name = "vdd_ldo0,vddio_pex_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + temperature-sensor at 4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + kbc at 7000e200 { + status = "okay"; + nvidia,debounce-delay-ms = <2>; + nvidia,repeat-delay-ms = <160>; + nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; + linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) + MATRIX_KEY(0x00, 0x03, KEY_S) + MATRIX_KEY(0x00, 0x04, KEY_A) + MATRIX_KEY(0x00, 0x05, KEY_Z) + MATRIX_KEY(0x00, 0x07, KEY_FN) + MATRIX_KEY(0x01, 0x07, KEY_MENU) + MATRIX_KEY(0x02, 0x06, KEY_LEFTALT) + MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT) + MATRIX_KEY(0x03, 0x00, KEY_5) + MATRIX_KEY(0x03, 0x01, KEY_4) + MATRIX_KEY(0x03, 0x02, KEY_R) + MATRIX_KEY(0x03, 0x03, KEY_E) + MATRIX_KEY(0x03, 0x04, KEY_F) + MATRIX_KEY(0x03, 0x05, KEY_D) + MATRIX_KEY(0x03, 0x06, KEY_X) + MATRIX_KEY(0x04, 0x00, KEY_7) + MATRIX_KEY(0x04, 0x01, KEY_6) + MATRIX_KEY(0x04, 0x02, KEY_T) + MATRIX_KEY(0x04, 0x03, KEY_H) + MATRIX_KEY(0x04, 0x04, KEY_G) + MATRIX_KEY(0x04, 0x05, KEY_V) + MATRIX_KEY(0x04, 0x06, KEY_C) + MATRIX_KEY(0x04, 0x07, KEY_SPACE) + MATRIX_KEY(0x05, 0x00, KEY_9) + MATRIX_KEY(0x05, 0x01, KEY_8) + MATRIX_KEY(0x05, 0x02, KEY_U) + MATRIX_KEY(0x05, 0x03, KEY_Y) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x05, 0x05, KEY_N) + MATRIX_KEY(0x05, 0x06, KEY_B) + MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) + MATRIX_KEY(0x06, 0x00, KEY_MINUS) + MATRIX_KEY(0x06, 0x01, KEY_0) + MATRIX_KEY(0x06, 0x02, KEY_O) + MATRIX_KEY(0x06, 0x03, KEY_I) + MATRIX_KEY(0x06, 0x04, KEY_L) + MATRIX_KEY(0x06, 0x05, KEY_K) + MATRIX_KEY(0x06, 0x06, KEY_COMMA) + MATRIX_KEY(0x06, 0x07, KEY_M) + MATRIX_KEY(0x07, 0x01, KEY_EQUAL) + MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) + MATRIX_KEY(0x07, 0x03, KEY_ENTER) + MATRIX_KEY(0x07, 0x07, KEY_MENU) + MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT) + MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT) + MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL) + MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL) + MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) + MATRIX_KEY(0x0B, 0x01, KEY_P) + MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) + MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) + MATRIX_KEY(0x0B, 0x04, KEY_SLASH) + MATRIX_KEY(0x0B, 0x05, KEY_DOT) + MATRIX_KEY(0x0C, 0x00, KEY_F10) + MATRIX_KEY(0x0C, 0x01, KEY_F9) + MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) + MATRIX_KEY(0x0C, 0x03, KEY_3) + MATRIX_KEY(0x0C, 0x04, KEY_2) + MATRIX_KEY(0x0C, 0x05, KEY_UP) + MATRIX_KEY(0x0C, 0x06, KEY_PRINT) + MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) + MATRIX_KEY(0x0D, 0x00, KEY_INSERT) + MATRIX_KEY(0x0D, 0x01, KEY_DELETE) + MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) + MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) + MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) + MATRIX_KEY(0x0D, 0x06, KEY_DOWN) + MATRIX_KEY(0x0D, 0x07, KEY_LEFT) + MATRIX_KEY(0x0E, 0x00, KEY_F11) + MATRIX_KEY(0x0E, 0x01, KEY_F12) + MATRIX_KEY(0x0E, 0x02, KEY_F8) + MATRIX_KEY(0x0E, 0x03, KEY_Q) + MATRIX_KEY(0x0E, 0x04, KEY_F4) + MATRIX_KEY(0x0E, 0x05, KEY_F3) + MATRIX_KEY(0x0E, 0x06, KEY_1) + MATRIX_KEY(0x0E, 0x07, KEY_F7) + MATRIX_KEY(0x0F, 0x00, KEY_ESC) + MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) + MATRIX_KEY(0x0F, 0x02, KEY_F5) + MATRIX_KEY(0x0F, 0x03, KEY_TAB) + MATRIX_KEY(0x0F, 0x04, KEY_F1) + MATRIX_KEY(0x0F, 0x05, KEY_F2) + MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) + MATRIX_KEY(0x0F, 0x07, KEY_F6) + MATRIX_KEY(0x14, 0x00, KEY_KP7) + MATRIX_KEY(0x15, 0x00, KEY_KP9) + MATRIX_KEY(0x15, 0x01, KEY_KP8) + MATRIX_KEY(0x15, 0x02, KEY_KP4) + MATRIX_KEY(0x15, 0x04, KEY_KP1) + MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) + MATRIX_KEY(0x16, 0x02, KEY_KP6) + MATRIX_KEY(0x16, 0x03, KEY_KP5) + MATRIX_KEY(0x16, 0x04, KEY_KP3) + MATRIX_KEY(0x16, 0x05, KEY_KP2) + MATRIX_KEY(0x16, 0x07, KEY_KP0) + MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) + MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) + MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) + MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) + MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) + MATRIX_KEY(0x1D, 0x03, KEY_HOME) + MATRIX_KEY(0x1D, 0x04, KEY_END) + MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) + MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) + MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) + MATRIX_KEY(0x1E, 0x02, KEY_MUTE) + MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>; + }; + + pmc at 7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <5000>; + nvidia,cpu-pwr-off-time = <5000>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <3875>; + nvidia,sys-clock-req-active-high; + }; + + pcie-controller at 80003000 { + status = "okay"; + + avdd-pex-supply = <&pci_vdd_reg>; + vdd-pex-supply = <&pci_vdd_reg>; + avdd-pex-pll-supply = <&pci_vdd_reg>; + avdd-plle-supply = <&pci_vdd_reg>; + vddio-pex-clk-supply = <&pci_clk_reg>; + + pci at 1,0 { + status = "okay"; + }; + + pci at 2,0 { + status = "okay"; + }; + }; + + usb at c5000000 { + status = "okay"; + }; + + usb-phy at c5000000 { + status = "okay"; + }; + usb at c5004000 { - statuc = "okay"; + status = "okay"; nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; }; + usb-phy at c5004000 { + status = "okay"; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; + }; + usb at c5008000 { status = "okay"; }; + usb-phy at c5008000 { + status = "okay"; + }; + sdhci at c8000200 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -71,6 +643,17 @@ bus-width = <8>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>;
@@ -84,8 +667,15 @@ }; }; - pwm: pwm at 7000a000 { - status = "okay"; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; }; lcd_panel: panel {
@@ -112,4 +702,111 @@ GPIO_ACTIVE_HIGH>; nvidia,panel-timings = <0 0 200 0 0>; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_reg: regulator at 0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + regulator at 1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "vdd_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + }; + + regulator at 2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + pci_vdd_reg: regulator at 3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_1v05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_pnl_reg: regulator at 4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator at 5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_hdmi: regulator at 6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "VDDIO_HDMI"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_reg>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "NVIDIA Tegra Harmony"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) + GPIO_ACTIVE_HIGH>; + nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) + GPIO_ACTIVE_HIGH>; + nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) + GPIO_ACTIVE_HIGH>; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; };
arch/arm/dts/tegra20-seaboard.dts +822 -67
996 lines not on this page · raw message
arch/arm/dts/tegra20-ventana.dts +632 -3
677 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 3/6 tegra: dts: Sync tegra20 device tree files with Linux
Quoted 2 lines · Simon Glass
Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot.
I'd rather be a bit more careful here, and only import the DT nodes directly related to display output.
This change brings in a slew of other nodes that aren't used by U-Boot (something we've historically explicitly avoided) such as pinctrl, audio, Tegra KBC, I2C mux, & regulators.
It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, and I think USB for all boards), and at least Harmony's USB nodes don't seem to match what's in the kernel so I'm not sure where the DT content came from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer rather than GPIO_ACTIVE_LOW, which is present in at least the most recent kernel release (v4.5).
Splitting this up a bit or limiting it to just display-related nodes would make it easier to debug any issues that crop up with the sync. Also, have we made an explicit decision to change the policy of only including DT nodes that U-Boot actually uses, rather than simply copying the entire kernel DT into U-Boot? I'm pretty sure that some board(s) have deliberate differences in areas other than display, e.g. since U-Boot doesn't (or at least didn't) support pinctrl-based I2C muxed which are used on some Tegra20 boards in the kernel at least, and hence U-Boot likely either disabled those I2C ports or picked an explicit pinmux configuration to hard-code to.
PATCH v2 3/6 tegra: dts: Sync tegra20 device tree files with Linux
Hi Stephen,
Quoted 7 lines · Stephen Warren
Quoted 4 lines · Simon Glass
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.
Quoted 6 lines
I'd rather be a bit more careful here, and only import the DT nodes directly related to display output.
This change brings in a slew of other nodes that aren't used by U-Boot (something we've historically explicitly avoided) such as pinctrl, audio, Tegra KBC, I2C mux, & regulators.
I believe that audio, KBC and regulators are used.
Quoted 7 lines
It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, and I think USB for all boards), and at least Harmony's USB nodes don't seem to match what's in the kernel so I'm not sure where the DT content came from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer rather than
GPIO_ACTIVE_LOW, which is present in at least the most recent kernel release (v4.5).
This was against v4.4, but I may have messed up the merge in some cases. since I had to change the addresses from 64 bit.
Quoted 10 lines
Splitting this up a bit or limiting it to just display-related nodes would make it easier to debug any issues that crop up with the sync. Also, have we made an explicit decision to change the policy of only including DT nodes that U-Boot actually uses, rather than simply copying the entire kernel DT into U-Boot? I'm pretty sure that some board(s) have deliberate differences in areas other than display, e.g. since U-Boot doesn't (or at least didn't) support pinctrl-based I2C muxed which are used on some Tegra20 boards in the kernel at least, and hence U-Boot likely either disabled those I2C ports or picked an explicit pinmux configuration to hard-code to.
I think I know what you mean, and I don't believe that actually affects any I2C ports that are used in U-Boot. Do you have any example?
I'd rather have the DT completely in sync, so far as can be done. We have this merge window to find problems. I don't see a big benefit to leaving stuff out...at least with other boards we've defaulted to just bringing everything in.
Are we mostly talking about the pinmux stuff?
Regards,
Simon
PATCH v2 3/6 tegra: dts: Sync tegra20 device tree files with Linux
Quoted 10 lines · Simon Glass
Hi Stephen,
Quoted 7 lines · Stephen Warren
Quoted 4 lines · Simon Glass
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.
Quoted 8 lines
Quoted 6 lines
I'd rather be a bit more careful here, and only import the DT nodes directly related to display output.
This change brings in a slew of other nodes that aren't used by U-Boot (something we've historically explicitly avoided) such as pinctrl, audio, Tegra KBC, I2C mux, & regulators.
I believe that audio, KBC and regulators are used.
Audio and regulators certainly aren't used by mainline U-Boot; we don't have any audio drivers and IIRC we don't have any regulators instantiated in the DTs currently in U-Boot for Tegra devices.
Quoted 9 lines
Quoted 6 lines
It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C, and I think USB for all boards), and at least Harmony's USB nodes don't seem to match what's in the kernel so I'm not sure where the DT content came from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer rather than
GPIO_ACTIVE_LOW, which is present in at least the most recent kernel release (v4.5).This was against v4.4, but I may have messed up the merge in some cases. since I had to change the addresses from 64 bit.
It looks like that particular change was made in v3.11 in the kernel.
Quoted 10 lines
Quoted 9 lines
Splitting this up a bit or limiting it to just display-related nodes would make it easier to debug any issues that crop up with the sync. Also, have we made an explicit decision to change the policy of only including DT nodes that U-Boot actually uses, rather than simply copying the entire kernel DT into U-Boot? I'm pretty sure that some board(s) have deliberate differences in areas other than display, e.g. since U-Boot doesn't (or at least didn't) support pinctrl-based I2C muxed which are used on some Tegra20 boards in the kernel at least, and hence U-Boot likely either disabled those I2C ports or picked an explicit pinmux configuration to hard-code to.
Quoted 3 lines
I think I know what you mean, and I don't believe that actually affects any I2C ports that are used in U-Boot. Do you have any example?
In tegra20-seaboard.dts, the kernel DT has a pinctrl-based I2C mux on controller /i2c at 7000c400, whereas U-Boot has that I2C controller routed to some fixed pinctrl setting, and is currently enabled. Thinking more about this, since the i2c-mux-pinctrl node won't currently be processed by U-Boot in any way, since there is no driver for it, that mux node shouldn't affect the I2C controller's operation any way in U-Boot, so everything should work out fine.
tegra20-ventana.dts has an i2c-mux-pinctrl node in the kernel DT, but the I2C controller isn't enabled in U-Boot, so there should be no possibility of regression.
tegra20-tamonten.dtsi already has the i2c-mux-pinctrl node in the U-Boot DT without issue.
Quoted 6 lines
I'd rather have the DT completely in sync, so far as can be done. We have this merge window to find problems. I don't see a big benefit to leaving stuff out...at least with other boards we've defaulted to just bringing everything in.
Are we mostly talking about the pinmux stuff?
I guess keeping the DT completely in sync, or as close as possible, will simply future comparisons. However, I have the following concerns, especially just doing it all at once:
1) This likely enables a lot more devices. In particular, there are certainly I2C controllers enabled in some kernel DTs that aren't enabled in U-Boot DTs yet, since we simply haven't needed them. Likewise, we don't instantiate complete regulator drivers (at least for Tegra) in (m)any cases in U-Boot. In theory, this will not cause any issue. However, there might be bugs such as:
* The clock driver doesn't correctly support/implement certain clocks/resets we haven't yet happened to use. This is quite likely.
* I2C controller driver is broken and doesn't call the clock driver with the correct parameters to enable clock and release reset for some controllers we haven't used yet. This is less likely.
* pinmux may not be set up correctly for controllers we haven't used yet. This is especially likely on older boards where U-Boot only partially programs the pinmux for controllers known to be used, rather than programming the entire thing at once to the final configuration. Hopefully this won't cause any issues, but in the worst case it could cause some individual controller to malfunction, which just perhaps could impact some other part of the system.
* Hopefully any regulator driver doesn't touch the HW unless explicitly requested to by some client, so hopefully we don't end up with rails being explicitly disabled at boot, this preventing HW from operating when it worked fine without the driver.
2) There are some bindings that are different between U-Boot and the kernel. One obvious example is the Tegra USB controller, which has a single "usb" node in U-Boot but separate "usb" and "usb-phy" nodes in the kernel. This change doesn't look backwards-compatible, since e.g. the vbus-supply node moved from the "usb" node (which U-Boot currently processes) to the "usb-phy" node (which U-Boot does not know about).
There are probably other more minor examples of similar issues.
3) Having all HW represented in the DTs in U-Boot is certainly a change in policy at least for Tegra. I hope it won't give the impression incorrect that U-Boot actually processes all those DT nodes and uses them as an information source. This is mainly just a mind-set change though, so shouldn't be too much of an issue.
To address your last question above: pinctrl is one obvious example where this wouldn't be true. Regulators are another. Neither of those currently have any DT integration in U-Boot, for Tegra at least. Clocks and resets are only partially integrated with DT; the clock/reset IDs are parsed from properties in client nodes, but the provider side nodes are entirely ignored.
Due to all that, I'd still strongly prefer this patch only sync the display-related nodes in order to limit and possible fall-out to display functionality; the topic of the series.
I'm fine with syncing the other nodes too, where possible. However, I'd like to see the sync split up into a variety of separate patches, likely based on node/HW type, to make "git bisect" easier in the face of any problems that crop up. Nothing would be more annoying than trying to debug an issue with display not working but being unable to do so because a new I2C controller's driver was causing the system to hard-hang by touching an unclocked register. Equally, just blindly syncing the entire DT content isn't going to work e.g. due to the USB binding differences I mentioned.
In summary, perhaps we can have a patch series like:
* Add/update all I2C nodes
* Add/update all MMC nodes
* Add/update all USB nodes
* Add/update all PCIe nodes
* Add/update all host1x/display/LCD/... nodes
* Add/update any misc nodes
* Add all nodes for which we know there's no kernel driver
That will make it much easier to debug any problems that do arise.
PATCH v2 3/6 tegra: dts: Sync tegra20 device tree files with Linux
Hi Stephen,
Quoted 25 lines · Stephen Warren
Quoted 24 lines · Simon Glass
Hi Stephen,
Quoted 18 lines · Stephen Warren
Quoted 6 lines · Simon Glass
Sync everything except the display panel, which will come in a future patch.
One USB port is left disabled since we don't want to support it in U-Boot.I'd rather be a bit more careful here, and only import the DT nodes directly
related to display output.This change brings in a slew of other nodes that aren't used by U-Boot (something we've historically explicitly avoided) such as pinctrl, audio, Tegra KBC, I2C mux, & regulators.
Quoted 6 lines
Quoted 1 line
I believe that audio, KBC and regulators are used.
Audio and regulators certainly aren't used by mainline U-Boot; we don't have any audio drivers and IIRC we don't have any regulators instantiated in the DTs currently in U-Boot for Tegra devices.
Regulators are used by the new LCD support. Yes you are right about audio.
Quoted 89 lines
Quoted 11 lines
Quoted 9 lines
It also doesn't sync the /aliases node with the kernel (e.g. Seaboard I2C,
and I think USB for all boards), and at least Harmony's USB nodes don't seem
to match what's in the kernel so I'm not sure where the DT content came from, e.g. consider usb at c5004000's nvidia,phy-reset-gpio used an integer rather thanGPIO_ACTIVE_LOW, which is present in at least the most recent kernel release (v4.5).Quoted 2 lines
This was against v4.4, but I may have messed up the merge in some cases. since I had to change the addresses from 64 bit.
It looks like that particular change was made in v3.11 in the kernel.
Quoted 18 lines
Quoted 8 lines
Splitting this up a bit or limiting it to just display-related nodes would
make it easier to debug any issues that crop up with the sync. Also, have we
made an explicit decision to change the policy of only including DT nodes that U-Boot actually uses, rather than simply copying the entire kernel DT
into U-Boot? I'm pretty sure that some board(s) have deliberateQuoted 8 lines
differences
in areas other than display, e.g. since U-Boot doesn't (or at least didn't)
support pinctrl-based I2C muxed which are used on some Tegra20 boards in the
kernel at least, and hence U-Boot likely either disabled those I2C ports or
picked an explicit pinmux configuration to hard-code to.Quoted 3 lines
I think I know what you mean, and I don't believe that actually affects any I2C ports that are used in U-Boot. Do you have any example?
In
tegra20-seaboard.dts, the kernel DT has a pinctrl-based I2C mux on controller /i2c at7000c400, whereas U-Boot has that I2C controller routed to some fixed pinctrl setting, and is currently enabled. Thinking more about this, since the i2c-mux-pinctrl node won't currently be processed by U-Boot in any way, since there is no driver for it, that mux node shouldn't affect the I2C controller's operation any way in U-Boot, so everything should work out fine.
tegra20-ventana.dtshas an i2c-mux-pinctrl node in the kernel DT, but the I2C controller isn't enabled in U-Boot, so there should be no possibility of regression.
tegra20-tamonten.dtsialready has the i2c-mux-pinctrl node in the U-Boot DT without issue.Quoted 6 lines
I'd rather have the DT completely in sync, so far as can be done. We have this merge window to find problems. I don't see a big benefit to leaving stuff out...at least with other boards we've defaulted to just bringing everything in.
Are we mostly talking about the pinmux stuff?
I guess keeping the DT completely in sync, or as close as possible, will simply future comparisons. However, I have the following concerns, especially just doing it all at once:
1) This likely enables a lot more devices. In particular, there are certainly I2C controllers enabled in some kernel DTs that aren't enabled in U-Boot DTs yet, since we simply haven't needed them. Likewise, we don't instantiate complete regulator drivers (at least for Tegra) in (m)any cases in U-Boot. In theory, this will not cause any issue. However, there might be bugs such as:
* The clock driver doesn't correctly support/implement certain clocks/resets we haven't yet happened to use. This is quite likely.
* I2C controller driver is broken and doesn't call the clock driver with the correct parameters to enable clock and release reset for some controllers we haven't used yet. This is less likely.
* pinmux may not be set up correctly for controllers we haven't used yet. This is especially likely on older boards where U-Boot only partially programs the pinmux for controllers known to be used, rather than programming the entire thing at once to the final configuration. Hopefully this won't cause any issues, but in the worst case it could cause some individual controller to malfunction, which just perhaps could impact some other part of the system.
Quoted 4 lines
* Hopefully any regulator driver doesn't touch the HW unless explicitly requested to by some client, so hopefully we don't end up with rails being explicitly disabled at boot, this preventing HW from operating when it worked fine without the driver.
The regulators are not used unless enabled, but they will be enabled if a display is used.
I worry that what you are saying above is that we *need* a different device tree from Linux. Would it not be better to make it the same and then fix any problems we discover?
Quoted 9 lines
2) There are some bindings that are different between U-Boot and the kernel. One obvious example is the Tegra USB controller, which has a single "usb" node in U-Boot but separate "usb" and "usb-phy" nodes in the kernel. This change doesn't look backwards-compatible, since e.g. the vbus-supply node moved from the "usb" node (which U-Boot currently processes) to the "usb-phy" node (which U-Boot does not know about).
There are probably other more minor examples of similar issues.
Hmm well that's the sort of thing I'd like to tidy up.
Quoted 7 lines
3) Having all HW represented in the DTs in U-Boot is certainly a change in policy at least for Tegra. I hope it won't give the impression incorrect that U-Boot actually processes all those DT nodes and uses them as an information source. This is mainly just a mind-set change though, so shouldn't be too much of an issue.
Quoted 6 lines
To address your last question above: pinctrl is one obvious example where this wouldn't be true. Regulators are another. Neither of those currently have any DT integration in U-Boot, for Tegra at least. Clocks and resets are only partially integrated with DT; the clock/reset IDs are parsed from properties in client nodes, but the provider side nodes are entirely ignored.
I'm hoping that you will create a pinctrl driver. Regulators are well supported in U-Boot now - please see drivers/power/regulator.
Quoted 25 lines
Due to all that, I'd still strongly prefer this patch only sync the display-related nodes in order to limit and possible fall-out to display functionality; the topic of the series.
I'm fine with syncing the other nodes too, where possible. However, I'd like to see the sync split up into a variety of separate patches, likely based on node/HW type, to make "git bisect" easier in the face of any problems that crop up. Nothing would be more annoying than trying to debug an issue with display not working but being unable to do so because a new I2C controller's driver was causing the system to hard-hang by touching an unclocked register. Equally, just blindly syncing the entire DT content isn't going to work e.g. due to the USB binding differences I mentioned.
In summary, perhaps we can have a patch series like:
* Add/update all I2C nodes
* Add/update all MMC nodes
* Add/update all USB nodes
* Add/update all PCIe nodes
* Add/update all host1x/display/LCD/... nodes
* Add/update any misc nodes
* Add all nodes for which we know there's no kernel driver
Quoted 1 line
That will make it much easier to debug any problems that do arise.
OK I'll take a look at this. Really I wish the Tegra maintainer would do this :-)
Regards,
Simon
PATCH v2 4/6 video: tegra: Move to using simple-panel and pwm-backlight
In reply to Simon GlassWe have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code.
This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings:
- colibri
- medcom-wide
- paz00
- tec
---
Changes in v2:
- Don't enable CONFIG_ERRNO_STR for each board
arch/arm/dts/tegra20-harmony.dts | 48 +++--- arch/arm/dts/tegra20-seaboard.dts | 45 +++--- arch/arm/dts/tegra20-ventana.dts | 54 +++---- configs/colibri_t20_defconfig | 3 + configs/harmony_defconfig | 3 + configs/medcom-wide_defconfig | 3 + configs/paz00_defconfig | 3 + configs/seaboard_defconfig | 3 + configs/tec_defconfig | 3 + configs/ventana_defconfig | 3 + drivers/video/tegra.c | 312 ++++++-------------------------------- 11 files changed, 145 insertions(+), 335 deletions(-)
arch/arm/dts/tegra20-harmony.dts +24 -24
@@ -31,7 +31,23 @@ status = "okay"; rgb { status = "okay"; - nvidia,panel = <&lcd_panel>; + + nvidia,panel = <&panel>; + + display-timings { + timing at 0 { + /* Seaboard has 1366x768 */ + clock-frequency = <42430000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <138>; + hfront-porch = <34>; + hsync-len = <136>; + vback-porch = <21>; + vfront-porch = <4>; + vsync-len = <4>; + }; + }; }; };
@@ -678,29 +694,13 @@ }; }; - lcd_panel: panel { - clock = <42430000>; - xres = <1024>; - yres = <600>; - left-margin = <138>; - right-margin = <34>; - hsync-len = <136>; - lower-margin = <4>; - upper-margin = <21>; - vsync-len = <4>; - hsync-active-high; - vsyncx-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(B, 5) - GPIO_ACTIVE_HIGH>; - nvidia,lvds-shutdown-gpios = <&gpio TEGRA_GPIO(B, 2) - GPIO_ACTIVE_HIGH>; - nvidia,backlight-vdd-gpios = <&gpio TEGRA_GPIO(W, 0) - GPIO_ACTIVE_HIGH>; - nvidia,panel-vdd-gpios = <&gpio TEGRA_GPIO(C, 6) - GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <0 0 200 0 0>; + panel: panel { + compatible = "auo,b101aw03", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; }; regulators {
arch/arm/dts/tegra20-seaboard.dts +23 -22
57 lines not on this page · raw message
arch/arm/dts/tegra20-ventana.dts +28 -26
72 lines not on this page · raw message
configs/colibri_t20_defconfig +3 -0
@@ -23,6 +23,8 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -30,6 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/harmony_defconfig +3 -0
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/medcom-wide_defconfig +3 -0
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/paz00_defconfig +3 -0
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/seaboard_defconfig +3 -0
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/tec_defconfig +3 -0
@@ -21,6 +21,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -28,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
configs/ventana_defconfig +3 -0
@@ -20,6 +20,8 @@ CONFIG_CMD_DHCP=y # CONFIG_CMD_NFS is not set CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y
@@ -27,6 +29,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y
drivers/video/tegra.c +49 -263
411 lines not on this page · raw message
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 5/6 tegra: video: Always use write-through cache on LCD
In reply to Simon GlassThis seems to give the best performance, so let's use it always.
---
Changes in v2: None
drivers/video/tegra.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-)
drivers/video/tegra.c +3 -18
@@ -22,15 +22,6 @@DECLARE_GLOBAL_DATA_PTR ; -enum lcd_cache_t { -FDT_LCD_CACHE_OFF =0 , -FDT_LCD_CACHE_WRITE_THROUGH =1 <<0 , -FDT_LCD_CACHE_WRITE_BACK =1 <<1 , -FDT_LCD_CACHE_FLUSH =1 <<2 , -FDT_LCD_CACHE_WRITE_BACK_FLUSH =FDT_LCD_CACHE_WRITE_BACK | -FDT_LCD_CACHE_FLUSH , -}; -/* Information about the display controller */ struct tegra_lcd_priv {int width;/* width in pixels */
@@ -41,7 +32,6 @@ struct tegra_lcd_priv {struct disp_ctlr *disp;/* Display controller to use */ fdt_addr_t frame_buffer;/* Address of frame buffer */ unsigned pixel_clock;/* Pixel clock in Hz */ -enum lcd_cache_t cache_type; };enum {
@@ -310,7 +300,6 @@ static int tegra_lcd_probe(struct udevice *dev)struct video_priv *uc_priv =dev_get_uclass_priv (dev);struct tegra_lcd_priv *priv =dev_get_priv (dev);const void *blob = gd->fdt_blob; -int type =DCACHE_OFF ;int ret;/* Initialize the Tegra display controller */
@@ -329,15 +318,11 @@ static int tegra_lcd_probe(struct udevice *dev)return ret; } -/* Set up the LCD caching as requested */ -if (priv->cache_type &FDT_LCD_CACHE_WRITE_THROUGH ) - type =DCACHE_WRITETHROUGH ; -else if (priv->cache_type &FDT_LCD_CACHE_WRITE_BACK ) - type =DCACHE_WRITEBACK ; -mmu_set_region_dcache_behaviour (priv->frame_buffer, plat->size, type); +mmu_set_region_dcache_behaviour (priv->frame_buffer, plat->size, +DCACHE_WRITETHROUGH );/* Enable flushing after LCD writes if requested */ -video_set_flush_dcache (dev, priv->cache_type &FDT_LCD_CACHE_FLUSH ); +video_set_flush_dcache (dev, true); uc_priv->xsize = priv->width; uc_priv->ysize = priv->height;
Signature · 1 line
2.8.0.rc3.226.g39d4020
PATCH v2 6/6 fdt: Drop some unused compatible strings
In reply to Simon GlassWe have driver-model drivers for some of these now, so drop them.
---
Changes in v2: None
include/fdtdec.h | 4 ---- lib/fdtdec.c | 4 ---- 2 files changed, 8 deletions(-)
include/fdtdec.h +0 -4
@@ -119,10 +119,7 @@ enum fdt_compat_id {COMPAT_NVIDIA_TEGRA20_EMC ,/* Tegra20 memory controller */ COMPAT_NVIDIA_TEGRA20_EMC_TABLE ,/* Tegra20 memory timing table */ COMPAT_NVIDIA_TEGRA20_NAND ,/* Tegra2 NAND controller */ -COMPAT_NVIDIA_TEGRA20_PWM ,/* Tegra 2 PWM controller */ -COMPAT_NVIDIA_TEGRA124_SOR ,/* Tegra 124 Serial Output Resource */ COMPAT_NVIDIA_TEGRA124_PMC ,/* Tegra 124 power mgmt controller */ -COMPAT_NVIDIA_TEGRA20_DC ,/* Tegra 2 Display controller */ COMPAT_NVIDIA_TEGRA210_SDMMC ,/* Tegra210 SDMMC controller */ COMPAT_NVIDIA_TEGRA124_SDMMC ,/* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
@@ -145,7 +142,6 @@ enum fdt_compat_id {COMPAT_SAMSUNG_EXYNOS5_DP ,/* Exynos Display port controller */ COMPAT_SAMSUNG_EXYNOS_DWMMC ,/* Exynos DWMMC controller */ COMPAT_SAMSUNG_EXYNOS_MMC ,/* Exynos MMC controller */ -COMPAT_SAMSUNG_EXYNOS_SERIAL ,/* Exynos UART */ COMPAT_MAXIM_MAX77686_PMIC ,/* MAX77686 PMIC */ COMPAT_GENERIC_SPI_FLASH ,/* Generic SPI Flash chip */ COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */
lib/fdtdec.c +0 -4
@@ -26,10 +26,7 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (NVIDIA_TEGRA20_EMC ,"nvidia,tegra20-emc" ),COMPAT (NVIDIA_TEGRA20_EMC_TABLE ,"nvidia,tegra20-emc-table" ),COMPAT (NVIDIA_TEGRA20_NAND ,"nvidia,tegra20-nand" ), -COMPAT (NVIDIA_TEGRA20_PWM ,"nvidia,tegra20-pwm" ), -COMPAT (NVIDIA_TEGRA124_SOR ,"nvidia,tegra124-sor" ),COMPAT (NVIDIA_TEGRA124_PMC ,"nvidia,tegra124-pmc" ), -COMPAT (NVIDIA_TEGRA20_DC ,"nvidia,tegra20-dc" ),COMPAT (NVIDIA_TEGRA210_SDMMC ,"nvidia,tegra210-sdhci" ),COMPAT (NVIDIA_TEGRA124_SDMMC ,"nvidia,tegra124-sdhci" ), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
@@ -50,7 +47,6 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (SAMSUNG_EXYNOS5_DP ,"samsung,exynos5-dp" ),COMPAT (SAMSUNG_EXYNOS_DWMMC ,"samsung,exynos-dwmmc" ),COMPAT (SAMSUNG_EXYNOS_MMC ,"samsung,exynos-mmc" ), -COMPAT (SAMSUNG_EXYNOS_SERIAL ,"samsung,exynos4210-uart" ),COMPAT (MAXIM_MAX77686_PMIC ,"maxim,max77686" ),COMPAT (GENERIC_SPI_FLASH ,"spi-flash" ), COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),
Signature · 1 line
2.8.0.rc3.226.g39d4020
v2 cover tegra: Move tegra20 towards the 'new' display bindings
In reply to Simon GlassQuoted 7 lines · Simon Glass
The original tegra20 display driver was written before Linux had device tree bindings for display. Since then Linux has developed a robust set of bindings covering various aspects of enabling a display.
This series moves closer to those bindings by using the panel and backlight as separate drivers. The device tree files for seaboard, ventana and harmony thereby become almost the same as Linux.
Thierry, since you're most familiar with display support and IIRC have worked on this in U-Boot too, perhaps you could review this series? Let me know if you need me to forward the emails to you.
Quoted 4 lines
Unfortunately this breaks the other boards, which will need a similar sync. So I'm not sure how easy it will be to accept this series. Still, it seems worth sending it out in the hope that board maintainers can help. I have kept this series separate so that it can progress separately.
Which boards in particular? If this is just other Tegra20 boards and simply because you haven't copied the relevant DTs from the kernel and/or made updates to any U-Boot defconfigs and/or config headers, can't you do that mechanically too? Sure you'll need other people to test boards you don't have, but IIUC the source changes are mechanical. If it's non-Tegra20 boards, can you expand on the cause of the breakage?