armv8: fsl-layerscape: Add support of LS1012A SoC and platform

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

Signed-off-by Calvin Johnson <[email protected]>

Signed-off-by Pratiyush Mohan Srivastava <[email protected]>

Signed-off-by Abhimanyu Saini <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2:
- Added support of qixis over i2c
- print fpga, board info using qixis

 arch/arm/Kconfig                              |  10 ++
 arch/arm/dts/Makefile                         |   3 +-
 arch/arm/dts/fsl-ls1012a-qds.dts              |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi             | 123 ++++++++++++++
 arch/arm/dts/fsl-ls1012a.dtsi                 | 119 ++++++++++++++
 board/freescale/ls1012aqds/Kconfig            |  15 ++
 board/freescale/ls1012aqds/MAINTAINERS        |   6 +
 board/freescale/ls1012aqds/Makefile           |   7 +
 board/freescale/ls1012aqds/README             |  94 +++++++++++
 board/freescale/ls1012aqds/ls1012aqds.c       | 220 ++++++++++++++++++++++++++
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |  35 ++++
 configs/ls1012aqds_qspi_defconfig             |  32 ++++
 include/configs/ls1012a_common.h              | 195 +++++++++++++++++++++++
 include/configs/ls1012aqds.h                  | 150 ++++++++++++++++++
 14 files changed, 1022 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
 create mode 100644 board/freescale/ls1012aqds/Kconfig
 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1012aqds/Makefile
 create mode 100644 board/freescale/ls1012aqds/README
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 create mode 100644 configs/ls1012aqds_qspi_defconfig
 create mode 100644 include/configs/ls1012a_common.h
 create mode 100644 include/configs/ls1012aqds.h

board/freescale/ls1012aqds/Makefile new file +7 -0

new file mode 100644
index 0000000..0b813f9
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o

board/freescale/ls1012aqds/README new file +0 -0

new file mode 100644
index 0000000..e94a267

board/freescale/ls1012aqds/README new file +41 -0

+
+LS1012A SoC Overview
+--------------------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer

board/freescale/ls1012aqds/README new file +38 -0

+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	? Provides MIC bias
+	? Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000

board/freescale/ls1012aqds/ls1012aqds.c new file +138 -0

new file mode 100644
index 0000000..a062c36
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+			(int)QIXIS_READ(scver), qixis_read_tag(buf),
+			(int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	/* Set MMDC_MDSCR[CON_REQ] */
+	out_be32(&mmdc->mdscr, 0x00008000);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  0x12554000);
+	out_be32(&mmdc->mdcfg0, 0xbabf7954);
+	out_be32(&mmdc->mdcfg1, 0xff328f64);
+	out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    0x00000680);
+	out_be32(&mmdc->mpmur0,    0x00000800);
+	out_be32(&mmdc->mdrwd,     0x00002000);
+	out_be32(&mmdc->mpodtctrl, 0x0000022a);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  0x00bf1023);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, 0x05180000);
+	out_be32(&mmdc->mdasp, 0x0000007f);
+
+	/* Enable MMDC */
+	out_be32(&mmdc->mdctl, 0x85180000);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, 0x00088032);
+	out_be32(&mmdc->mdscr, 0x00008033);
+	out_be32(&mmdc->mdscr, 0x00048031);
+	out_be32(&mmdc->mdscr, 0x19308030);
+
+	/* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr,	    0x04008040);
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
+
+	/* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr,   0x00848031);
+	out_be32(&mmdc->mdscr,   0x00008200);
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, 0x00048031);
+	out_be32(&mmdc->mdscr, 0x00008000);
+
+	mdelay(1);
+
+	/* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr,     0x04008050);
+	out_be32(&mmdc->mdscr,     0x00048033);
+	out_be32(&mmdc->mppdcmpr2, 0x00000001);
+	out_be32(&mmdc->mprddlctl, 0x40404040);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
+
+	out_be32(&mmdc->mdscr, 0x00008033);
+
+	/* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr,       0x04008050);
+	out_be32(&mmdc->mdscr,       0x00048033);
+	out_be32(&mmdc->mppdcmpr2,   0x00000001);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
+
+	out_be32(&mmdc->mdscr, 0x00008033);
+

board/freescale/ls1012aqds/ls1012aqds.c new file +63 -0

+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+
+	i2c_set_bus_num(0);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

board/freescale/ls1012aqds/ls1012aqds_qixis.h new file +35 -0

new file mode 100644
index 0000000..584f604
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

configs/ls1012aqds_qspi_defconfig new file +32 -0

new file mode 100644
index 0000000..2bc178c
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

include/configs/ls1012a_common.h new file +18 -0

new file mode 100644
index 0000000..855fb60
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define	CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH

include/configs/ls1012a_common.h new file +154 -0

+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		1000000
+#define CONFIG_ENV_SPI_MODE		0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
+					"$kernel_start $kernel_size && "\
+					"bootm $kernel_load"
+#define CONFIG_BOOTDELAY		10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */

include/configs/ls1012aqds.h new file +1 -0

new file mode 100644
index 0000000..584a87c
@@ -0,0 +1,150 @@
+/*

Quoted 11 lines · Prabhakar Kushwaha

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

Signed-off-by Calvin Johnson <[email protected]>

Signed-off-by Pratiyush Mohan Srivastava <[email protected]>

Signed-off-by Abhimanyu Saini <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---

Quoted 12 lines

include/configs/ls1012a_common.h new file +12 -0

+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\

include/configs/ls1012a_common.h line 176

Quoted 8 lines

include/configs/ls1012a_common.h new file +8 -0

+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
+					"$kernel_start $kernel_size && "\

include/configs/ls1012a_common.h line 28

Quoted 6 lines

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
...
+++ b/include/configs/ls1012a_common.h
...

include/configs/ls1012a_common.h new file +2 -0

+#define CONFIG_SYS_CLK_FREQ          100000000
+#define CONFIG_DDR_CLK_FREQ          125000000

Hard-coded value? Are the clocks board-specfic?

include/configs/ls1012a_common.h line 41

Quoted 3 lines

include/configs/ls1012a_common.h new file +3 -0

+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY            25000000        /* 12MHz */

Does this timer has a dedicated clock source? This should be CONFIG_SYS_CLK_FREQ/4, right? Isn't it also board-specific?

Quoted 2 lines

+++ b/include/configs/ls1012aqds.h
+#include "ls1012a_common.h"

Shouldn't sysclk/ddrclk be put here?

-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Wednesday, May 11, 2016 9:30 PM
To: Prabhakar Kushwaha <[email protected]>; u- boot at lists.denx.de
Cc: Calvin Johnson <[email protected]>; Pratiyush Srivastava <[email protected]>; Abhimanyu Saini <[email protected]>
Subject: Re: [PATCH 8/9][v2] armv8: ls1012a: Add support of ls1012aqds board

Quoted 16 lines · Prabhakar Kushwaha

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

Signed-off-by Calvin Johnson <[email protected]>

Signed-off-by Pratiyush Mohan Srivastava

<[email protected]>

Signed-off-by Abhimanyu Saini <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2:
- Added support of qixis over i2c
- print fpga, board info using qixis

Quoted 10 lines

 arch/arm/Kconfig                              |  10 ++
 arch/arm/dts/Makefile                         |   3 +-
 arch/arm/dts/fsl-ls1012a-qds.dts              |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi             | 123 ++++++++++++++
 arch/arm/dts/fsl-ls1012a.dtsi                 | 119 ++++++++++++++
 board/freescale/ls1012aqds/Kconfig            |  15 ++
 board/freescale/ls1012aqds/MAINTAINERS        |   6 +
 board/freescale/ls1012aqds/Makefile           |   7 +
 board/freescale/ls1012aqds/README             |  94 +++++++++++
 board/freescale/ls1012aqds/ls1012aqds.c       | 220

++++++++++++++++++++++++++

Quoted 3 lines

 board/freescale/ls1012aqds/ls1012aqds_qixis.h |  35 ++++
 configs/ls1012aqds_qspi_defconfig             |  32 ++++
 include/configs/ls1012a_common.h              | 195

+++++++++++++++++++++++

Quoted 15 lines

 include/configs/ls1012aqds.h                  | 150 ++++++++++++++++++
 14 files changed, 1022 insertions(+), 1 deletion(-)  create mode

100644 arch/arm/dts/fsl-ls1012a-qds.dts create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi create mode 100644 board/freescale/ls1012aqds/Kconfig

 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1012aqds/Makefile
 create mode 100644 board/freescale/ls1012aqds/README  create mode
100644 board/freescale/ls1012aqds/ls1012aqds.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 create mode 100644 configs/ls1012aqds_qspi_defconfig  create mode

100644 include/configs/ls1012a_common.h create mode 100644 include/configs/ls1012aqds.h

<snip>

board/freescale/ls1012aqds/MAINTAINERS line 6

Quoted 13 lines

board/freescale/ls1012aqds/MAINTAINERS new file +6 -0

new file mode 100644
index 0000000..3c01df6
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_defconfig

Please add maintainer name.

Quoted 20 lines

board/freescale/ls1012aqds/Makefile new file +7 -0

new file mode 100644
index 0000000..0b813f9
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o

board/freescale/ls1012aqds/README new file +0 -0

new file mode 100644
index 0000000..e94a267

board/freescale/ls1012aqds/README line 5

Quoted 6 lines

board/freescale/ls1012aqds/README new file +5 -0

@@ -0,0 +1,94 @@
+Overview
+--------
+The LS1012AQDS power supplies (PS) provide all the voltages necessary
+for the correct operation of the LS1012A processor, DDR3L, QSPI
+memory, and other onboard peripherals.

Power suppliers? That's all you have?

Quoted 47 lines

board/freescale/ls1012aqds/README new file +46 -0

+
+LS1012A SoC Overview
+--------------------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected
+L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
+
+ LS1012AQDS board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:

board/freescale/ls1012aqds/README

Quoted 6 lines

board/freescale/ls1012aqds/README new file +6 -0

+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1
+ GT/s

What memory is 6-bit?

Quoted 142 lines

board/freescale/ls1012aqds/README new file +38 -0

+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	? Provides MIC bias
+	? Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000

board/freescale/ls1012aqds/ls1012aqds.c new file +96 -0

new file mode 100644
index 0000000..a062c36
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) {
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n"); }
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+			(int)QIXIS_READ(scver), qixis_read_tag(buf),
+			(int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	/* Set MMDC_MDSCR[CON_REQ] */
+	out_be32(&mmdc->mdscr, 0x00008000);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  0x12554000);
+	out_be32(&mmdc->mdcfg0, 0xbabf7954);
+	out_be32(&mmdc->mdcfg1, 0xff328f64);
+	out_be32(&mmdc->mdcfg2, 0x01ff00db);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    0x00000680);
+	out_be32(&mmdc->mpmur0,    0x00000800);
+	out_be32(&mmdc->mdrwd,     0x00002000);
+	out_be32(&mmdc->mpodtctrl, 0x0000022a);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  0x00bf1023);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, 0x05180000);
+	out_be32(&mmdc->mdasp, 0x0000007f);
+
+	/* Enable MMDC */
+	out_be32(&mmdc->mdctl, 0x85180000);

board/freescale/ls1012aqds/ls1012aqds.c line 106

Quoted 10 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +10 -0

+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, 0x00088032);
+	out_be32(&mmdc->mdscr, 0x00008033);
+	out_be32(&mmdc->mdscr, 0x00048031);
+	out_be32(&mmdc->mdscr, 0x19308030);
+
+	/* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr,	    0x04008040);
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003,

0x00010000);

board/freescale/ls1012aqds/ls1012aqds.c

Quoted 5 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +5 -0

+
+	/* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr,   0x00848031);
+	out_be32(&mmdc->mdscr,   0x00008200);
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001,

0x00000001);

Quoted 4 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +4 -0

+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, 0x00048031);

board/freescale/ls1012aqds/ls1012aqds.c

Quoted 10 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +10 -0

+	out_be32(&mmdc->mdscr, 0x00008000);
+
+	mdelay(1);
+
+	/* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr,     0x04008050);
+	out_be32(&mmdc->mdscr,     0x00048033);
+	out_be32(&mmdc->mppdcmpr2, 0x00000001);
+	out_be32(&mmdc->mprddlctl, 0x40404040);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000,

0x10000000);

board/freescale/ls1012aqds/ls1012aqds.c

Quoted 8 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +8 -0

+
+	out_be32(&mmdc->mdscr, 0x00008033);
+
+	/* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr,       0x04008050);
+	out_be32(&mmdc->mdscr,       0x00048033);
+	out_be32(&mmdc->mppdcmpr2,   0x00000001);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010,

0x00000010);

board/freescale/ls1012aqds/ls1012aqds.c line 148

Quoted 13 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +13 -0

+
+	out_be32(&mmdc->mdscr, 0x00008033);
+
+	/* PD, SR */
+	out_be32(&mmdc->mdpdc, 0x00030035);
+	out_be32(&mmdc->mapsr, 0x00001067);
+
+	/* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
+
+	/* disable CON_REQ */
+	out_be32(&mmdc->mdscr, 0x0);
+}

Put those magic numbers into a header file and use macros. You may reuse this code someday.

board/freescale/ls1012aqds/ls1012aqds.c line 157

Quoted 9 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +9 -0

+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = 0x40000000;
+
+	return 0;
+}

Same here.

Quoted 6 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +6 -0

+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;

board/freescale/ls1012aqds/ls1012aqds.c

Quoted 10 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +10 -0

+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+
+	i2c_set_bus_num(0);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd,

1);

Quoted 155 lines

board/freescale/ls1012aqds/ls1012aqds.c new file +45 -0

+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0]; #endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd) {
+	u64 base[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+
+	/* fixup DT for the two DDR banks */
+	base[0] = gd->bd->bi_dram[0].start;
+	size[0] = gd->bd->bi_dram[0].size;
+	base[1] = gd->bd->bi_dram[1].start;
+	size[1] = gd->bd->bi_dram[1].size;
+
+	fdt_fixup_memory_banks(blob, base, size, 2);
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

board/freescale/ls1012aqds/ls1012aqds_qixis.h new file +35 -0

new file mode 100644
index 0000000..584f604
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

configs/ls1012aqds_qspi_defconfig new file +32 -0

new file mode 100644
index 0000000..2bc178c
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

include/configs/ls1012a_common.h new file +22 -0

new file mode 100644
index 0000000..855fb60
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define	CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE

include/configs/ls1012a_common.h line 28

Quoted 6 lines

include/configs/ls1012a_common.h new file +6 -0

+
+#define CONFIG_SYS_TEXT_BASE		0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		125000000

Hard-coded value? Are the clocks board-specfic?

include/configs/ls1012a_common.h

Quoted 5 lines

include/configs/ls1012a_common.h new file +5 -0

+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_SYS_INIT_SP_ADDR

	(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

include/configs/ls1012a_common.h line 34

Quoted 1 line

include/configs/ls1012a_common.h new file +1 -0

+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE +

0x10000000)

include/configs/ls1012a_common.h

Quoted 4 lines

include/configs/ls1012a_common.h new file +4 -0

+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE

CONFIG_SYS_DDR_SDRAM_BASE

include/configs/ls1012a_common.h line 41

Quoted 3 lines

include/configs/ls1012a_common.h new file +3 -0

+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		25000000	/* 12MHz */

Does this timer has a dedicated clock source? This should be CONFIG_SYS_CLK_FREQ/4, right? Isn't it also board-specific?

include/configs/ls1012a_common.h

Quoted 6 lines

include/configs/ls1012a_common.h new file +6 -0

+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE +

128 * 1024)

Quoted 50 lines

include/configs/ls1012a_common.h new file +50 -0

+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		1000000
+#define CONFIG_ENV_SPI_MODE		0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI

include/configs/ls1012a_common.h

Quoted 10 lines

include/configs/ls1012a_common.h new file +10 -0

+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE

	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \

include/configs/ls1012a_common.h line 108

Quoted 1 line

include/configs/ls1012a_common.h new file +1 -0

+

CONFIG_SYS_SCSI_MAX_LUN)

include/configs/ls1012a_common.h

Quoted 4 lines

include/configs/ls1012a_common.h new file +4 -0

+
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe

code */

Quoted 19 lines

include/configs/ls1012a_common.h new file +19 -0

+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP

include/configs/ls1012a_common.h

Quoted 10 lines

include/configs/ls1012a_common.h new file +10 -0

+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600,

115200 }

Quoted 22 lines

include/configs/ls1012a_common.h new file +22 -0

+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\

include/configs/ls1012a_common.h

Quoted 10 lines

include/configs/ls1012a_common.h new file +10 -0

+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200

root=/dev/ram0 " \

include/configs/ls1012a_common.h line 175

Quoted 2 lines

include/configs/ls1012a_common.h new file +2 -0

+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read

$kernel_load "\

include/configs/ls1012a_common.h

Quoted 6 lines

include/configs/ls1012a_common.h new file +6 -0

+					"$kernel_start $kernel_size && "\
+					"bootm $kernel_load"
+#define CONFIG_BOOTDELAY		10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer

Size */

include/configs/ls1012a_common.h

Quoted 3 lines

include/configs/ls1012a_common.h new file +3 -0

+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot

args buffer */

include/configs/ls1012a_common.h

Quoted 4 lines

include/configs/ls1012a_common.h new file +4 -0

+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command

args */

include/configs/ls1012a_common.h

Quoted 3 lines

include/configs/ls1012a_common.h new file +3 -0

+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip

size */

Quoted 15 lines

include/configs/ls1012a_common.h new file +4 -0

+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */

(quoted diff) +0 -0

b/include/configs/ls1012aqds.h new file mode 100644 index 0000000..584a87c

include/configs/ls1012aqds.h new file +5 -0

@@ -0,0 +1,150 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */

include/configs/ls1012aqds.h line 11

Quoted 6 lines

include/configs/ls1012aqds.h new file +6 -0

+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+

Shouldn't sysclk/ddrclk be put here?

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

Signed-off-by Calvin Johnson <[email protected]>

Signed-off-by Pratiyush Mohan Srivastava <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
Changes for v2: Sending as it is

 arch/arm/Kconfig                        |  10 ++
 arch/arm/dts/Makefile                   |   3 +-
 arch/arm/dts/fsl-ls1012a-rdb.dts        |  16 +++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi       |  39 ++++++
 board/freescale/ls1012ardb/Kconfig      |  15 +++
 board/freescale/ls1012ardb/MAINTAINERS  |   6 +
 board/freescale/ls1012ardb/Makefile     |   7 ++
 board/freescale/ls1012ardb/README       |  89 ++++++++++++++
 board/freescale/ls1012ardb/ls1012ardb.c | 210 ++++++++++++++++++++++++++++++++
 configs/ls1012ardb_qspi_defconfig       |  32 +++++
 include/configs/ls1012ardb.h            |  59 +++++++++
 11 files changed, 485 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
 create mode 100644 board/freescale/ls1012ardb/Kconfig
 create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1012ardb/Makefile
 create mode 100644 board/freescale/ls1012ardb/README
 create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
 create mode 100644 configs/ls1012ardb_qspi_defconfig
 create mode 100644 include/configs/ls1012ardb.h

board/freescale/ls1012ardb/Makefile new file +7 -0

new file mode 100644
index 0000000..05fa9d9
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o

board/freescale/ls1012ardb/README new file +37 -0

new file mode 100644
index 0000000..cda03f6
@@ -0,0 +1,89 @@
+Overview
+--------
+The LS1012ARDB power supplies (PS) provide all the voltages necessary
+for the correct operation of the LS1012A processor, DDR3L, QSPI memory,
+and other onboard peripherals.
+
+LS1012A SoC Overview
+--------------------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)