armv8/ls2080a: configure PMU's PCTBENR to enable WDT

PATCH Superseded Yunhui Cui 4 participants 9 messages Apr 15, 2016 – Jun 7, 2016 Arm (32-bit)

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Yunhui Cui

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2016-04-15 03:47 UTC #0 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

From: Yunhui Cui <[email protected]>

The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.

Signed-off-by Yunhui Cui <[email protected]>

---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)

arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0

index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
 	return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to

arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0

index 10d17b2..62e4f95 100644
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE	0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64

arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0

index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif

board/freescale/ls2080aqds/ls2080aqds.c +2 -0

index b3bd40a..c109349 100644
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }

board/freescale/ls2080ardb/ls2080ardb.c +2 -0

index fb39af6..7872f1f 100644
@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }

Signature · 1 line

2.1.0.27.g96db324

York Sun

2016-05-16 16:14 UTC #1 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Quoted 88 lines · Yunhui Cui

From: Yunhui Cui <[email protected]>

Signed-off-by Yunhui Cui <[email protected]>

---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)

arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0

index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
 	return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff;
+}
+#endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to

arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0

index 10d17b2..62e4f95 100644
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE	0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64

arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0

index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);
 #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 void erratum_a009635(void);
 #endif

board/freescale/ls2080aqds/ls2080aqds.c +2 -0

index b3bd40a..c109349 100644
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }

board/freescale/ls2080ardb/ls2080ardb.c +0 -0

index fb39af6..7872f1f 100644

board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188

Quoted 8 lines

board/freescale/ls2080ardb/ls2080ardb.c +2 -0

@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }

Yunhui,

I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.

York

Yunhui Cui

2016-05-17 03:28 UTC #2 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Hi York,

I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().

Thanks
Yunhui

Quoted 113 lines

-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
 	return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE	0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
Yunhui,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
York

York Sun

2016-05-17 15:44 UTC #3 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Quoted 5 lines · Yunhui Cui

Hi York,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().

Yunhui,

First, please reply inline. This is how we do review in the mailing list.

Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.

York

Quoted 113 lines

Quoted 113 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
 	return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE	0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
Yunhui,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.

Leo Li

2016-05-27 18:34 UTC #4 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Quoted 136 lines · York Sun

Quoted 5 lines · Yunhui Cui
Hi York,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().
Yunhui,
First, please reply inline. This is how we do review in the mailing list.
Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.
York
Quoted 110 lines
Quoted 110 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
    return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET     0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                            4
 #define CONFIG_SYS_CACHELINE_SIZE          64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
    select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
    rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
    /* invert AQR405 IRQ pins polarity */
    out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
Yunhui,
Quoted 3 lines
Quoted 3 lines
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
_______________________________________________
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U-Boot at lists.denx.de
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Signature · 1 line

- Leo

York Sun

2016-05-27 18:36 UTC #5 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Leo,

Did you type anything? I don't see any comment on top, or inline.

York

Quoted 140 lines · Leo Li

Quoted 136 lines · York Sun
Quoted 5 lines · Yunhui Cui
Hi York,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().
Yunhui,
First, please reply inline. This is how we do review in the mailing list.
Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.
York
Quoted 110 lines
Quoted 110 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
    return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET     0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                            4
 #define CONFIG_SYS_CACHELINE_SIZE          64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
    select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
    rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
    /* invert AQR405 IRQ pins polarity */
    out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
Yunhui,
Quoted 3 lines
Quoted 3 lines
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
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U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Leo Li

2016-05-27 18:40 UTC #6 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Sorry, I mistakenly clicked the send button before I really type stuff. Please ignore this mail.

Leo

Quoted 149 lines · York Sun

Leo,
Did you type anything? I don't see any comment on top, or inline.
York
Quoted 140 lines · Leo Li
Quoted 136 lines · York Sun
Quoted 5 lines · Yunhui Cui
Hi York,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().
Yunhui,
First, please reply inline. This is how we do review in the mailing list.
Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.
York
Quoted 110 lines
Quoted 110 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
    return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET     0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                            4
 #define CONFIG_SYS_CACHELINE_SIZE          64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
    select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
    rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
    /* invert AQR405 IRQ pins polarity */
    out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
Yunhui,
Quoted 3 lines
Quoted 3 lines
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 1 line

- Leo

Leo Li

2016-05-27 18:38 UTC #7 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

In reply to York Sun

Quoted 8 lines · York Sun

Quoted 5 lines · Yunhui Cui
Hi York,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
[Yunhui] During the u_boot imamge compiled by using the ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
So maybe cannot move the code to timer_init().

Quoted 7 lines

Yunhui,
First, please reply inline. This is how we do review in the mailing list.
Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.

Hi Yunhui,

Any response? You should better put it into cpu specific files instead of board specific files.

Although watchdog is not a common timer, it might be a good place to add this for now. And you can also consider adding a watchdog driver under drivers/watchdog/.

Regards,
Leo

Quoted 121 lines

York
Quoted 110 lines
Quoted 110 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 90 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
    return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+   u32 pmu_val;
+
+   pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+   *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE   0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET     0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                            4
 #define CONFIG_SYS_CACHELINE_SIZE          64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
    select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
    rtc_enable_32khz_output();
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
    /* invert AQR405 IRQ pins polarity */
    out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+   enable_watchdog_clk();
+
    return 0;
 }
 
Yunhui,
Quoted 3 lines
Quoted 3 lines
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 1 line

- Leo

Yunhui Cui

2016-06-07 09:34 UTC #8 lore raw

PATCH v3 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

In reply to York Sun

Hi York,

Thanks for your suggestions, and I moved the code into timer_init() and sent v4 .

Best Regards,
Yunhui

Quoted 143 lines

-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 11:44 PM
To: Yunhui Cui; Yunhui Cui
Cc: u-boot at lists.denx.de; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 3 lines · Yunhui Cui
Hi York,
I think you can move your code into timer_init() in cpu.c and follow
the example of cltbenr.
Quoted 1 line
[Yunhui] During the u_boot imamge compiled by using the
ls2080ardb_defconfig bootup on ls2080ardb, timer_init() cannot be called ...
Quoted 1 line
So maybe cannot move the code to timer_init().
Yunhui,
First, please reply inline. This is how we do review in the mailing list.
Second, please check your code again. Function timer_init() must be called. You cannot get away from it. Otherwise, you don't have a general timer and all delay functions fail.
York
Quoted 12 lines
Quoted 12 lines
-----Original Message-----
From: York Sun [mailto:york.sun at nxp.com]
Sent: Tuesday, May 17, 2016 12:14 AM
To: Yunhui Cui
Cc: u-boot at lists.denx.de; Yunhui Cui; Prabhakar Kushwaha
Subject: Re: [PATCH v3] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
Quoted 2 lines · Yunhui Cui
From: Yunhui Cui <[email protected]>
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.
Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c           | 15
+++++++++++++++
Quoted 93 lines
Quoted 93 lines
Quoted 80 lines
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  4 ++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h    |  1 +
 board/freescale/ls2080aqds/ls2080aqds.c           |  2 ++
 board/freescale/ls2080ardb/ls2080ardb.c           |  2 ++
 5 files changed, 24 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/soc.c +15 -0
index 0cb0100..c36976d 100644
@@ -42,6 +42,21 @@ bool soc_has_aiop(void)
 	return false;
 }
 
+#if defined(CONFIG_LS2080A)
+/*
+ * In certain Layerscape SoCs, the clock for each core's watchdog
+ * has an enable bit in the PMU Physical Core Time Base Enable
+Register
+ * (PCTBENR), which allows the watchdog to operate.
+ */
+void enable_watchdog_clk(void)
+{
+	u32 pmu_val;
+
+	pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET);
+	*(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val |
+0xff; } #endif
+
 #ifdef CONFIG_LS2080A
 /*
  * This erratum requires setting a value to eddrtqcr1 to diff --git
a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 10d17b2..62e4f95 100644
arch/arm/include/asm/arch-fsl-layerscape/config.h +4 -0
@@ -143,6 +143,10 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+/* PMU-Physical Core Time Base Enable Register */
+#define FSL_PMU_REG_BASE	0x1E30000
+#define FSL_PMU_PCTBENR_OFFSET	0x8A0
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
arch/arm/include/asm/arch-fsl-layerscape/soc.h +1 -0
index 831d817..bd4a8f1 100644
@@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void);  #endif
 
 void cpu_name(char *name);
+void enable_watchdog_clk(void);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635  void erratum_a009635(void);
 #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c
b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40a..c109349 100644
board/freescale/ls2080aqds/ls2080aqds.c +2 -0
@@ -213,6 +213,8 @@ int board_init(void)
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
board/freescale/ls2080ardb/ls2080ardb.c +0 -0
index fb39af6..7872f1f 100644
board/freescale/ls2080ardb/ls2080ardb.c int board_init(void) · line 188
Quoted 8 lines
board/freescale/ls2080ardb/ls2080ardb.c +2 -0
@@ -181,6 +181,8 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 
+	enable_watchdog_clk();
+
 	return 0;
 }
 
Yunhui,
I think you can move your code into timer_init() in cpu.c and follow the example of cltbenr.