arm64: minor fixes of cache operation routine
cover arm64: minor fixes of cache operation routine
Masahiro Yamada (3):
arm64: optimize __asm_{flush,invalidate}_dcache_all
arm64: fix comment "flush & invalidate"
arm64: rename __asm_flush_dcache_level to __asm_dcache_level
arch/arm/cpu/armv8/cache.S | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-)
Signature · 1 line
1.9.1
PATCH 1/3 arm64: optimize __asm_{flush, invalidate}_dcache_all
__asm_dcache_all can directly return to the caller of __asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
---
arch/arm/cpu/armv8/cache.S | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)
arch/arm/cpu/armv8/cache.S +2 -8
@@ -104,19 +104,13 @@ finished: ENDPROC(__asm_dcache_all) ENTRY(__asm_flush_dcache_all) - mov x16, lr mov x0, #0 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) ENTRY(__asm_invalidate_dcache_all) - mov x16, lr mov x0, #0x1 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) /*
Signature · 1 line
1.9.1
PATCH 1/3 arm64: optimize __asm_{flush, invalidate}_dcache_all
Quoted 28 lines · Masahiro Yamada
__asm_dcache_allcan directly return to the caller of __asm_{flush,invalidate}_dcache_all.We do not have to waste x16 register here.
Signed-off-by Masahiro Yamada <[email protected]>---
arch/arm/cpu/armv8/cache.S | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-)arch/arm/cpu/armv8/cache.S +1
-4@@ -104,19 +104,13 @@ finished: ENDPROC(__asm_dcache_all) ENTRY(__asm_flush_dcache_all) - mov x16, lr mov x0, #0 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_flush_dcache_all)
arch/arm/cpu/armv8/cache.S finished: · line 116
Quoted 10 lines
arch/arm/cpu/armv8/cache.S +1
-4ENTRY(__asm_invalidate_dcache_all) - mov x16, lr mov x0, #0x1 - bl __asm_dcache_all - mov lr, x16 - ret + b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) /*
It is a smart solution.
PATCH 1/3 arm64: optimize __asm_{flush, invalidate}_dcache_all
In reply to Masahiro YamadaQuoted 7 lines · Masahiro Yamada
__asm_dcache_allcan directly return to the caller of __asm_{flush,invalidate}_dcache_all.We do not have to waste x16 register here.
Signed-off-by Masahiro Yamada <[email protected]>Reviewed-by York Sun <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160530/93d258b0/attachment.sig>
PATCH 2/3 arm64: fix comment "flush & invalidate"
In reply to Masahiro YamadaWe should say "clean & invalidate", or simply "flush".
---
arch/arm/cpu/armv8/cache.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/armv8/cache.S +2 -2
@@ -19,7 +19,7 @@ * clean and invalidate one level cache. * * x0: cache level - * x1: 0 flush & invalidate, 1 invalidate only + * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ ENTRY(__asm_flush_dcache_level)
@@ -62,7 +62,7 @@ ENDPROC(__asm_flush_dcache_level) /* * void __asm_flush_dcache_all(int invalidate_only) * - * x0: 0 flush & invalidate, 1 invalidate only + * x0: 0 clean & invalidate, 1 invalidate only * * clean and invalidate all data cache by SET/WAY. */
Signature · 1 line
1.9.1
PATCH 2/3 arm64: fix comment "flush & invalidate"
Quoted 3 lines · Masahiro Yamada
We should say "clean & invalidate", or simply "flush".
Signed-off-by Masahiro Yamada <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160530/7c66f187/attachment.sig>
PATCH 3/3 arm64: rename __asm_flush_dcache_level to __asm_dcache_level
In reply to Masahiro YamadaSince 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name.
---
arch/arm/cpu/armv8/cache.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
arch/arm/cpu/armv8/cache.S +6 -6
@@ -14,15 +14,15 @@ #include <linux/linkage.h> /* - * void __asm_flush_dcache_level(level) + * void __asm_dcache_level(level) * - * clean and invalidate one level cache. + * flush or invalidate one level cache. * * x0: cache level * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ -ENTRY(__asm_flush_dcache_level) +ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@ loop_way: b.ge loop_set ret -ENDPROC(__asm_flush_dcache_level) +ENDPROC(__asm_dcache_level) /* * void __asm_flush_dcache_all(int invalidate_only) * * x0: 0 clean & invalidate, 1 invalidate only * - * clean and invalidate all data cache by SET/WAY. + * flush or invalidate all data cache by SET/WAY. */ ENTRY(__asm_dcache_all) mov x1, x0
@@ -87,7 +87,7 @@ loop_level: and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 b.lt skip /* skip if no cache or icache */ - bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ + bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ skip: add x0, x0, #1 /* increment cache level */ cmp x11, x0
Signature · 1 line
1.9.1
PATCH 3/3 arm64: rename __asm_flush_dcache_level to __asm_dcache_level
Quoted 6 lines · Masahiro Yamada
Since
1e6ad55c0582("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name.Signed-off-by Masahiro Yamada <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160530/4472a1de/attachment.sig>