spi: fsl_qspi: Fix issues on arm64

index cb8d929..96fb909 100644
@@ -92,9 +92,9 @@ DECLARE_GLOBAL_DATA_PTR;
 struct fsl_qspi_platdata {
 	u32 flags;
 	u32 speed_hz;
-	u32 reg_base;
-	u32 amba_base;
-	u32 amba_total_size;
+	fdt_addr_t reg_base;
+	fdt_addr_t amba_base;
+	fdt_size_t amba_total_size;
 	u32 flash_num;
 	u32 num_chipselect;
 };

@@ -940,8 +940,13 @@ static int fsl_qspi_probe(struct udevice *bus)
 	priv->flags = plat->flags;
 
 	priv->speed_hz = plat->speed_hz;
-	priv->amba_base[0] = plat->amba_base;
-	priv->amba_total_size = plat->amba_total_size;
+	/*
+	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+	 * AMBA memory zone should be located on the 0~4GB space
+	 * even on a 64bits cpu.
+	 */
+	priv->amba_base[0] = (u32)plat->amba_base;
+	priv->amba_total_size = (u32)plat->amba_total_size;
 	priv->flash_num = plat->flash_num;
 	priv->num_chipselect = plat->num_chipselect;
 

@@ -984,10 +989,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-	struct reg_data {
-		u32 addr;
-		u32 size;
-	} regs_data[2];
+	struct fdt_resource res_regs, res_mem;
 	struct fsl_qspi_platdata *plat = bus->platdata;
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;

@@ -996,10 +998,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	if (fdtdec_get_bool(blob, node, "big-endian"))
 		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 
-	ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
-				   sizeof(regs_data)/sizeof(u32));
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI", &res_regs);
+	if (ret) {
+		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+		return -ENOMEM;
+	}
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI-memory", &res_mem);
 	if (ret) {
-		debug("Error: can't get base addresses (ret = %d)!\n", ret);
+		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 

@@ -1017,16 +1025,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
 					      FSL_QSPI_MAX_CHIPSELECT_NUM);
 
-	plat->reg_base = regs_data[0].addr;
-	plat->amba_base = regs_data[1].addr;
-	plat->amba_total_size = regs_data[1].size;
+	plat->reg_base = res_regs.start;
+	plat->amba_base = res_mem.start;
+	plat->amba_total_size = res_mem.end - res_mem.start + 1;
 	plat->flash_num = flash_num;
 
-	debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
 	      __func__,
-	      plat->reg_base,
-	      plat->amba_base,
-	      plat->amba_total_size,
+	      (u64)plat->reg_base,
+	      (u64)plat->amba_base,
+	      (u64)plat->amba_total_size,
 	      plat->speed_hz,
 	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
 	      );

index 96fb909..db7ebee 100644
@@ -927,10 +927,11 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev)
 
 static int fsl_qspi_probe(struct udevice *bus)
 {
-	u32 total_size;
+	u32 amba_size_per_chip;
 	struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 	struct fsl_qspi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_bus *dm_spi_bus;
+	int i;
 
 	dm_spi_bus = bus->uclass_priv;
 

@@ -956,7 +957,22 @@ static int fsl_qspi_probe(struct udevice *bus)
 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 		QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 
-	total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+	/*
+	 * Assign AMBA memory zone for every chipselect
+	 * QuadSPI has two channels, every channel has two chipselects.
+	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+	 * into two parts and assign to every channel. This indicate that every
+	 * channel only has one valid chipselect.
+	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+	 * into four parts and assign to every chipselect.
+	 * Every channel will has two valid chipselects.
+	 */
+	amba_size_per_chip = priv->amba_total_size >>
+			     (priv->num_chipselect >> 1);
+	for (i = 1 ; i < priv->num_chipselect ; i++)
+		priv->amba_base[i] =
+			amba_size_per_chip + priv->amba_base[i - 1];
+
 	/*
 	 * Any read access to non-implemented addresses will provide
 	 * undefined results.

@@ -967,14 +983,30 @@ static int fsl_qspi_probe(struct udevice *bus)
 	 * setting the size of these devices to 0.  This would ensure
 	 * that the complete memory map is assigned to only one flash device.
 	 */
-	qspi_write32(priv->flags, &priv->regs->sfa1ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfa2ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb1ad,
-		     total_size | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb2ad,
-		     total_size | priv->amba_base[0]);
+	qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+	switch (priv->num_chipselect) {
+	case 2:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[1]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		break;
+	case 4:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[2]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[3]);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[3] + amba_size_per_chip);
+		break;
+	default:
+		debug("Error: Unsupported chipselect number %u!\n",
+		      priv->num_chipselect);
+		qspi_module_disable(priv, 1);
+		return -EINVAL;
+	}
 
 	qspi_set_lut(priv);
 

@@ -1063,8 +1095,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
 	bus = dev->parent;
 	priv = dev_get_priv(bus);
 
-	priv->cur_amba_base =
-		priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+	priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
 	qspi_module_disable(priv, 0);
 

index 007a5a0..da2bb7b 100644
@@ -127,6 +127,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf);
 #endif
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR	0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR	0x71 /* Write any device register */
+#endif
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *

129 lines not on this page · raw message

index 2ae2e3c..01457de 100644
@@ -970,6 +970,43 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+	u8 cmd[4];
+	u32 offset = 0x800004; /* CR3V register offset */
+	u8 cr3v;
+	int ret;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	cmd[1] = offset >> 16;
+	cmd[2] = offset >> 8;
+	cmd[3] = offset >> 0;
+
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	/* CR3V bit3: 4-KB Erase */
+	if (cr3v & 0x8)
+		return 0;
+
+	cmd[0] = CMD_SPANSION_WRAR;
+	cr3v |= 0x8;
+	ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	if (!(cr3v & 0x8))
+		return -EFAULT;
+
+	return 0;
+}
+#endif
+
 int spi_flash_scan(struct spi_flash *flash)
 {
 	struct spi_slave *spi = flash->spi;

@@ -1020,6 +1057,41 @@ int spi_flash_scan(struct spi_flash *flash)
 		return -EPROTONOSUPPORT;
 	}
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+	/*
+	 * The S25FS-S family physical sectors may be configured as a
+	 * hybrid combination of eight 4-kB parameter sectors
+	 * at the top or bottom of the address space with all
+	 * but one of the remaining sectors being uniform size.
+	 * The Parameter Sector Erase commands (20h or 21h) must
+	 * be used to erase the 4-kB parameter sectors individually.
+	 * The Sector (uniform sector) Erase commands (D8h or DCh)
+	 * must be used to erase any of the remaining
+	 * sectors, including the portion of highest or lowest address
+	 * sector that is not overlaid by the parameter sectors.
+	 * The uniform sector erase command has no effect on parameter sectors.
+	 */
+	if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+		int ret;
+		u8 id[6];
+
+		/* Read the ID codes again, 6 bytes */
+		ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+		if (ret)
+			return -EIO;
+
+		ret = memcmp(id, idcode, 5);
+		if (ret)
+			return -EIO;
+
+		/* 0x81: S25FS-S family 0x80: S25FL-S family */
+		if (id[5] == 0x81) {
+			ret = spansion_s25fss_disable_4KB_erase(spi);
+			if (ret)
+				return ret;
+		}
+	}
+#endif
 	/* Flash powers up read-only, so clear BP# bits */
 	if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
 	    idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||