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ARM: OMAP4+: Fix DPLL programming sequence

PATCH In review Lokesh Vutla 3 participants 3 messages May 23, 2016 – May 30, 2016 Arm (32-bit)

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Lokesh Vutla

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#0 lore raw

PATCH 1/1 ARM: OMAP4+: Fix DPLL programming sequence

All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence.

Reported-by Richard Woodruff <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/omap-common/clocks-common.c +5 -3
index ef2ac98..2de9935 100644
@@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 			/* Dpll locked with ideal values for nominal opps. */
 			debug("\n %s Dpll already locked with ideal"
 						"nominal opp values", dpll);
+
+			bypass_dpll(base);
 			goto setup_post_dividers;
 		}
 	}

@@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 
 	writel(temp, &dpll_regs->cm_clksel_dpll);
 
+setup_post_dividers:
+	setup_post_dividers(base, params);
+
 	/* Lock */
 	if (lock)
 		do_lock_dpll(base);
 
-setup_post_dividers:
-	setup_post_dividers(base, params);
-
 	/* Wait till the DPLL locks */
 	if (lock)
 		wait_for_lock(base);
Signature · 1 line
2.8.2
#1 lore raw

PATCH 1/1 ARM: OMAP4+: Fix DPLL programming sequence

Quoted 31 lines · Lokesh Vutla

All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence.

Reported-by Richard Woodruff <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/omap-common/clocks-common.c +5 -0
index ef2ac98..2de9935 100644
@@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 			/* Dpll locked with ideal values for nominal opps. */
 			debug("\n %s Dpll already locked with ideal"
 						"nominal opp values", dpll);
+
+			bypass_dpll(base);
 			goto setup_post_dividers;
 		}
 	}

@@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 
 	writel(temp, &dpll_regs->cm_clksel_dpll);
 
+setup_post_dividers:
+	setup_post_dividers(base, params);
+

arch/arm/cpu/armv7/omap-common/clocks-common.c static void do_setup_dpll(u32 const base, const struct dpll_params *params, · line 265

Quoted 10 lines
arch/arm/cpu/armv7/omap-common/clocks-common.c +0 -3
 	/* Lock */
 	if (lock)
 		do_lock_dpll(base);
 
-setup_post_dividers:
-	setup_post_dividers(base, params);
-
 	/* Wait till the DPLL locks */
 	if (lock)
 		wait_for_lock(base);

LGTM

Reviewed-by Nishanth Menon <[email protected]>
Signature · 2 lines
Regards,
Nishanth Menon
#2 lore raw
In reply to Lokesh Vutla
Quoted 7 lines · Lokesh Vutla

All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence.

Reported-by Richard Woodruff <[email protected]>
Signed-off-by Lokesh Vutla <[email protected]>
Reviewed-by Nishanth Menon <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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