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Multiple FSL Security Engine RNG instantation

PATCH New Alex Porosanu 2 participants 6 messages Apr 29, 2016 – May 24, 2016

Subsystems (4)
Arm (32-bit) PowerPC Arm i.MX and Layerscape Crypto API
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Alex Porosanu

author
#0 lore raw

cover Multiple FSL Security Engine RNG instantation

This series of patches add the neccesary support for allowing multi-SEC SoCs, like the C292 & C293 to instantiate the respecting RNGs.

Alex Porosanu (3):
arch/arm: add SEC JR0 offset
arch/arm, arch/powerpc: add # of SEC engines on the SOC crypto/fsl: add support for multiple SEC engines initialization

 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   2 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   9 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   8 +-
 arch/arm/include/asm/arch-ls102xa/config.h         |   2 +
 arch/arm/include/asm/arch-mx6/imx-regs.h           |   9 +-
 arch/arm/include/asm/arch-mx7/imx-regs.h           |  11 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c                |   9 +
 arch/powerpc/include/asm/config_mpc85xx.h          |   6 +
 board/freescale/c29xpcie/c29xpcie.c                |   2 +-
 drivers/crypto/fsl/jr.c                            | 271 ++++++++++++---------
 drivers/crypto/fsl/jr.h                            |   3 +
 include/fsl_sec.h                                  |   6 +-
 12 files changed, 210 insertions(+), 128 deletions(-)
Signature · 1 line
1.9.3
author
#1 lore raw

PATCH 1/3 arch/arm: add SEC JR0 offset

From: Alex Porosanu <[email protected]>

Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by Alex Porosanu <[email protected]>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h |  9 +++++++--
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  8 ++++++--
 arch/arm/include/asm/arch-ls102xa/config.h             |  1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h               |  9 +++++++--
 arch/arm/include/asm/arch-mx7/imx-regs.h               | 11 +++++++----
 5 files changed, 28 insertions(+), 10 deletions(-)
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +7 -2
index 0bad0c7..57b99d4 100644
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 

@@ -157,6 +155,13 @@ struct sys_info {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +6 -2
index 1d3b336..65b3357 100644
@@ -77,8 +77,12 @@
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR		(CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR		(CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
index 267bd17..92f30e2 100644
@@ -40,6 +40,7 @@
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
 #define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
arch/arm/include/asm/arch-mx6/imx-regs.h +7 -2
index 3ab04bf..ac37e4f 100644
@@ -227,8 +227,13 @@
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET   0
+#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
arch/arm/include/asm/arch-mx7/imx-regs.h +7 -4
index a3106e7..74917f0 100644
@@ -218,10 +218,13 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>
Signature · 1 line
1.9.3
author
#2 lore raw

PATCH 2/3 arch/arm, arch/powerpc: add # of SEC engines on the SOC

In reply to Alex Porosanu

From: Alex Porosanu <[email protected]>

Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC.

Signed-off-by Alex Porosanu <[email protected]>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
 arch/arm/include/asm/arch-ls102xa/config.h        | 1 +
 arch/powerpc/include/asm/config_mpc85xx.h         | 6 ++++++
 board/freescale/c29xpcie/c29xpcie.c               | 2 +-
 4 files changed, 10 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-fsl-layerscape/config.h +2 -0
index 10d17b2..5771b28 100644
@@ -143,6 +143,7 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64

@@ -195,6 +196,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
index 92f30e2..139a623 100644
@@ -132,6 +132,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
arch/powerpc/include/asm/config_mpc85xx.h +6 -0
index eccc146..505d355 100644
@@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #elif defined(CONFIG_QEMU_E500)
 #define CONFIG_MAX_CPUS			1

@@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
board/freescale/c29xpcie/c29xpcie.c +1 -1
index e325b4d..45f463f 100644
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
 
 	while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
 			CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
-			+ offset * 0x20000)) >= 0) {
+			+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
 		fdt_del_node(blob, nodeoff);
 		offset++;
 	}
Signature · 1 line
1.9.3
author
#3 lore raw

PATCH 3/3 crypto/fsl: add support for multiple SEC engines initialization

In reply to Alex Porosanu

From: Alex Porosanu <[email protected]>

For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator).

Signed-off-by Alex Porosanu <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c |   9 ++
 drivers/crypto/fsl/jr.c             | 271 +++++++++++++++++++++---------------
 drivers/crypto/fsl/jr.h             |   3 +
 include/fsl_sec.h                   |   6 +-
 4 files changed, 172 insertions(+), 117 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu_init.c +9 -0
index f168375..61f5639 100644
@@ -958,6 +958,15 @@ int cpu_init_r(void)
 
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
+
+#if defined(CONFIG_PPC_C29X)
+	if ((SVR_SOC_VER(svr) == SVR_C292) ||
+	    (SVR_SOC_VER(svr) == SVR_C293))
+		sec_init_idx(1);
+
+	if (SVR_SOC_VER(svr) == SVR_C293)
+		sec_init_idx(2);
+#endif
 #endif
 
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
drivers/crypto/fsl/jr.c +156 -115

520 lines not on this page · raw message

drivers/crypto/fsl/jr.h +3 -0
index 1642dbb..d897e57 100644
@@ -90,6 +90,9 @@ struct jobring {
 	/* This ring can be on the stack */
 	struct jr_info info[JR_SIZE];
 	struct op_ring *output_ring;
+	/* Offset in CCSR to the SEC engine to which this JR belongs */
+	uint32_t sec_offset;
+
 };
 
 struct result {
include/fsl_sec.h +4 -2
index a52110a..bffabc8 100644
@@ -294,8 +294,6 @@ struct sg_entry {
 
 #endif
 
-int sec_init(void);
-
 /* blob_dek:
  * Encapsulates the src in a secure blob and stores it dst
  * @src: reference to the plaintext

@@ -305,6 +303,10 @@ int sec_init(void);
  */
 int blob_dek(const u8 *src, u8 *dst, u8 len);
 
+#if defined(CONFIG_PPC_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
 #endif
 
 #endif /* __FSL_SEC_H */
Signature · 1 line
1.9.3
author
#4 lore raw

cover Multiple FSL Security Engine RNG instantation

In reply to Alex Porosanu

Ping!

Quoted 38 lines

-----Original Message-----
From: U-Boot [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Alex Porosanu
Sent: Friday, April 29, 2016 3:18 PM
To: u-boot at lists.denx.de
Cc: Adrian Alonso Lazcano <[email protected]>; Mircea Pop <[email protected]>; Ruchika Gupta <[email protected]>
Subject: [U-Boot] [PATCH 0/3] Multiple FSL Security Engine RNG instantation

This series of patches add the neccesary support for allowing multi-SEC SoCs, like the C292 & C293 to instantiate the respecting RNGs.

Alex Porosanu (3):
arch/arm: add SEC JR0 offset
arch/arm, arch/powerpc: add # of SEC engines on the SOC crypto/fsl: add support for multiple SEC engines initialization

 arch/arm/include/asm/arch-fsl-layerscape/config.h  |   2 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   9 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |   8 +-
 arch/arm/include/asm/arch-ls102xa/config.h         |   2 +
 arch/arm/include/asm/arch-mx6/imx-regs.h           |   9 +-
 arch/arm/include/asm/arch-mx7/imx-regs.h           |  11 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c                |   9 +
 arch/powerpc/include/asm/config_mpc85xx.h          |   6 +
 board/freescale/c29xpcie/c29xpcie.c                |   2 +-
 drivers/crypto/fsl/jr.c                            | 271 ++++++++++++---------
 drivers/crypto/fsl/jr.h                            |   3 +
 include/fsl_sec.h                                  |   6 +-
 12 files changed, 210 insertions(+), 128 deletions(-)

--
1.9.3

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#5 lore raw

cover Multiple FSL Security Engine RNG instantation

In reply to Alex Porosanu
Quoted 8 lines · Alex Porosanu

This series of patches add the neccesary support for allowing multi-SEC SoCs, like the C292 & C293 to instantiate the respecting RNGs.

Alex Porosanu (3):
arch/arm: add SEC JR0 offset
arch/arm, arch/powerpc: add # of SEC engines on the SOC crypto/fsl: add support for multiple SEC engines initialization

Applied to u-boot-fsl-qoriq master, awaiting upstream.

Thanks.

York