armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
PATCH 1/1 armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
From: Shaohui Xie <[email protected]>
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active.
Signed-off-by Shaohui Xie <[email protected]>
--- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ include/configs/ls1043ardb.h | 1 + 2 files changed, 5 insertions(+)
board/freescale/ls1043ardb/ls1043ardb.c +4 -0
@@ -84,6 +84,8 @@ int board_early_init_f(void)int board_init (void ) {struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR ; +struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR ; +/* * Set CCI-400 control override register to enable barrier
@@ -106,6 +108,8 @@ int board_init(void)#ifdef CONFIG_U_QE u_qe_init ();#endif +/* invert AQR105 IRQ pins polarity */ +out_be32 (&scfg->intpcr,AQR105_IRQ_MASK );return 0 ; }
include/configs/ls1043ardb.h +1 -0
@@ -254,6 +254,7 @@#define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHY_AQUANTIA +#define AQR105_IRQ_MASK 0x40000000#define RGMII_PHY1_ADDR 0x1#define RGMII_PHY2_ADDR 0x2
Signature · 1 line
2.1.0.27.g96db324
PATCH 1/1 armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY
Quoted 11 lines · shh.xie at gmail.com
From: Shaohui Xie <[email protected]>
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in
SCFG_INTPCRregister, because AQR105 interrupt is low active but GIC accepts high active.Signed-off-by Shaohui Xie <[email protected]>--- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++ include/configs/ls1043ardb.h | 1 + 2 files changed, 5 insertions(+)
Applied to u-boot-fsl-qoriq master, awaiting upstream.
Thanks.
York