spi: spi_flash: Dont set quad enable for micron in all cases

-----Original Message-----
From: Siva Durga Prasad Paladugu
Sent: Tuesday, June 14, 2016 2:48 PM
To: jagannadh.teki at gmail.com; 'Siva Durga Prasad Paladugu' <[email protected]>; u-boot at lists.denx.de
Cc: Michal Simek <[email protected]>
Subject: RE: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases

-----Original Message-----
From: Siva Durga Prasad Paladugu [mailto:siva.durga.paladugu at xilinx.com]
Sent: Thursday, May 26, 2016 12:28 PM
To: u-boot at lists.denx.de
Cc: Michal Simek <[email protected]>; jagannadh.teki at gmail.com; Siva Durga Prasad Paladugu <[email protected]>
Subject: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases

Dont set quad enable for micron devices in all cases Setting the quad enable bit in micron expects all other commands like register reads on quad lines which may not be supported by some controllers. Hence, dont set the quad enable if controller driver sets the no_all_quad.

Hi Jagan,

Any comments on this series. If not, Please take this series.

Regards,
Siva

Signed-off-by Siva Durga Prasad Paladugu <[email protected]>

---
Changes for v2:
- Newly added in series.

---
 drivers/mtd/spi/spi_flash.c |   13 ++++++++++++-
 include/spi.h               |    2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

drivers/mtd/spi/spi_flash.c index renamed from drivers/mtd/spi/spi_flash.c +0 -0

5451725..5b22ae2 100644

drivers/mtd/spi/spi_flash.c +2 -0

@@ -926,6 +926,8 @@ static int micron_quad_enable(struct spi_flash *flash)
 
 static int set_quad_mode(struct spi_flash *flash, u8 idcode0)  {
+	struct spi_slave *spi = flash->spi;
+
 	switch (idcode0) {
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 	case SPI_FLASH_CFI_MFR_MACRONIX:

@@ -938,7 +940,16 @@ static int set_quad_mode(struct spi_flash *flash, u8

idcode0) #endif #ifdef CONFIG_SPI_FLASH_STMICRO

drivers/mtd/spi/spi_flash.c +10 -1

 	case SPI_FLASH_CFI_MFR_STMICRO:
-		return micron_quad_enable(flash);
+		/*
+		 * Set quad enable for micron only
+		 * if controller supports sending of
+		 * all commands on quad lines, otherwise
+		 * dont enable it
+		 */
+		if (spi->no_all_quad)
+			return 0;
+		else
+			return micron_quad_enable(flash);
 #endif
 	default:
 		printf("SF: Need set QEB func for %02x flash\n", idcode0); diff --

git a/include/spi.h b/include/spi.h index 4b88d39..17c6e4d 100644

include/spi.h +1 -2

@@ -117,7 +117,7 @@ struct spi_slave {
 	unsigned int max_write_size;
 	void *memory_map;
 	u8 option;
-
+	u8 no_all_quad;
 	u8 flags;
 #define SPI_XFER_BEGIN		BIT(0)	/* Assert CS before transfer */
 #define SPI_XFER_END		BIT(1)	/* Deassert CS after transfer */
--

1.7.1

Hi Tom,

Quoted 23 lines

-----Original Message-----
From: Siva Durga Prasad Paladugu
Sent: Tuesday, June 14, 2016 2:48 PM
To: jagannadh.teki at gmail.com; 'Siva Durga Prasad Paladugu' <[email protected]>; u-boot at lists.denx.de
Cc: Michal Simek <[email protected]>
Subject: RE: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases

-----Original Message-----
From: Siva Durga Prasad Paladugu [mailto:siva.durga.paladugu at xilinx.com]
Sent: Thursday, May 26, 2016 12:28 PM
To: u-boot at lists.denx.de
Cc: Michal Simek <[email protected]>; jagannadh.teki at gmail.com; Siva Durga Prasad Paladugu <[email protected]>
Subject: [PATCH v2 1/3] spi: spi_flash: Dont set quad enable for micron in all cases

Dont set quad enable for micron devices in all cases Setting the quad enable bit in micron expects all other commands like register reads on quad lines which may not be supported by some controllers. Hence, dont set the quad enable if controller driver sets the no_all_quad.

Quoted 6 lines

Hi Jagan,

Any comments on this series. If not, Please take this series.

Regards,
Siva

If Jagan is busy, Is it possible to get it acked/reviewed from some other person and can go through your tree/Michal tree.

Dont set quad enable for micron devices in all cases Setting the quad enable bit in micron expects all other commands like register reads on quad lines which may not be supported by some controllers. Hence, dont set the quad enable if controller driver sets the no_all_quad.

Signed-off-by Siva Durga Prasad Paladugu <[email protected]>

---
Changes for v2:
- Newly added in series.

---
 drivers/mtd/spi/spi_flash.c |   13 ++++++++++++-
 include/spi.h               |    2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

drivers/mtd/spi/spi_flash.c +12 -1

index 5451725..5b22ae2 100644
@@ -926,6 +926,8 @@ static int micron_quad_enable(struct spi_flash *flash)
 
 static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
 {
+	struct spi_slave *spi = flash->spi;
+
 	switch (idcode0) {
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 	case SPI_FLASH_CFI_MFR_MACRONIX:

@@ -938,7 +940,16 @@ static int set_quad_mode(struct spi_flash *flash, u8 idcode0)
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	case SPI_FLASH_CFI_MFR_STMICRO:
-		return micron_quad_enable(flash);
+		/*
+		 * Set quad enable for micron only
+		 * if controller supports sending of
+		 * all commands on quad lines, otherwise
+		 * dont enable it
+		 */
+		if (spi->no_all_quad)
+			return 0;
+		else
+			return micron_quad_enable(flash);
 #endif
 	default:
 		printf("SF: Need set QEB func for %02x flash\n", idcode0);

include/spi.h +0 -0

index 4b88d39..17c6e4d 100644

This adds QSPI driver support for ZynqMP platform
This driver supports all spi flash commands in
qspi single mode.

Signed-off-by Siva Durga Prasad Paladugu <[email protected]>

---
Changes for v2:
- set no_all_quad as zynqmp qspi
controller doesnt support it

---
 drivers/spi/Kconfig       |    9 +
 drivers/spi/Makefile      |    1 +
 drivers/spi/zynqmp_qspi.c |  705 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 715 insertions(+), 0 deletions(-)
 create mode 100644 drivers/spi/zynqmp_qspi.c

drivers/spi/Kconfig +9 -0

index f0258f8..25a98a6 100644
@@ -155,6 +155,15 @@ config ZYNQ_QSPI
 	  Zynq QSPI IP core. This IP is used to connect the flash in
 	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
 
+config ZYNQMP_QSPI
+	bool "ZynqMP QSPI driver"
+	depends on ARCH_ZYNQMP
+	help
+	  Enable the ZynqMP Quad-SPI (QSPI) driver. This driver can be
+	  used to access the SPI NOR flash on platforms embedding this
+	  ZynqMP QSPI IP core. This IP is used to connect the flash in
+	  4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 config OMAP3_SPI
 	bool "McSPI driver for OMAP"
 	help

drivers/spi/Makefile +1 -0

index 3eca745..b47103f 100644
@@ -51,3 +51,4 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o
 obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
 obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
 obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
+obj-$(CONFIG_ZYNQMP_QSPI) += zynqmp_qspi.o

drivers/spi/zynqmp_qspi.c new file +695 -0

new file mode 100644
index 0000000..93ace51
@@ -0,0 +1,705 @@
+/*
+ * Xilinx ZynqMP Quad-SPI(QSPI) Controller Driver
+ *
+ * (C) Copyright 2016 Xilinx, Inc
+ * Siva Durga Prasad <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <memalign.h>
+#include <ubi_uboot.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <asm/io.h>
+#include "../mtd/spi/sf_internal.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Config Register bit Masks
+ */
+#define ZYNQMP_QSPI_CONFIG_STRT_MODE_MASK	BIT(29)
+#define ZYNQMP_QSPI_CONFIG_MODE_EN_MASK		GENMASK(31, 30)
+#define ZYNQMP_QSPI_CONFIG_DMA_MODE		BIT(31)
+#define ZYNQMP_QSPI_CONFIG_CPHA_MASK		BIT(2)
+#define ZYNQMP_QSPI_CONFIG_CPOL_MASK		BIT(1)
+#define ZYNQMP_QSPI_CONFIG_GFIFO_WP_HOLD	BIT(19)
+#define ZYNQMP_QSPI_CONFIG_BAUD_DIV_MASK	GENMASK(5, 3)
+#define ZYNQMP_QSPI_CONFIG_DFLT_BAUD_RATE_DIV	BIT(3)
+
+/*
+ * QSPI Interrupt Registers bit Masks
+ */
+#define ZYNQMP_QSPI_IXR_TXNFULL_MASK	BIT(2)
+#define ZYNQMP_QSPI_IXR_TXFULL_MASK	BIT(3)
+#define ZYNQMP_QSPI_IXR_RXNEMTY_MASK	BIT(4)
+#define ZYNQMP_QSPI_IXR_GFEMTY_MASK	BIT(7)
+#define ZYNQMP_QSPI_IXR_ALL_MASK	(ZYNQMP_QSPI_IXR_TXNFULL_MASK | \
+					 ZYNQMP_QSPI_IXR_RXNEMTY_MASK)
+#define ZYNQMP_QSPI_GFIFO_ALL_INT_MASK	0xFBE
+
+/*
+ * QSPI Enable Register bit Masks
+ */
+#define ZYNQMP_QSPI_ENABLE_ENABLE_MASK	BIT(0)
+
+/*
+ * QSPI Generic FIFO register bit masks
+ */
+#define ZYNQMP_QSPI_GFIFO_LOW_BUS		BIT(14)
+#define ZYNQMP_QSPI_GFIFO_CS_LOWER		BIT(12)
+#define ZYNQMP_QSPI_GFIFO_UP_BUS		BIT(15)
+#define ZYNQMP_QSPI_GFIFO_CS_UPPER		BIT(13)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_QSPI		GENMASK(11, 10)
+#define ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI		BIT(10)
+#define ZYNQMP_QSPI_GFIFO_TX			BIT(16)
+#define ZYNQMP_QSPI_GFIFO_RX			BIT(17)
+#define ZYNQMP_QSPI_GFIFO_STRIPE_MASK		BIT(18)
+#define ZYNQMP_QSPI_GFIFO_IMD_MASK		GENMASK(7, 0)
+#define ZYNQMP_QSPI_GFIFO_EXP_MASK		BIT(9)
+#define ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK		BIT(8)
+
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_ASSERT	5
+#define ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_DEASSERT	5
+#define ZYNQMP_QSPI_GFIFO_EXP_INIT_VAL		8
+#define ZYNQMP_QSPI_GFIFO_IMD_MAX_DATA_LEN	255
+/*
+ * QSPI DMA Destination status register bit masks
+ */
+#define ZYNQMP_QSPI_DMA_DST_I_STS_DONE		BIT(1)
+#define ZYNQMP_QSPI_DMA_DST_I_STS_MASK		GENMASK(7, 1)
+
+/*
+ * QSPI Generic QSPI selection register bit mask
+ */
+#define ZYNQMP_QSPI_GQSPI_SELECT		BIT(0)
+
+#define ZYNQMP_QSPI_FIFO_THRESHOLD 1
+
+#define SPI_XFER_ON_BOTH	0
+#define SPI_XFER_ON_LOWER	1
+#define SPI_XFER_ON_UPPER	2
+
+#define ZYNQMP_QSPI_DMA_ALIGN	0x4
+#define ZYNQMP_QSPI_DMA_POLL_TIMEOUT	10000000
+
+#define ZYNQMP_QSPI_GENERIC_BASEADDR_OFFSET		0x100
+#define ZYNQMP_QSPI_GENERIC_DMABASE_OFFSET		0x800
+
+/* QSPI register offsets */
+struct zynqmp_qspi_regs {
+	u32 confr;	/* 0x00 */
+	u32 isr;	/* 0x04 */
+	u32 ier;	/* 0x08 */
+	u32 idisr;	/* 0x0C */
+	u32 imaskr;	/* 0x10 */
+	u32 enbr;	/* 0x14 */
+	u32 dr;		/* 0x18 */
+	u32 txd0r;	/* 0x1C */
+	u32 drxr;	/* 0x20 */
+	u32 sicr;	/* 0x24 */
+	u32 txftr;	/* 0x28 */
+	u32 rxftr;	/* 0x2C */
+	u32 gpior;	/* 0x30 */
+	u32 reserved0;	/* 0x34 */
+	u32 lpbkdly;	/* 0x38 */
+	u32 reserved1;	/* 0x3C */
+	u32 genfifo;	/* 0x40 */
+	u32 gqspisel;	/* 0x44 */
+	u32 reserved2;	/* 0x48 */
+	u32 gqfifoctrl;	/* 0x4C */
+	u32 gqfthr;	/* 0x50 */
+	u32 gqpollcfg;	/* 0x54 */
+	u32 gqpollto;	/* 0x58 */
+	u32 gqxfersts;	/* 0x5C */
+	u32 gqfifosnap;	/* 0x60 */
+	u32 gqrxcpy;	/* 0x64 */
+};
+
+struct zynqmp_qspi_dma_regs {
+	u32 dmadst;	/* 0x00 */
+	u32 dmasize;	/* 0x04 */
+	u32 dmasts;	/* 0x08 */
+	u32 dmactrl;	/* 0x0C */
+	u32 reserved0;	/* 0x10 */
+	u32 dmaisr;	/* 0x14 */
+	u32 dmaier;	/* 0x18 */
+	u32 dmaidr;	/* 0x1C */
+	u32 dmaimr;	/* 0x20 */
+	u32 dmactrl2;	/* 0x24 */
+	u32 dmadstmsb;	/* 0x28 */
+};
+
+struct zynqmp_qspi_platdata {
+	struct zynqmp_qspi_regs *regs;
+	struct zynqmp_qspi_dma_regs *dma_regs;
+	u32 frequency;
+	u32 speed_hz;
+};
+
+struct zynqmp_qspi_priv {
+	struct zynqmp_qspi_regs *regs;
+	struct zynqmp_qspi_dma_regs *dma_regs;
+	u8 mode;
+	u32 freq;
+	const void *tx_buf;
+	void *rx_buf;
+	unsigned len;
+	int bytes_to_transfer;
+	int bytes_to_receive;
+	unsigned int is_inst;
+	unsigned int is_dual;
+	unsigned int u_page;
+	unsigned int bus;
+	unsigned int stripe;
+	unsigned cs_change:1;
+};
+
+static u8 last_cmd;
+
+static int zynqmp_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+	struct zynqmp_qspi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = bus->of_offset;
+
+	debug("%s\n", __func__);
+
+	plat->regs = (struct zynqmp_qspi_regs *)(dev_get_addr(bus) +
+					 ZYNQMP_QSPI_GENERIC_BASEADDR_OFFSET);
+	plat->dma_regs = (struct zynqmp_qspi_dma_regs *)(dev_get_addr(bus) +
+					 ZYNQMP_QSPI_GENERIC_DMABASE_OFFSET);
+
+	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+					 166666666);
+	plat->speed_hz = plat->frequency / 2;
+
+	return 0;
+}
+
+static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv *priv)
+{
+	u32 config_reg;
+	struct zynqmp_qspi_regs *regs = priv->regs;
+
+	writel(ZYNQMP_QSPI_GQSPI_SELECT, &regs->gqspisel);
+	writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, &regs->idisr);
+	writel(ZYNQMP_QSPI_FIFO_THRESHOLD, &regs->txftr);
+	writel(ZYNQMP_QSPI_FIFO_THRESHOLD, &regs->rxftr);
+	writel(ZYNQMP_QSPI_GFIFO_ALL_INT_MASK, &regs->isr);
+
+	config_reg = readl(&regs->confr);
+	config_reg &= ~(ZYNQMP_QSPI_CONFIG_STRT_MODE_MASK |
+			ZYNQMP_QSPI_CONFIG_MODE_EN_MASK);
+	config_reg |= ZYNQMP_QSPI_CONFIG_DMA_MODE |
+		      ZYNQMP_QSPI_CONFIG_GFIFO_WP_HOLD |
+		      ZYNQMP_QSPI_CONFIG_DFLT_BAUD_RATE_DIV;
+	writel(config_reg, &regs->confr);
+
+	writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, &regs->enbr);
+}
+
+static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv *priv)
+{
+	u32 gqspi_fifo_reg = 0;
+
+	gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS |
+			 ZYNQMP_QSPI_GFIFO_CS_LOWER;
+
+	return gqspi_fifo_reg;
+}
+
+static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
+				      u32 gqspi_fifo_reg)
+{
+	struct zynqmp_qspi_regs *regs = priv->regs;
+	u32 reg;
+
+	do {
+		reg = readl(&regs->isr);
+	} while (!(reg & ZYNQMP_QSPI_IXR_GFEMTY_MASK));
+
+	writel(gqspi_fifo_reg, &regs->genfifo);
+}
+
+static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
+{
+	u32 gqspi_fifo_reg = 0;
+
+	if (is_on) {
+		gqspi_fifo_reg = zynqmp_qspi_bus_select(priv);
+		gqspi_fifo_reg |= ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI |
+				  ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_ASSERT;
+	} else {
+		gqspi_fifo_reg = ZYNQMP_QSPI_GFIFO_LOW_BUS;
+		gqspi_fifo_reg |= ZYNQMP_QSPI_GFIFO_IMD_DATA_CS_DEASSERT;
+	}
+
+	debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
+
+	zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
+}
+
+static int zynqmp_qspi_set_speed(struct udevice *bus, uint speed)
+{
+	struct zynqmp_qspi_platdata *plat = bus->platdata;
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+	struct zynqmp_qspi_regs *regs = priv->regs;
+	uint32_t confr;
+	u8 baud_rate_val = 0;
+
+	debug("%s\n", __func__);
+	if (speed > plat->frequency)
+		speed = plat->frequency;
+
+	/* Set the clock frequency */
+	confr = readl(&regs->confr);
+	if (speed == 0) {
+		/* Set divisor 8, if the freq is 0 */
+		baud_rate_val = 0x2;
+	} else if (plat->speed_hz != speed) {
+		while ((baud_rate_val < 8) &&
+		       ((plat->frequency /
+		       (2 << baud_rate_val)) > speed))
+			baud_rate_val++;
+
+		plat->speed_hz = speed / (2 << baud_rate_val);
+	}
+	confr &= ~ZYNQMP_QSPI_CONFIG_BAUD_DIV_MASK;
+	confr |= (baud_rate_val << 3);
+	writel(confr, &regs->confr);
+
+	priv->freq = speed;
+
+	debug("regs=%p, mode=%d\n", priv->regs, priv->freq);
+
+	return 0;
+}
+
+static int zynqmp_qspi_child_pre_probe(struct udevice *bus)
+{
+	struct spi_slave *slave = dev_get_parent_priv(bus);
+
+	slave->mode_rx = QUAD_OUTPUT_FAST;
+	slave->mode = SPI_TX_QUAD;
+	slave->no_all_quad = 1;
+
+	return 0;
+}
+
+static int zynqmp_qspi_probe(struct udevice *bus)
+{
+	struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus);
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+
+	debug("zynqmp_qspi_probe:  bus:%p, priv:%p\n", bus, priv);
+
+	priv->regs = plat->regs;
+	priv->dma_regs = plat->dma_regs;
+
+	/* init the zynq spi hw */
+	zynqmp_qspi_init_hw(priv);
+
+	return 0;
+}
+
+static int zynqmp_qspi_set_mode(struct udevice *bus, uint mode)
+{
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+	struct zynqmp_qspi_regs *regs = priv->regs;
+	uint32_t confr;
+
+	debug("%s\n", __func__);
+	/* Set the SPI Clock phase and polarities */
+	confr = readl(&regs->confr);
+	confr &= ~(ZYNQMP_QSPI_CONFIG_CPHA_MASK |
+		   ZYNQMP_QSPI_CONFIG_CPOL_MASK);
+
+	if (priv->mode & SPI_CPHA)
+		confr |= ZYNQMP_QSPI_CONFIG_CPHA_MASK;
+	if (priv->mode & SPI_CPOL)
+		confr |= ZYNQMP_QSPI_CONFIG_CPOL_MASK;
+
+	priv->mode = mode;
+
+	debug("regs=%p, mode=%d\n", priv->regs, priv->mode);
+
+	return 0;
+}
+
+static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
+{
+	u32 data;
+	u32 timeout = ZYNQMP_QSPI_DMA_POLL_TIMEOUT;
+	struct zynqmp_qspi_regs *regs = priv->regs;
+	u32 *buf = (u32 *)priv->tx_buf;
+	u32 len = size;
+
+	debug("TxFIFO: 0x%x, size: 0x%x\n", readl(&regs->isr),
+	      size);
+
+	while (size && timeout) {
+		if (readl(&regs->isr) &
+			ZYNQMP_QSPI_IXR_TXNFULL_MASK) {
+			if (size >= 4) {
+				writel(*buf, &regs->txd0r);
+				buf++;
+				size -= 4;
+			} else {
+				switch (size) {
+				case 1:
+					data = *((u8 *)buf);
+					buf += 1;
+					data |= 0xFFFFFF00;
+					break;
+				case 2:
+					data = *((u16 *)buf);
+					buf += 2;
+					data |= 0xFFFF0000;
+					break;
+				case 3:
+					data = *((u16 *)buf);
+					buf += 2;
+					data |= (*((u8 *)buf) << 16);
+					buf += 1;
+					data |= 0xFF000000;
+					break;
+				}
+				writel(data, &regs->txd0r);
+				size = 0;
+			}
+		} else {
+			udelay(1);
+			timeout--;
+		}
+	}
+	if (!timeout) {
+		debug("zynqmp_qspi_fill_tx_fifo: Timeout\n");
+		return -1;
+	}
+
+	priv->tx_buf += len;
+	return 0;
+}
+
+static void zynqmp_qspi_genfifo_cmd(struct zynqmp_qspi_priv *priv)
+{
+	u8 command = 1;
+	u32 gen_fifo_cmd;
+	u32 bytecount = 0;
+
+	while (priv->len) {
+		gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX;
+
+		if (command) {
+			command = 0;
+			last_cmd = *(u8 *)priv->tx_buf;
+		}
+
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI;
+		gen_fifo_cmd |= *(u8 *)priv->tx_buf;
+		bytecount++;
+		priv->len--;
+		priv->tx_buf = (u8 *)priv->tx_buf + 1;
+
+		debug("GFIFO_CMD_Cmd = 0x%x\n", gen_fifo_cmd);
+
+		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+	}
+}
+
+static u32 zynqmp_qspi_calc_exp(struct zynqmp_qspi_priv *priv,
+				u32 *gen_fifo_cmd)
+{
+	u32 expval = ZYNQMP_QSPI_GFIFO_EXP_INIT_VAL;
+	u32 len;
+
+	while (1) {
+		if (priv->len > ZYNQMP_QSPI_GFIFO_IMD_MAX_DATA_LEN) {
+			if (priv->len & (1 << expval)) {
+				*gen_fifo_cmd &= ~ZYNQMP_QSPI_GFIFO_IMD_MASK;
+				*gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_EXP_MASK;
+				*gen_fifo_cmd |= expval;
+				priv->len -= (1 << expval);
+				return expval;
+			}
+			expval++;
+		} else {
+			*gen_fifo_cmd &= ~(ZYNQMP_QSPI_GFIFO_IMD_MASK |
+					  ZYNQMP_QSPI_GFIFO_EXP_MASK);
+			*gen_fifo_cmd |= (u8)priv->len;
+			len = (u8)priv->len;
+			priv->len  = 0;
+			return len;
+		}
+	}
+}
+
+static int zynqmp_qspi_genfifo_fill_tx(struct zynqmp_qspi_priv *priv)
+{
+	u32 gen_fifo_cmd;
+	u32 len;
+	int ret = 0;
+
+	gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+	gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_TX |
+			ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+	if (priv->stripe)
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+	if (last_cmd == CMD_QUAD_PAGE_PROGRAM)
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_SPI_MODE_QSPI;
+	else
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI;
+
+	while (priv->len) {
+		len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+		debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
+
+		if (gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK)
+			ret = zynqmp_qspi_fill_tx_fifo(priv,
+						       1 << len);
+		else
+			ret = zynqmp_qspi_fill_tx_fifo(priv,
+						       len);
+
+		if (ret)
+			return ret;
+	}
+	return ret;
+}
+
+static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv *priv,
+				 u32 gen_fifo_cmd, u32 *buf)
+{
+	u32 addr;
+	u32 size, len;
+	u32 timeout = ZYNQMP_QSPI_DMA_POLL_TIMEOUT;
+	u32 actuallen = priv->len;
+	struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
+
+	writel((unsigned long)buf, &dma_regs->dmadst);
+	writel(roundup(priv->len, 4), &dma_regs->dmasize);
+	writel(ZYNQMP_QSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
+	addr = (unsigned long)buf;
+	size = roundup(priv->len, ARCH_DMA_MINALIGN);
+	flush_dcache_range(addr, addr+size);
+
+	while (priv->len) {
+		len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+		if (!(gen_fifo_cmd & ZYNQMP_QSPI_GFIFO_EXP_MASK) &&
+		    (len % 4)) {
+			gen_fifo_cmd &= ~(0xFF);
+			gen_fifo_cmd |= (len/4 + 1) * 4;
+		}
+		zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+		debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+	}
+
+	while (timeout) {
+		if (readl(&dma_regs->dmaisr) &
+		    ZYNQMP_QSPI_DMA_DST_I_STS_DONE) {
+			writel(ZYNQMP_QSPI_DMA_DST_I_STS_DONE,
+			       &dma_regs->dmaisr);
+			break;
+		}
+		udelay(1);
+		timeout--;
+	}
+
+	debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
+	      (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
+	      actuallen);
+	if (!timeout) {
+		debug("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
+		return -1;
+	}
+
+	if (buf != priv->rx_buf)
+		memcpy(priv->rx_buf, buf, actuallen);
+
+	return 0;
+}
+
+static int zynqmp_qspi_genfifo_fill_rx(struct zynqmp_qspi_priv *priv)
+{
+	u32 gen_fifo_cmd;
+	u32 *buf;
+	u32 actuallen = priv->len;
+
+	gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
+	gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_RX |
+			ZYNQMP_QSPI_GFIFO_DATA_XFR_MASK;
+
+	if (last_cmd == CMD_READ_QUAD_OUTPUT_FAST ||
+	    last_cmd == CMD_READ_QUAD_IO_FAST)
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_SPI_MODE_QSPI;
+	else
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_SPI_MODE_SPI;
+
+	if (priv->stripe)
+		gen_fifo_cmd |= ZYNQMP_QSPI_GFIFO_STRIPE_MASK;
+
+	/*
+	 * Check if receive buffer is aligned to 4 byte and length
+	 * is multiples of four byte as we are using dma to receive.
+	 */
+	if (!((unsigned long)priv->rx_buf & (ZYNQMP_QSPI_DMA_ALIGN - 1)) &&
+	    !(actuallen % ZYNQMP_QSPI_DMA_ALIGN)) {
+		buf = (u32 *)priv->rx_buf;
+		return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+	}
+
+	ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
+						  ZYNQMP_QSPI_DMA_ALIGN));
+	buf = (u32 *)tmp;
+	return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
+}
+
+static int zynqmp_qspi_start_transfer(struct zynqmp_qspi_priv *priv)
+{
+	int ret = 0;
+
+	if (priv->is_inst) {
+		if (priv->tx_buf)
+			zynqmp_qspi_genfifo_cmd(priv);
+		else
+			ret = -1;
+	} else {
+		if (priv->tx_buf)
+			ret = zynqmp_qspi_genfifo_fill_tx(priv);
+		else if (priv->rx_buf)
+			ret = zynqmp_qspi_genfifo_fill_rx(priv);
+		else
+			ret = -1;
+	}
+	return ret;
+}
+
+static int zynqmp_qspi_transfer(struct zynqmp_qspi_priv *priv)
+{
+	static unsigned cs_change = 1;
+	int status = 0;
+
+	debug("%s\n", __func__);
+
+	while (1) {
+		/* Select the chip if required */
+		if (cs_change)
+			zynqmp_qspi_chipselect(priv, 1);
+
+		cs_change = priv->cs_change;
+
+		if (!priv->tx_buf && !priv->rx_buf && priv->len) {
+			status = -1;
+			break;
+		}
+
+		/* Request the transfer */
+		if (priv->len) {
+			status = zynqmp_qspi_start_transfer(priv);
+			priv->is_inst = 0;
+			if (status < 0)
+				break;
+		}
+
+		if (cs_change)
+			/* Deselect the chip */
+			zynqmp_qspi_chipselect(priv, 0);
+		break;
+	}
+
+	return status;
+}
+
+static int zynqmp_qspi_claim_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+	struct zynqmp_qspi_regs *regs = priv->regs;
+
+	debug("%s\n", __func__);
+	writel(ZYNQMP_QSPI_ENABLE_ENABLE_MASK, &regs->enbr);
+
+	return 0;
+}
+
+static int zynqmp_qspi_release_bus(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+	struct zynqmp_qspi_regs *regs = priv->regs;
+	u32 regval;
+
+	debug("%s\n", __func__);
+	regval = readl(&regs->enbr);
+	regval &= ~ZYNQMP_QSPI_ENABLE_ENABLE_MASK;
+	writel(regval, &regs->enbr);
+
+	return 0;
+}
+
+int zynqmp_qspi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct zynqmp_qspi_priv *priv = dev_get_priv(bus);
+
+	debug("%s: priv: 0x%08lx bitlen: %d dout: 0x%08lx ", __func__,
+	      (unsigned long)priv, bitlen, (unsigned long)dout);
+	debug("din: 0x%08lx flags: 0x%lx\n", (unsigned long)din, flags);
+
+	priv->tx_buf = dout;
+	priv->rx_buf = din;
+	priv->len = bitlen / 8;
+
+	if (dout && flags & SPI_XFER_BEGIN)
+		priv->is_inst = 1;
+	else
+		priv->is_inst = 0;
+
+	if (flags & SPI_XFER_END)
+		priv->cs_change = 1;
+	else
+		priv->cs_change = 0;
+
+	priv->u_page = 0;
+	priv->stripe = 0;
+	priv->bus = 0;
+
+	zynqmp_qspi_transfer(priv);
+
+	return 0;
+}
+
+static const struct dm_spi_ops zynqmp_qspi_ops = {
+	.claim_bus      = zynqmp_qspi_claim_bus,
+	.release_bus    = zynqmp_qspi_release_bus,
+	.xfer           = zynqmp_qspi_xfer,
+	.set_speed      = zynqmp_qspi_set_speed,
+	.set_mode       = zynqmp_qspi_set_mode,
+};
+
+static const struct udevice_id zynqmp_qspi_ids[] = {
+	{ .compatible = "xlnx,zynqmp-qspi-1.0" },
+	{ }
+};
+
+U_BOOT_DRIVER(zynqmp_qspi) = {

Added the qspi driver support for respective ZynqMP boards ZCU102, ZCU102 RevB and DC1 boards.

Signed-off-by Siva Durga Prasad Paladugu <[email protected]>

---
Changes for v2:
- None

---
 configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig |    4 ++++
 configs/xilinx_zynqmp_zcu102_defconfig           |    4 ++++
 configs/xilinx_zynqmp_zcu102_revB_defconfig      |    4 ++++
 3 files changed, 12 insertions(+), 0 deletions(-)

configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +4 -0

index cc08b03..164b156 100644
@@ -3,6 +3,9 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"

@@ -28,6 +31,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_I2C_CADENCE=y

configs/xilinx_zynqmp_zcu102_defconfig +4 -0

index 6f1cff8..64c032d 100644
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"

@@ -27,6 +30,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y

configs/xilinx_zynqmp_zcu102_revB_defconfig +3 -0

index a8982a0..39e341c 100644
@@ -2,6 +2,9 @@ CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ZYNQMP_QSPI=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"