MIPS cache cleanups

PATCH New Paul Burton 2 participants 7 messages May 27, 2016 – May 31, 2016 MIPS

Share & tools

Paul Burton

author

2016-05-27 13:28 UTC #0 lore raw

v2 cover MIPS cache cleanups

This short series cleans up the MIPS cache code in preparation for introducing support for L2 cache support. It's hopefully a useful standalone cleanup as-is, so I'll submit it now.

Applies atop u-boot-mips/next as of 43aaa7696cd7.

Paul Burton (3):
MIPS: Move cache sizes to Kconfig
MIPS: Split I & D cache line size config
MIPS: Abstract cache op loops with a macro

 arch/mips/Kconfig                | 34 +++++++++++++++++
 arch/mips/include/asm/cache.h    |  7 ++++
 arch/mips/lib/cache.c            | 79 ++++++++++++----------------------------
 arch/mips/lib/cache_init.S       | 10 ++---
 board/dbau1x00/Kconfig           | 12 ++++++
 board/micronas/vct/Kconfig       | 12 ++++++
 board/pb1x00/Kconfig             | 12 ++++++
 board/qca/ap121/Kconfig          | 12 ++++++
 board/qca/ap143/Kconfig          | 12 ++++++
 board/qemu-mips/Kconfig          | 12 ++++++
 board/tplink/wdr4300/Kconfig     | 12 ++++++
 include/configs/ap121.h          |  5 ---
 include/configs/ap143.h          |  5 ---
 include/configs/dbau1x00.h       |  7 ----
 include/configs/pb1x00.h         |  6 ---
 include/configs/qemu-mips.h      |  7 ----
 include/configs/qemu-mips64.h    |  7 ----
 include/configs/tplink_wdr4300.h |  5 ---
 include/configs/vct.h            |  7 ----
 19 files changed, 154 insertions(+), 109 deletions(-)

Signature · 1 line

2.8.3

Paul Burton

author

2016-05-27 13:28 UTC #1 lore raw

PATCH v2 1/3 MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0).

Signed-off-by Paul Burton <[email protected]>

---

Changes in v2:
- Add help text to Kconfig entries.
- Use int, not hex, for cache size Kconfig entries.
- Introduce CONFIG_SYS_CACHE_SIZE_AUTO.

 arch/mips/Kconfig                | 28 ++++++++++++++++++++++++++++
 arch/mips/lib/cache.c            |  2 +-
 arch/mips/lib/cache_init.S       |  6 +++---
 board/dbau1x00/Kconfig           |  9 +++++++++
 board/micronas/vct/Kconfig       |  9 +++++++++
 board/pb1x00/Kconfig             |  9 +++++++++
 board/qca/ap121/Kconfig          |  9 +++++++++
 board/qca/ap143/Kconfig          |  9 +++++++++
 board/qemu-mips/Kconfig          |  9 +++++++++
 board/tplink/wdr4300/Kconfig     |  9 +++++++++
 include/configs/ap121.h          |  5 -----
 include/configs/ap143.h          |  5 -----
 include/configs/dbau1x00.h       |  7 -------
 include/configs/pb1x00.h         |  6 ------
 include/configs/qemu-mips.h      |  7 -------
 include/configs/qemu-mips64.h    |  7 -------
 include/configs/tplink_wdr4300.h |  5 -----
 include/configs/vct.h            |  7 -------
 18 files changed, 95 insertions(+), 53 deletions(-)

arch/mips/Kconfig +28 -0

index abaeaf0..043d3d8 100644
@@ -243,6 +243,34 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 	bool
 
+config SYS_DCACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+	int
+	default 0
+	help
+	  The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+		SYS_CACHELINE_SIZE = 0
+	help
+	  Select this (or let it be auto-selected by not defining any cache
+	  sizes) in order to allow U-Boot to automatically detect the sizes
+	  of caches at runtime. This has a small cost in code size & runtime
+	  so if you know the cache configuration for your system at compile
+	  time it would be beneficial to configure it.
+
 config MIPS_L1_CACHE_SHIFT_4
 	bool

arch/mips/lib/cache.c +1 -1

index 7482005..fbaafee 100644
@@ -9,7 +9,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 
 static inline unsigned long icache_line_size(void)
 {

arch/mips/lib/cache_init.S +3 -3

index 08b7c3a..4bb9a17 100644
@@ -99,14 +99,14 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t2, CONFIG_SYS_ICACHE_SIZE
 	li	t8, CONFIG_SYS_CACHELINE_SIZE
 #else
 	l1_info	t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t3, CONFIG_SYS_DCACHE_SIZE
 	li	t9, CONFIG_SYS_CACHELINE_SIZE
 #else

@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
 	/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
 	li	v0, CONFIG_SYS_ICACHE_SIZE
 #else

board/dbau1x00/Kconfig +9 -0

index 342ec59..1715a28 100644
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0xbfc00000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 menu "dbau1x00 board options"
 
 choice

board/micronas/vct/Kconfig +9 -0

index 535a77b..5bb6f03 100644
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x87000000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 menu "vct board options"
 
 choice

board/pb1x00/Kconfig +9 -0

index 236a410..27b2ef0 100644
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x83800000
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif

board/qca/ap121/Kconfig +9 -0

index c3ecc8f..f28ea1c 100644
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x9f000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif

board/qca/ap143/Kconfig +9 -0

index 5ea5d6f..ff02236 100644
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0x9f000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif

board/qemu-mips/Kconfig +9 -0

index 3de1f44..66957e7 100644
@@ -11,4 +11,13 @@ config SYS_TEXT_BASE
 	default 0xbfc00000 if 32BIT
 	default 0xffffffffbfc00000 if 64BIT
 
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif

board/tplink/wdr4300/Kconfig +9 -0

index 65785bd..ded7f9b 100644
@@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
 	default 0xa1000000
 
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_CACHELINE_SIZE
+	default 32
+
 endif

include/configs/ap121.h +0 -5

index 6f69f31..f069d50 100644
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  200
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

include/configs/ap143.h +0 -5

index f907c02..e45f743 100644
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  325
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

include/configs/dbau1x00.h +0 -7

index 68d9e36..68ff025 100644
@@ -202,11 +202,4 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif	/* __CONFIG_H */

include/configs/pb1x00.h +0 -6

index 869768a..b907419 100644
@@ -144,12 +144,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * BOOTP options

include/configs/qemu-mips.h +0 -7

index 246ee01..f58fc4c 100644
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */

include/configs/qemu-mips64.h +0 -7

index 60a3a71..2190d16 100644
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */

include/configs/tplink_wdr4300.h +0 -5

index 09a69fe..6273711 100644
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ			280
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		0x8000
-#define CONFIG_SYS_ICACHE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN		0x40000

include/configs/vct.h +0 -7

index 68eb089..cc5e354 100644
@@ -204,13 +204,6 @@
 #endif /* CONFIG_VCT_ONENAND */
 
 /*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
  * I2C/EEPROM
  */
 #define CONFIG_SYS_I2C

Signature · 1 line

2.8.3

Daniel Schwierzeck

2016-05-31 08:02 UTC #2 lore raw

PATCH v2 1/3 MIPS: Move cache sizes to Kconfig

Am 27.05.2016 um 15:28 schrieb Paul Burton:

Quoted 28 lines

Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0).
Signed-off-by Paul Burton <[email protected]>
---
Changes in v2:
- Add help text to Kconfig entries.
- Use int, not hex, for cache size Kconfig entries.
- Introduce CONFIG_SYS_CACHE_SIZE_AUTO.
 arch/mips/Kconfig                | 28 ++++++++++++++++++++++++++++
 arch/mips/lib/cache.c            |  2 +-
 arch/mips/lib/cache_init.S       |  6 +++---
 board/dbau1x00/Kconfig           |  9 +++++++++
 board/micronas/vct/Kconfig       |  9 +++++++++
 board/pb1x00/Kconfig             |  9 +++++++++
 board/qca/ap121/Kconfig          |  9 +++++++++
 board/qca/ap143/Kconfig          |  9 +++++++++
 board/qemu-mips/Kconfig          |  9 +++++++++
 board/tplink/wdr4300/Kconfig     |  9 +++++++++
 include/configs/ap121.h          |  5 -----

Quoted 9 lines

 include/configs/ap143.h          |  5 -----
 include/configs/dbau1x00.h       |  7 -------
 include/configs/pb1x00.h         |  6 ------
 include/configs/qemu-mips.h      |  7 -------
 include/configs/qemu-mips64.h    |  7 -------
 include/configs/tplink_wdr4300.h |  5 -----
 include/configs/vct.h            |  7 -------
 18 files changed, 95 insertions(+), 53 deletions(-)

applied to u-boot-mips, thanks!

Signature · 9 lines

- Daniel

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160531/45d0d9b7/attachment.sig>

Paul Burton

author

2016-05-27 13:28 UTC #3 lore raw

PATCH v2 2/3 MIPS: Split I & D cache line size config

In reply to Paul Burton

Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence.

Signed-off-by Paul Burton <[email protected]>

---

Changes in v2:
- Provide CONFIG_SYS_CACHELINE_SIZE as a synonym for ARCH_DMA_MINALIGN to avoid breaking drivers that use it for now.

 arch/mips/Kconfig             | 12 +++++++++---
 arch/mips/include/asm/cache.h |  7 +++++++
 arch/mips/lib/cache.c         | 22 +++++++---------------
 arch/mips/lib/cache_init.S    |  4 ++--
 board/dbau1x00/Kconfig        |  5 ++++-
 board/micronas/vct/Kconfig    |  5 ++++-
 board/pb1x00/Kconfig          |  5 ++++-
 board/qca/ap121/Kconfig       |  5 ++++-
 board/qca/ap143/Kconfig       |  5 ++++-
 board/qemu-mips/Kconfig       |  5 ++++-
 board/tplink/wdr4300/Kconfig  |  5 ++++-
 11 files changed, 53 insertions(+), 27 deletions(-)

arch/mips/Kconfig +9 -3

index 043d3d8..1045308 100644
@@ -249,21 +249,27 @@ config SYS_DCACHE_SIZE
 	help
 	  The total size of the L1 Dcache, if known at compile time.
 
+config SYS_DCACHE_LINE_SIZE
+	hex
+	default 0
+	help
+	  The size of L1 Dcache lines, if known at compile time.
+
 config SYS_ICACHE_SIZE
 	int
 	default 0
 	help
 	  The total size of the L1 ICache, if known at compile time.
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	int
 	default 0
 	help
-	  The size of L1 cache lines, if known at compile time.
+	  The size of L1 Icache lines, if known at compile time.
 
 config SYS_CACHE_SIZE_AUTO
 	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
-		SYS_CACHELINE_SIZE = 0
+		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
 	help
 	  Select this (or let it be auto-selected by not defining any cache
 	  sizes) in order to allow U-Boot to automatically detect the sizes

arch/mips/include/asm/cache.h +7 -0

index 806bd26..0cea581 100644
@@ -12,4 +12,11 @@
 
 #define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
 
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
 #endif /* __MIPS_CACHE_H__ */

arch/mips/lib/cache.c +7 ~~-15~~

index fbaafee..19a42ff 100644
@@ -9,23 +9,13 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
-
 static inline unsigned long icache_line_size(void)
 {
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
+	unsigned long conf1, il;
 
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_ICACHE_LINE_SIZE;
 
-static inline unsigned long icache_line_size(void)
-{
-	unsigned long conf1, il;
 	conf1 = read_c0_config1();
 	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
 	if (!il)

@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
 static inline unsigned long dcache_line_size(void)
 {
 	unsigned long conf1, dl;
+
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_DCACHE_LINE_SIZE;
+
 	conf1 = read_c0_config1();
 	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
 	if (!dl)

@@ -43,8 +37,6 @@ static inline unsigned long dcache_line_size(void)
 	return 2 << dl;
 }
 
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
-
 void flush_cache(ulong start_addr, ulong size)
 {
 	unsigned long ilsize = icache_line_size();

arch/mips/lib/cache_init.S +2 -2

index 4bb9a17..bc8ab27 100644
@@ -101,14 +101,14 @@
 LEAF(mips_cache_reset)
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t2, CONFIG_SYS_ICACHE_SIZE
-	li	t8, CONFIG_SYS_CACHELINE_SIZE
+	li	t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
 	l1_info	t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t3, CONFIG_SYS_DCACHE_SIZE
-	li	t9, CONFIG_SYS_CACHELINE_SIZE
+	li	t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
 	l1_info	t3, t9, MIPS_CONF1_DA_SHF
 #endif

board/dbau1x00/Kconfig +4 -1

index 1715a28..448176d 100644
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 menu "dbau1x00 board options"

board/micronas/vct/Kconfig +4 -1

index 5bb6f03..df7c029 100644
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 menu "vct board options"

board/pb1x00/Kconfig +4 -1

index 27b2ef0..ef8905d 100644
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif

board/qca/ap121/Kconfig +4 -1

index f28ea1c..4fd6a71 100644
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif

board/qca/ap143/Kconfig +4 -1

index ff02236..74c632a 100644
@@ -15,10 +15,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif

board/qemu-mips/Kconfig +4 -1

index 66957e7..e696a12 100644
@@ -14,10 +14,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 16384
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 16384
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif

board/tplink/wdr4300/Kconfig +4 -1

index ded7f9b..67a0228 100644
@@ -18,10 +18,13 @@ config SYS_TEXT_BASE
 config SYS_DCACHE_SIZE
 	default 32768
 
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
 config SYS_ICACHE_SIZE
 	default 65536
 
-config SYS_CACHELINE_SIZE
+config SYS_ICACHE_LINE_SIZE
 	default 32
 
 endif

Signature · 1 line

2.8.3

Daniel Schwierzeck

2016-05-31 08:03 UTC #4 lore raw

PATCH v2 2/3 MIPS: Split I & D cache line size config

Am 27.05.2016 um 15:28 schrieb Paul Burton:

Quoted 13 lines

Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence.
Signed-off-by Paul Burton <[email protected]>
---
Changes in v2:
- Provide CONFIG_SYS_CACHELINE_SIZE as a synonym for ARCH_DMA_MINALIGN to avoid breaking drivers that use it for now.

Quoted 13 lines

 arch/mips/Kconfig             | 12 +++++++++---
 arch/mips/include/asm/cache.h |  7 +++++++
 arch/mips/lib/cache.c         | 22 +++++++---------------
 arch/mips/lib/cache_init.S    |  4 ++--
 board/dbau1x00/Kconfig        |  5 ++++-
 board/micronas/vct/Kconfig    |  5 ++++-
 board/pb1x00/Kconfig          |  5 ++++-
 board/qca/ap121/Kconfig       |  5 ++++-
 board/qca/ap143/Kconfig       |  5 ++++-
 board/qemu-mips/Kconfig       |  5 ++++-
 board/tplink/wdr4300/Kconfig  |  5 ++++-
 11 files changed, 53 insertions(+), 27 deletions(-)

applied to u-boot-mips, thanks!

Signature · 9 lines

- Daniel

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160531/553f4078/attachment.sig>

Paul Burton

author

2016-05-27 13:28 UTC #5 lore raw

PATCH v2 3/3 MIPS: Abstract cache op loops with a macro

In reply to Paul Burton

The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support.

Signed-off-by Paul Burton <[email protected]>

---

Changes in v2: None

 arch/mips/lib/cache.c | 59 ++++++++++++++++-----------------------------------
 1 file changed, 18 insertions(+), 41 deletions(-)

arch/mips/lib/cache.c +18 ~~-41~~

index 19a42ff..5f520c0 100644
@@ -37,82 +37,59 @@ static inline unsigned long dcache_line_size(void)
 	return 2 << dl;
 }
 
+#define cache_loop(start, end, lsize, ops...) do {			\
+	const void *addr = (const void *)(start & ~(lsize - 1));	\
+	const void *aend = (const void *)((end - 1) & ~(lsize - 1));	\
+	const unsigned int cache_ops[] = { ops };			\
+	unsigned int i;							\
+									\
+	for (; addr <= aend; addr += lsize) {				\
+		for (i = 0; i < ARRAY_SIZE(cache_ops); i++)		\
+			mips_cache(cache_ops[i], addr);			\
+	}								\
+} while (0)
+
 void flush_cache(ulong start_addr, ulong size)
 {
 	unsigned long ilsize = icache_line_size();
 	unsigned long dlsize = dcache_line_size();
-	const void *addr, *aend;
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (size == 0)
 		return;
 
-	addr = (const void *)(start_addr & ~(dlsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
 	if (ilsize == dlsize) {
 		/* flush I-cache & D-cache simultaneously */
-		while (1) {
-			mips_cache(HIT_WRITEBACK_INV_D, addr);
-			mips_cache(HIT_INVALIDATE_I, addr);
-			if (addr == aend)
-				break;
-			addr += dlsize;
-		}
+		cache_loop(start_addr, start_addr + size, ilsize,
+			   HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
 		return;
 	}
 
 	/* flush D-cache */
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += dlsize;
-	}
+	cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
 
 	/* flush I-cache */
-	addr = (const void *)(start_addr & ~(ilsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
-	while (1) {
-		mips_cache(HIT_INVALIDATE_I, addr);
-		if (addr == aend)
-			break;
-		addr += ilsize;
-	}
+	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_INVALIDATE_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
 }

Signature · 1 line

2.8.3

Daniel Schwierzeck

2016-05-31 08:03 UTC #6 lore raw

PATCH v2 3/3 MIPS: Abstract cache op loops with a macro

Am 27.05.2016 um 15:28 schrieb Paul Burton:

Quoted 7 lines

The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support.

Quoted 9 lines

Signed-off-by Paul Burton <[email protected]>
---
Changes in v2: None
 arch/mips/lib/cache.c | 59 ++++++++++++++++-----------------------------------
 1 file changed, 18 insertions(+), 41 deletions(-)

applied to u-boot-mips, thanks!

Signature · 9 lines

- Daniel

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 473 bytes
Desc: OpenPGP digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20160531/03e60184/attachment-0001.sig>