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mips: ath79: ap121: Enable ethernet

PATCH New Wills Wang 4 participants 16 messages May 30, 2016 – May 31, 2016 1 message not in the archive MIPS

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A message that is not in the archive (sent off-list or not yet received): [email protected]

Wills Wang

author
#1 lore raw

PATCH 2/6 mips: ath79: ap121: Enable ethernet

This patch enable network function for ap121 board.

Signed-off-by Wills Wang <[email protected]>
Acked-by Marek Vasut <[email protected]>

---

 arch/mips/dts/ap121.dts   | 5 +++++
 arch/mips/dts/ar933x.dtsi | 4 ++--
 board/qca/ap121/ap121.c   | 2 ++
 configs/ap121_defconfig   | 9 +++++++--
 4 files changed, 16 insertions(+), 4 deletions(-)
arch/mips/dts/ap121.dts +5 -0
index e31f601..a934a58 100644
@@ -41,3 +41,8 @@
 		reg = <0>;
 	};
 };
+
+&gmac0 {
+	phy-mode = "rmii";
+	status = "okay";
+};
arch/mips/dts/ar933x.dtsi +2 -2
index 00896b2..971f13e 100644
@@ -75,7 +75,7 @@
 			};
 
 			gmac0: eth at 0x19000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x19000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rmii";

@@ -92,7 +92,7 @@
 			};
 
 			gmac1: eth at 0x1a000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x1a000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rgmii";
board/qca/ap121/ap121.c +2 -0
index d6c60fe..e245faa 100644
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -46,5 +47,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
configs/ap121_defconfig +7 -2
index 7604e2e..91fa734 100644
@@ -19,8 +19,13 @@ CONFIG_SYS_PROMPT="ap121 # "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ATMEL=y
Signature · 1 line
1.9.1
#2 lore raw

PATCH 2/6 mips: ath79: ap121: Enable ethernet

Am 30.05.2016 um 16:54 schrieb Wills Wang:

Quoted 11 lines

This patch enable network function for ap121 board.

Signed-off-by Wills Wang <[email protected]>
Acked-by Marek Vasut <[email protected]>

---

 arch/mips/dts/ap121.dts   | 5 +++++
 arch/mips/dts/ar933x.dtsi | 4 ++--
 board/qca/ap121/ap121.c   | 2 ++
 configs/ap121_defconfig   | 9 +++++++--
 4 files changed, 16 insertions(+), 4 deletions(-)

applied to u-boot-mips, thanks!

Signature · 9 lines
- Daniel

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author
#3 lore raw

PATCH 3/6 mips: ath79: Use 8MB flash profile for mtd partition by default

In reply to a message not in the archive

Change bootm flash address and mtd partition table for 8MB flash profile.

Signed-off-by Wills Wang <[email protected]>

---

 include/configs/ap121.h | 4 ++--
 include/configs/ap143.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)
include/configs/ap121.h +2 -2
index 6f69f31..9537034 100644
@@ -45,13 +45,13 @@
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f650000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
+					"6144k(rootfs),1600k(uImage)," \
 					"64k(NVRAM),64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
include/configs/ap143.h +3 -3
index f907c02..6f19829 100644
@@ -49,14 +49,14 @@
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f680000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
-					"64k(NVRAM),64k(ART)"
+					"6336k(rootfs),1472k(uImage)," \
+					"64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
 #define CONFIG_ENV_IS_IN_SPI_FLASH
Signature · 1 line
1.9.1
#4 lore raw

PATCH 3/6 mips: ath79: Use 8MB flash profile for mtd partition by default

Am 30.05.2016 um 16:54 schrieb Wills Wang:

Quoted 9 lines

Change bootm flash address and mtd partition table for 8MB flash profile.

Signed-off-by Wills Wang <[email protected]>

---

 include/configs/ap121.h | 4 ++--
 include/configs/ap143.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

applied to u-boot-mips, thanks!

Signature · 9 lines
- Daniel

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author
#5 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

In reply to a message not in the archive

Add code to ungate USB and ethernet controller on qca953x

Signed-off-by Wills Wang <[email protected]>

---

 arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/mips/mach-ath79/reset.c +50 -0
index 33bf979..a5ee141 100644
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
 	return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_eth_reset(void)
 {
 	/*

@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
 		return eth_init_ar933x();
 	if (soc_is_ar934x())
 		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
 	return -EINVAL;
 }

@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
 	return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_usb_reset(void)
 {
 	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
 		return usb_reset_ar933x(reset_regs);
 	if (soc_is_ar934x())
 		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
 	return -EINVAL;
 }
Signature · 1 line
1.9.1
#6 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

Quoted 1 line · Wills Wang

Add code to ungate USB and ethernet controller on qca953x

Is this code coming from mainline Linux ?

Quoted 89 lines
Signed-off-by Wills Wang <[email protected]>

---

 arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/mips/mach-ath79/reset.c +50 -0
index 33bf979..a5ee141 100644
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
 	return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_eth_reset(void)
 {
 	/*

@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
 		return eth_init_ar933x();
 	if (soc_is_ar934x())
 		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
 	return -EINVAL;
 }

@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
 	return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_usb_reset(void)
 {
 	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
 		return usb_reset_ar933x(reset_regs);
 	if (soc_is_ar934x())
 		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
 	return -EINVAL;
 }
Signature · 2 lines
Best regards,
Marek Vasut
author
#7 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

Quoted 3 lines · Marek Vasut
Quoted 1 line · Wills Wang

Add code to ungate USB and ethernet controller on qca953x

Is this code coming from mainline Linux ?

No, i refer to u-boot code from QSDK.

Quoted 90 lines
Quoted 89 lines
Signed-off-by Wills Wang <[email protected]>

---

  arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 50 insertions(+)
arch/mips/mach-ath79/reset.c +50 -0
index 33bf979..a5ee141 100644
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
  	return 0;
  }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
  int ath79_eth_reset(void)
  {
  	/*

@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
  		return eth_init_ar933x();
  	if (soc_is_ar934x())
  		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
  	return -EINVAL;
  }

@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
  	return 0;
  }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
  int ath79_usb_reset(void)
  {
  	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
  		return usb_reset_ar933x(reset_regs);
  	if (soc_is_ar934x())
  		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
  	return -EINVAL;
  }
Signature · 2 lines
Best Regards
Wills
#8 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

Quoted 8 lines · Wills Wang
Quoted 3 lines · Marek Vasut
Quoted 1 line · Wills Wang

Add code to ungate USB and ethernet controller on qca953x

Is this code coming from mainline Linux ?

No, i refer to u-boot code from QSDK.

Oh ok. I'd suggest to pick the code from mainline Linux when possible, it's far more maintained than the ancient LSDK/QSDK.

Quoted 46 lines
Quoted 46 lines
Quoted 46 lines
Signed-off-by Wills Wang <[email protected]>

---

  arch/mips/mach-ath79/reset.c | 50
++++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 50 insertions(+)
arch/mips/mach-ath79/reset.c +18 -0
index 33bf979..a5ee141 100644
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
      return 0;
  }
  +static int eth_init_qca953x(void)
+{
+    void __iomem *rregs = map_physmem(AR71XX_RESET_BASE,
 AR71XX_RESET_SIZE,
+                      MAP_NOCACHE);
+    const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+             QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+             QCA953X_RESET_ETH_SWITCH_ANALOG |
+             QCA953X_RESET_ETH_SWITCH;
+
+    setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+    mdelay(1);
+    clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+    mdelay(1);
+
+    return 0;
+}
+
  int ath79_eth_reset(void)
  {
      /*

@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
          return eth_init_ar933x();
      if (soc_is_ar934x())
          return eth_init_ar934x();
+    if (soc_is_qca953x())
+        return eth_init_qca953x();
        return -EINVAL;
  }

@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem
 *reset_regs)
      return 0;
Quoted 8 lines
Quoted 8 lines

arch/mips/mach-ath79/reset.c static int usb_reset_ar934x(void __iomem *reset_regs) · line 213

Quoted 8 lines
arch/mips/mach-ath79/reset.c +6 -0
  }
  +static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+                      MAP_NOCACHE);
+
+    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+            0xf00, 0x200);

Do you know what these magic numbers mean ?

Quoted 36 lines
Quoted 35 lines
Quoted 34 lines
arch/mips/mach-ath79/reset.c +24 -0
+    mdelay(10);
+
+    /* Ungate the USB block */
+    setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USBSUS_OVERRIDE);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_ANALOG);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_HOST);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+    mdelay(1);
+
+    return 0;
+}
+
  int ath79_usb_reset(void)
  {
      void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
          return usb_reset_ar933x(reset_regs);
      if (soc_is_ar934x())
          return usb_reset_ar934x(reset_regs);
+    if (soc_is_qca953x())
+        return usb_reset_qca953x(reset_regs);
        return -EINVAL;
  }
Signature · 2 lines
Best regards,
Marek Vasut
#9 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

Hello,

2016-05-31 2:51 GMT+02:00 Marek Vasut <[email protected]>:

Quoted 1 line · Wills Wang

[snip]

Quoted 9 lines
Quoted 7 lines
Quoted 7 lines

arch/mips/mach-ath79/reset.c static int usb_reset_ar934x(void __iomem *reset_regs) · line 213

Quoted 7 lines

+static int usb_reset_qca953x(void __iomem *reset_regs)

arch/mips/mach-ath79/reset.c +6 -0
+{
+    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+                      MAP_NOCACHE);
+
+    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+            0xf00, 0x200);

Do you know what these magic numbers mean ?

I can help here.

This register is common for (almost) all modern QC/A WiSOCs, with similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x (please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses (offset +/- 1), depending on the SOC.

The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.

I'm going to provide some patches for ath79 in future, which will make code more universal for all QC/A WiSOCs.

--
Regards,
Piotr Dymacz

[1] http://postimg.org/image/tyrkhkw57/full/

Quoted 45 lines
Quoted 27 lines
Quoted 27 lines
Quoted 27 lines
arch/mips/mach-ath79/reset.c +22 -0
+    mdelay(10);
+
+    /* Ungate the USB block */
+    setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USBSUS_OVERRIDE);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_ANALOG);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_HOST);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+    mdelay(1);
+
+    return 0;
+}
+
  int ath79_usb_reset(void)
  {
      void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
          return usb_reset_ar933x(reset_regs);
Quoted 9 lines
Quoted 8 lines

arch/mips/mach-ath79/reset.c int ath79_usb_reset(void)

Quoted 7 lines
arch/mips/mach-ath79/reset.c +2 -0
      if (soc_is_ar934x())
          return usb_reset_ar934x(reset_regs);
+    if (soc_is_qca953x())
+        return usb_reset_qca953x(reset_regs);
        return -EINVAL;
  }

--
Best regards,
Marek Vasut
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#10 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

Quoted 26 lines · Piotr Dymacz

Hello,

2016-05-31 2:51 GMT+02:00 Marek Vasut <[email protected]>:

Quoted 1 line · Wills Wang

[snip]

Quoted 9 lines
Quoted 7 lines
Quoted 7 lines

arch/mips/mach-ath79/reset.c static int usb_reset_ar934x(void __iomem *reset_regs) · line 213

Quoted 7 lines

+static int usb_reset_qca953x(void __iomem *reset_regs)

arch/mips/mach-ath79/reset.c +6 -0
+{
+    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+                      MAP_NOCACHE);
+
+    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+            0xf00, 0x200);

Do you know what these magic numbers mean ?

I can help here.

This register is common for (almost) all modern QC/A WiSOCs, with similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x (please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses (offset +/- 1), depending on the SOC.

Quoted 5 lines

The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.

I'm going to provide some patches for ath79 in future, which will make code more universal for all QC/A WiSOCs.

Oh, very cool, thanks!

Signature · 2 lines
Best regards,
Marek Vasut
author
#11 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

In reply to Piotr Dymacz
Quoted 23 lines · Piotr Dymacz

Hello,

2016-05-31 2:51 GMT+02:00 Marek Vasut <[email protected]>:

Quoted 1 line · Wills Wang

[snip]

Quoted 8 lines
Quoted 7 lines
Quoted 7 lines

arch/mips/mach-ath79/reset.c static int usb_reset_ar934x(void __iomem *reset_regs) · line 213

Quoted 7 lines

+static int usb_reset_qca953x(void __iomem *reset_regs)

arch/mips/mach-ath79/reset.c +6 -0
+{
+    void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+                      MAP_NOCACHE);
+
+    clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+            0xf00, 0x200);

Do you know what these magic numbers mean ?

I can help here.

This register is common for (almost) all modern QC/A WiSOCs, with similar structure, at least for AR934x, QCA953x, QCA955x and QCA956x (please take a look at [1]).
I have seen it (SDK, datasheets) under two different names:
SWITCH_CLOCK_SPARE and SWITCH_CLOCK_CONTROL, on different addresses (offset +/- 1), depending on the SOC.

Quoted 2 lines

The bit field [8:11] is "USB_REFCLK_FREQ_SEL" and it's the same for all above SOCs. Value (dec) 2 is for 25 MHz, value 5 for 40 MHz.

You are right, i found the same description in ar9341 data sheet.

Quoted 2 lines

I'm going to provide some patches for ath79 in future, which will make code more universal for all QC/A WiSOCs.

You are always welcome.

Quoted 48 lines

--
Regards,
Piotr Dymacz

[1] http://postimg.org/image/tyrkhkw57/full/

Quoted 42 lines
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
arch/mips/mach-ath79/reset.c +22 -0
+    mdelay(10);
+
+    /* Ungate the USB block */
+    setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USBSUS_OVERRIDE);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_ANALOG);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_HOST);
+    mdelay(1);
+    clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+             QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+    mdelay(1);
+
+    return 0;
+}
+
   int ath79_usb_reset(void)
   {
       void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,

@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
Quoted 8 lines
Quoted 8 lines

arch/mips/mach-ath79/reset.c int ath79_usb_reset(void)

Quoted 8 lines
arch/mips/mach-ath79/reset.c +2 -0
           return usb_reset_ar933x(reset_regs);
       if (soc_is_ar934x())
           return usb_reset_ar934x(reset_regs);
+    if (soc_is_qca953x())
+        return usb_reset_qca953x(reset_regs);
         return -EINVAL;
   }

--
Best regards,
Marek Vasut
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Signature · 2 lines
Best Regards
Wills
#12 lore raw

PATCH 4/6 mips: ath79: Add support for ungating USB and ethernet on qca953x

In reply to Wills Wang

Am 30.05.2016 um 16:54 schrieb Wills Wang:

Quoted 7 lines

Add code to ungate USB and ethernet controller on qca953x

Signed-off-by Wills Wang <[email protected]>

---

 arch/mips/mach-ath79/reset.c | 50 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

applied to u-boot-mips, thanks!

Signature · 9 lines
- Daniel

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author
#13 lore raw

PATCH 5/6 mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

In reply to a message not in the archive

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by Wills Wang <[email protected]>

---

 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
 arch/mips/mach-ath79/reset.c                    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
arch/mips/mach-ath79/include/mach/ar71xx_regs.h +1 -0
index dabcad0..7b48524 100644
@@ -331,6 +331,7 @@
 #define AR933X_PLL_CPU_CONFIG_REG			0x00
 #define AR933X_PLL_CLK_CTRL_REG				0x08
 #define AR933X_PLL_DITHER_FRAC_REG			0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
 
 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT		10
 #define AR933X_PLL_CPU_CONFIG_NINT_MASK			0x3f
arch/mips/mach-ath79/reset.c +1 -1
index a5ee141..073a179 100644
@@ -89,7 +89,7 @@ static int eth_init_ar933x(void)
 	mdelay(10);
 
 	/* Get Atheros S26 PHY out of reset. */
-	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+	clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
 			0x1f, 0x10);
 	mdelay(10);
Signature · 1 line
1.9.1
#14 lore raw

PATCH 5/6 mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define

Am 30.05.2016 um 16:54 schrieb Wills Wang:

Quoted 9 lines

Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip.

Signed-off-by Wills Wang <[email protected]>

---

 arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 +
 arch/mips/mach-ath79/reset.c                    | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

applied to u-boot-mips, thanks!

Signature · 9 lines
- Daniel

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author
#15 lore raw

PATCH 6/6 mips: ath79: ap143: Reset ethernet on boot

In reply to a message not in the archive

This patch reset the ethernet controller for ap143 board

Signed-off-by Wills Wang <[email protected]>

---

 board/qca/ap143/ap143.c | 2 ++
 1 file changed, 2 insertions(+)
board/qca/ap143/ap143.c +2 -0
index 1572472..e921ea5 100644
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -62,5 +63,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
Signature · 1 line
1.9.1
#16 lore raw

PATCH 6/6 mips: ath79: ap143: Reset ethernet on boot

Am 30.05.2016 um 16:54 schrieb Wills Wang:

Quoted 8 lines

This patch reset the ethernet controller for ap143 board

Signed-off-by Wills Wang <[email protected]>

---

 board/qca/ap143/ap143.c | 2 ++
 1 file changed, 2 insertions(+)

applied to u-boot-mips, thanks!

Signature · 9 lines
- Daniel

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