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clk: convert API to match reset/mailbox style

PATCH New Stephen Warren 3 participants 10 messages May 23, 2016 – Jun 8, 2016

Subsystems (14)
Arm (32-bit) USB Arm sub-architectures MIPS +10 more subsystems
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Stephen Warren

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PATCH 1/1 clk: convert API to match reset/mailbox style

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Cc Mateusz Kulikowski <[email protected]>
Cc Daniel Schwierzeck <[email protected]>
Cc Purna Chandra Mandal <[email protected]>
Cc Masahiro Yamada <[email protected]>
Signed-off-by Stephen Warren <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/clock.h   |  12 --
 arch/arm/mach-rockchip/board.c               |  41 +++++-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c |  17 ++-
 arch/arm/mach-snapdragon/clock-apq8016.c     |  10 +-
 arch/arm/mach-zynq/clk.c                     |   1 -
 arch/mips/mach-pic32/cpu.c                   |  47 +++---
 arch/sandbox/dts/test.dts                    |  17 ++-
 arch/sandbox/include/asm/clk.h               |  39 +++++
 arch/sandbox/include/asm/test.h              |   9 --
 board/microchip/pic32mzda/pic32mzda.c        |  23 ++-
 cmd/clk.c                                    |   2 +-
 drivers/clk/Makefile                         |   1 +
 drivers/clk/clk-uclass.c                     | 204 +++++++++++++++++++--------
 drivers/clk/clk_fixed_rate.c                 |  13 +-
 drivers/clk/clk_pic32.c                      |  32 ++---
 drivers/clk/clk_rk3036.c                     |  83 +++--------
 drivers/clk/clk_rk3288.c                     | 141 ++++--------------
 drivers/clk/clk_sandbox.c                    |  85 ++++++-----
 drivers/clk/clk_sandbox_test.c               | 101 +++++++++++++
 drivers/clk/uniphier/clk-uniphier-core.c     |  26 ++--
 drivers/clk/uniphier/clk-uniphier-mio.c      |   1 -
 drivers/gpio/rk_gpio.c                       |   1 -
 drivers/i2c/rk_i2c.c                         |   8 +-
 drivers/mmc/msm_sdhci.c                      |  15 +-
 drivers/mmc/rockchip_dw_mmc.c                |   8 +-
 drivers/mmc/uniphier-sd.c                    |  17 +--
 drivers/serial/serial_msm.c                  |  15 +-
 drivers/serial/serial_pic32.c                |   9 +-
 drivers/spi/rk_spi.c                         |   8 +-
 drivers/usb/host/ehci-generic.c              |  16 +--
 drivers/video/rockchip/rk_edp.c              |  13 +-
 drivers/video/rockchip/rk_hdmi.c             |  14 +-
 drivers/video/rockchip/rk_lvds.c             |   1 -
 drivers/video/rockchip/rk_vop.c              |  13 +-
 include/clk.h                                | 132 -----------------
 include/clk_client.h                         | 174 +++++++++++++++++++++++
 include/clk_uclass.h                         |  95 +++++++++++++
 test/dm/clk.c                                | 110 ++++++++++-----
 38 files changed, 948 insertions(+), 606 deletions(-)
 create mode 100644 arch/sandbox/include/asm/clk.h
 create mode 100644 drivers/clk/clk_sandbox_test.c
 delete mode 100644 include/clk.h
 create mode 100644 include/clk_client.h
 create mode 100644 include/clk_uclass.h
arch/arm/include/asm/arch-rockchip/clock.h +0 -12
index d66b26f18ef3..317e5128ed2b 100644
@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  */
 void *rockchip_get_cru(void);
 
-/**
- * rkclk_get_clk() - get a pointer to a given clock
- *
- * This is an internal function - use outside the clock subsystem indicates
- * that work is needed!
- *
- * @clk_id:	Clock requested
- * @devp:	Returns a pointer to that clock
- * @return 0 if OK, -ve on error
- */
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
-
 struct rk3288_cru;
 struct rk3288_grf;
arch/arm/mach-rockchip/board.c +35 -6

60 lines not on this page · raw message

arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +11 -6
index 2e212823352e..6161be17017c 100644
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <errno.h>
 #include <ram.h>

@@ -36,7 +36,7 @@ struct chan_info {
 struct dram_info {
 	struct chan_info chan[2];
 	struct ram_info info;
-	struct udevice *ddr_clk;
+	struct clk ddr_clk;
 	struct rk3288_cru *cru;
 	struct rk3288_grf *grf;
 	struct rk3288_sgrf *sgrf;

@@ -576,7 +576,7 @@ static void dram_all_config(const struct dram_info *dram,
 	rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
 }
 
-static int sdram_init(const struct dram_info *dram,
+static int sdram_init(struct dram_info *dram,
 		      const struct rk3288_sdram_params *sdram_params)
 {
 	int channel;

@@ -592,8 +592,8 @@ static int sdram_init(const struct dram_info *dram,
 		return -E2BIG;
 	}
 
-	debug("ddr clk %s\n", dram->ddr_clk->name);
-	ret = clk_set_rate(dram->ddr_clk, sdram_params->base.ddr_freq);
+	debug("ddr clk dpll\n");
+	ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
 	debug("ret=%d\n", ret);
 	if (ret) {
 		debug("Could not set DDR clock\n");

@@ -836,6 +836,7 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	struct dram_info *priv = dev_get_priv(dev);
 	struct regmap *map;
 	int ret;
+	struct udevice *dev_clk;
 
 	map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 	if (IS_ERR(map))

@@ -856,7 +857,11 @@ static int rk3288_dmc_probe(struct udevice *dev)
 	priv->chan[1].pctl = regmap_get_range(map, 2);
 	priv->chan[1].publ = regmap_get_range(map, 3);
 
-	ret = uclass_get_device(UCLASS_CLK, CLK_DDR, &priv->ddr_clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
+	if (ret)
+		return ret;
+	priv->ddr_clk.id = CLK_DDR;
+	ret = clk_request(dev_clk, &priv->ddr_clk);
 	if (ret)
 		return ret;
arch/arm/mach-snapdragon/clock-apq8016.c +5 -5
index d548d757d37b..aeccbc271502 100644
@@ -9,7 +9,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <asm/io.h>

@@ -212,11 +212,11 @@ static int clk_init_uart(struct msm_clk_priv *priv)
 	return 0;
 }
 
-ulong msm_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+ulong msm_set_rate(struct clk *clk, ulong rate)
 {
-	struct msm_clk_priv *priv = dev_get_priv(dev);
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
-	switch (periph) {
+	switch (clk->id) {
 	case 0: /* SDC1 */
 		return clk_init_sdc(priv, 0, rate);
 		break;

@@ -243,7 +243,7 @@ static int msm_clk_probe(struct udevice *dev)
 }
 
 static struct clk_ops msm_clk_ops = {
-	.set_periph_rate = msm_set_periph_rate,
+	.set_rate = msm_set_rate,
 };
 
 static const struct udevice_id msm_clk_ids[] = {
arch/arm/mach-zynq/clk.c +0 -1
index 6444be8f0325..40383c11c914 100644
@@ -6,7 +6,6 @@
  */
 #include <common.h>
 #include <errno.h>
-#include <clk.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
arch/mips/mach-pic32/cpu.c +29 -18

84 lines not on this page · raw message

arch/sandbox/dts/test.dts +16 -1
index 879b30e3ccc6..9e46f9e815a6 100644
@@ -108,8 +108,23 @@
 		compatible = "denx,u-boot-fdt-test";
 	};
 
-	clk@0 {
+	clk_fixed: clk-fixed {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1234>;
+	};
+
+	clk_sandbox: clk-sbox {
 		compatible = "sandbox,clk";
+		#clock-cells = <1>;
+	};
+
+	clk-test {
+		compatible = "sandbox,clk-test";
+		clocks = <&clk_fixed>,
+			 <&clk_sandbox 1>,
+			 <&clk_sandbox 0>;
+		clock-names = "fixed", "i2c", "spi";
 	};
 
 	eth at 10002000 {
arch/sandbox/include/asm/clk.h new file +39 -0
new file mode 100644
index 000000000000..7fd2868f9080
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_CLK_H
+#define __SANDBOX_CLK_H
+
+#include <common.h>
+
+struct udevice;
+
+enum {
+	SANDBOX_CLK_ID_SPI,
+	SANDBOX_CLK_ID_I2C,
+
+	SANDBOX_CLK_ID_COUNT,
+};
+
+enum {
+	SANDBOX_CLK_TEST_ID_FIXED,
+	SANDBOX_CLK_TEST_ID_SPI,
+	SANDBOX_CLK_TEST_ID_I2C,
+
+	SANDBOX_CLK_TEST_ID_COUNT,
+};
+
+ulong sandbox_clk_query_rate(struct udevice *dev, int id);
+int sandbox_clk_query_enable(struct udevice *dev, int id);
+
+int sandbox_clk_test_get(struct udevice *dev);
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
+int sandbox_clk_test_enable(struct udevice *dev, int id);
+int sandbox_clk_test_disable(struct udevice *dev, int id);
+int sandbox_clk_test_free(struct udevice *dev);
+
+#endif
arch/sandbox/include/asm/test.h +0 -9
index 224b0ebaf955..451a78e590e3 100644
@@ -19,15 +19,6 @@
 
 #define SANDBOX_CLK_RATE		32768
 
-enum {
-	PERIPH_ID_FIRST = 0,
-	PERIPH_ID_SPI = PERIPH_ID_FIRST,
-	PERIPH_ID_I2C,
-	PERIPH_ID_PCI,
-
-	PERIPH_ID_COUNT,
-};
-
 /* System controller driver data */
 enum {
 	SYSCON0		= 32,
board/microchip/pic32mzda/pic32mzda.c +17 -6
index afe2ab8b7133..ab059a10bc35 100644
@@ -10,21 +10,32 @@
 
 #include <common.h>
 #include <dm.h>
-#include <clk.h>
+#include <clk_client.h>
+#include <dt-bindings/clock/microchip,clock.h>
 #include <mach/pic32.h>
 
 #ifdef CONFIG_DISPLAY_BOARDINFO
 int checkboard(void)
 {
-	ulong rate = 0;
+	ulong rate;
 	struct udevice *dev;
+	struct clk clk;
+	int ret;
 
 	printf("Core: %s\n", get_core_name());
 
-	if (!uclass_get_device(UCLASS_CLK, 0, &dev)) {
-		rate = clk_get_rate(dev);
-		printf("CPU Speed: %lu MHz\n", rate / 1000000);
-	}
+	if (uclass_get_device(UCLASS_CLK, 0, &dev))
+		return 0;
+
+	clk.id = PB7CLK;
+	ret = clk_request(dev, &clk);
+	if (ret < 0)
+		return 0;
+
+	rate = clk_get_rate(&clk);
+	printf("CPU Speed: %lu MHz\n", rate / 1000000);
+
+	clk_free(&clk);
 
 	return 0;
 }
cmd/clk.c +1 -1
index 6d3d46a18447..96aaad3d1aff 100644
@@ -5,7 +5,7 @@
  */
 #include <common.h>
 #include <command.h>
-#include <clk.h>
+#include <clk_client.h>
 
 int __weak soc_clk_dump(void)
 {
drivers/clk/Makefile +1 -0
index c51db1562b64..645f06c99d0d 100644
@@ -9,5 +9,6 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
drivers/clk/clk-uclass.c +146 -58

253 lines not on this page · raw message

drivers/clk/clk_fixed_rate.c +5 -8
index 8beda9cb5572..d12f9e260b05 100644
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_uclass.h>
 #include <dm/device.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -16,19 +16,16 @@ struct clk_fixed_rate {
 
 #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
 
-static ulong clk_fixed_rate_get_rate(struct udevice *dev)
+static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
-	return to_clk_fixed_rate(dev)->fixed_rate;
-}
+	if (clk->id != 0)
+		return -EINVAL;
 
-static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph)
-{
-	return clk_fixed_rate_get_rate(dev);
+	return to_clk_fixed_rate(clk->dev)->fixed_rate;
 }
 
 const struct clk_ops clk_fixed_rate_ops = {
 	.get_rate = clk_fixed_rate_get_rate,
-	.get_periph_rate = clk_fixed_rate_get_periph_rate,
 };
 
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
drivers/clk/clk_pic32.c +12 -20
index 5d883544d513..8dac1b47efac 100644
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_uclass.h>
 #include <dm.h>
 #include <div64.h>
 #include <wait_bit.h>

@@ -339,24 +339,17 @@ static void pic32_clk_init(struct udevice *dev)
 	pic32_mpll_init(priv);
 }
 
-static ulong pic32_clk_get_rate(struct udevice *dev)
+static ulong pic32_get_rate(struct clk *clk)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
-
-	return pic32_get_cpuclk(priv);
-}
-
-static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong rate;
 
-	switch (periph) {
+	switch (clk->id) {
 	case PB1CLK ... PB7CLK:
-		rate = pic32_get_pbclk(priv, periph);
+		rate = pic32_get_pbclk(priv, clk->id);
 		break;
 	case REF1CLK ... REF5CLK:
-		rate = pic32_get_refclk(priv, periph);
+		rate = pic32_get_refclk(priv, clk->id);
 		break;
 	case PLLCLK:
 		rate = pic32_get_pll_rate(priv);

@@ -372,15 +365,15 @@ static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
 	return rate;
 }
 
-static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong pic32_set_rate(struct clk *clk, ulong rate)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong pll_hz;
 
-	switch (periph) {
+	switch (clk->id) {
 	case REF1CLK ... REF5CLK:
 		pll_hz = pic32_get_pll_rate(priv);
-		pic32_set_refclk(priv, periph, pll_hz, rate, ROCLK_SRC_SPLL);
+		pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL);
 		break;
 	default:
 		break;

@@ -390,9 +383,8 @@ static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 }
 
 static struct clk_ops pic32_pic32_clk_ops = {
-	.get_rate = pic32_clk_get_rate,
-	.set_periph_rate = pic32_set_periph_rate,
-	.get_periph_rate = pic32_get_periph_rate,
+	.set_rate = pic32_set_rate,
+	.get_rate = pic32_get_rate,
 };
 
 static int pic32_clk_probe(struct udevice *dev)
drivers/clk/clk_rk3036.c +19 -64

134 lines not on this page · raw message

drivers/clk/clk_rk3288.c +25 -116

243 lines not on this page · raw message

drivers/clk/clk_sandbox.c +53 -32

127 lines not on this page · raw message

drivers/clk/clk_sandbox_test.c new file +101 -0

101 lines not on this page · raw message

drivers/clk/uniphier/clk-uniphier-core.c +13 -13
index 25c163b395dd..b42265b4f1a1 100644
@@ -9,14 +9,14 @@
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
-#include <clk.h>
+#include <clk_uclass.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
 
-static int uniphier_clk_enable(struct udevice *dev, int index)
+static int uniphier_clk_enable(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_gate_data *gate = priv->socdata->gate;
 	unsigned int nr_gate = priv->socdata->nr_gate;
 	void __iomem *reg;

@@ -24,7 +24,7 @@ static int uniphier_clk_enable(struct udevice *dev, int index)
 	int i;
 
 	for (i = 0; i < nr_gate; i++) {
-		if (gate[i].index != index)
+		if (gate[i].index != clk->id)
 			continue;
 
 		reg = priv->base + gate[i].reg;

@@ -41,9 +41,9 @@ static int uniphier_clk_enable(struct udevice *dev, int index)
 	return 0;
 }
 
-static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
+static ulong uniphier_clk_get_rate(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;

@@ -52,7 +52,7 @@ static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
 	int i;
 
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)

@@ -75,9 +75,9 @@ static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
 	return matched_rate;
 }
 
-static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
+static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;

@@ -87,7 +87,7 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 	/* first, decide the best match rate */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)

@@ -105,7 +105,7 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 	/* second, really set registers */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index || rdata[i].rate != best_rate)
+		if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
 			continue;
 
 		reg = priv->base + rdata[i].reg;

@@ -124,8 +124,8 @@ static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
 
 const struct clk_ops uniphier_clk_ops = {
 	.enable = uniphier_clk_enable,
-	.get_periph_rate = uniphier_clk_get_rate,
-	.set_periph_rate = uniphier_clk_set_rate,
+	.get_rate = uniphier_clk_get_rate,
+	.set_rate = uniphier_clk_set_rate,
 };
 
 int uniphier_clk_probe(struct udevice *dev)
drivers/clk/uniphier/clk-uniphier-mio.c +0 -1
index a2b0e80a3394..7003e378be73 100644
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <clk.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
drivers/gpio/rk_gpio.c +0 -1
index 40e87bd1996a..9d583af64739 100644
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
 #include <syscon.h>
 #include <asm/errno.h>
drivers/i2c/rk_i2c.c +3 -5
index 3fceade61ec7..edf98fa966d2 100644
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <errno.h>
 #include <i2c.h>

@@ -29,10 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define RK_I2C_FIFO_SIZE	32
 
 struct rk_i2c {
-	struct udevice *clk;
+	struct clk clk;
 	struct i2c_regs *regs;
 	unsigned int speed;
-	int clk_id;
 };
 
 static inline void rk_i2c_get_div(int div, int *divh, int *divl)

@@ -55,7 +54,7 @@ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
 	int div, divl, divh;
 
 	/* First get i2c rate from pclk */
-	i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);
+	i2c_rate = clk_get_rate(&i2c->clk);
 
 	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
 	divh = 0;

@@ -362,7 +361,6 @@ static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	return 0;
 }
drivers/mmc/msm_sdhci.c +11 -4
index 1e2a29b825f3..6715dd604dfb 100644
@@ -9,7 +9,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <sdhci.h>
 #include <wait_bit.h>

@@ -49,7 +49,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
 					"clock-frequency", 400000);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,

@@ -61,11 +62,17 @@ static int msm_sdc_clk_init(struct udevice *dev)
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
drivers/mmc/rockchip_dw_mmc.c +3 -5
index cb9e1048d035..d38aeaadf46e 100644
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <dwmmc.h>
 #include <errno.h>

@@ -19,8 +19,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct rockchip_dwmmc_priv {
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	struct dwmci_host host;
 };
 

@@ -30,7 +29,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = clk_set_periph_rate(priv->clk, priv->periph, freq);
+	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);
 		return ret;

@@ -73,7 +72,6 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
-	priv->periph = ret;
 
 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
 				 "clock-freq-min-max", minmax, 2))
drivers/mmc/uniphier-sd.c +9 -8
index 81a80cdbc2ca..7aa45965de48 100644
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <fdtdec.h>
 #include <mapmem.h>
 #include <mmc.h>

@@ -651,8 +651,7 @@ int uniphier_sd_probe(struct udevice *dev)
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	fdt_addr_t base;
-	struct udevice *clk_dev;
-	int clk_id;
+	struct clk clk;
 	int ret;
 
 	priv->dev = dev;

@@ -665,20 +664,22 @@ int uniphier_sd_probe(struct udevice *dev)
 	if (!priv->regbase)
 		return -ENOMEM;
 
-	clk_id = clk_get_by_index(dev, 0, &clk_dev);
-	if (clk_id < 0) {
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
 		dev_err(dev, "failed to get host clock\n");
-		return clk_id;
+		return ret;
 	}
 
 	/* set to max rate */
-	priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX);
+	priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 	if (IS_ERR_VALUE(priv->mclk)) {
 		dev_err(dev, "failed to set rate for host clock\n");
+		clk_free(&clk);
 		return priv->mclk;
 	}
 
-	ret = clk_enable(clk_dev, clk_id);
+	ret = clk_enable(&clk);
+	clk_free(&clk);
 	if (ret) {
 		dev_err(dev, "failed to enable host clock\n");
 		return ret;
drivers/serial/serial_msm.c +11 -4
index 80fb89ea8b05..cbb00d7f689a 100644
@@ -10,7 +10,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <errno.h>
 #include <serial.h>

@@ -150,7 +150,8 @@ static int msm_uart_clk_init(struct udevice *dev)
 					"clock-frequency", 115200);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,

@@ -162,11 +163,17 @@ static int msm_uart_clk_init(struct udevice *dev)
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
drivers/serial/serial_pic32.c +5 -4
index af9fbbf65544..0e90f9cfb753 100644
@@ -5,7 +5,7 @@
  *
  */
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <serial.h>
 #include <wait_bit.h>

@@ -135,7 +135,7 @@ static int pic32_uart_getc(struct udevice *dev)
 static int pic32_uart_probe(struct udevice *dev)
 {
 	struct pic32_uart_priv *priv = dev_get_priv(dev);
-	struct udevice *clkdev;
+	struct clk clk;
 	fdt_addr_t addr;
 	fdt_size_t size;
 	int ret;

@@ -148,10 +148,11 @@ static int pic32_uart_probe(struct udevice *dev)
 	priv->base = ioremap(addr, size);
 
 	/* get clock rate */
-	ret = clk_get_by_index(dev, 0, &clkdev);
+	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
-	priv->uartclk = clk_get_periph_rate(clkdev, ret);
+	priv->uartclk = clk_get_rate(&clk);
+	clk_free(&clk);
 
 	/* initialize serial */
 	return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
drivers/spi/rk_spi.c +3 -5
index 9eff423acd12..617487ffdb5c 100644
@@ -10,7 +10,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <dm.h>
 #include <errno.h>
 #include <spi.h>

@@ -35,8 +35,7 @@ struct rockchip_spi_platdata {
 
 struct rockchip_spi_priv {
 	struct rockchip_spi *regs;
-	struct udevice *clk;
-	int clk_id;
+	struct clk clk;
 	unsigned int max_freq;
 	unsigned int mode;
 	ulong last_transaction_us;	/* Time of last transaction end */

@@ -144,7 +143,6 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 					 50000000);

@@ -175,7 +173,7 @@ static int rockchip_spi_probe(struct udevice *bus)
 	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 	 * is the assumed speed for CLK_GENERAL.
 	 */
-	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
+	ret = clk_set_rate(&priv->clk, 99000000);
 	if (ret < 0) {
 		debug("%s: Failed to set clock: %d\n", __func__, ret);
 		return ret;
drivers/usb/host/ehci-generic.c +8 -8
index 4444988e36fc..a2ae917f996b 100644
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <asm/io.h>
 #include <dm.h>
 #include "ehci.h"

@@ -26,15 +26,15 @@ static int ehci_usb_probe(struct udevice *dev)
 	int i;
 
 	for (i = 0; ; i++) {
-		struct udevice *clk_dev;
-		int clk_id;
+		struct clk *clk;
+		int ret;
 
-		clk_id = clk_get_by_index(dev, i, &clk_dev);
-		if (clk_id < 0)
+		ret = clk_get_by_index(dev, i, &clk);
+		if (ret < 0)
 			break;
-		if (clk_enable(clk_dev, clk_id))
-			printf("failed to enable clock (dev=%s, id=%d)\n",
-			       clk_dev->name, clk_id);
+		if (clk_enable(&clk))
+			printf("failed to enable clock %d\n", i);
+		clk_free(&clk);
 	}
 
 	hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
drivers/video/rockchip/rk_edp.c +6 -7
index 124ddf684b51..2cf531399b83 100644
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>

@@ -1009,8 +1009,7 @@ int rk_edp_probe(struct udevice *dev)
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 	struct rk3288_edp *regs = priv->regs;
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	int ret;
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",

@@ -1026,8 +1025,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);

@@ -1036,8 +1035,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 192000000);
+		ret = clk_set_rate(&clk, 192000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
drivers/video/rockchip/rk_hdmi.c +7 -7
index 5fcb61ac2a3e..92535d0dd31d 100644
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>

@@ -859,15 +859,15 @@ static int rk_hdmi_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	struct udevice *reg, *clk;
-	int periph;
+	struct udevice *reg;
+	struct clk clk;
 	int ret;
 	int vop_id = uc_plat->source_id;
 
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);

@@ -880,8 +880,8 @@ static int rk_hdmi_probe(struct udevice *dev)
 	 */
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 384000000);
+		ret = clk_set_rate(&clk, 384000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
drivers/video/rockchip/rk_lvds.c +0 -1
index dc10b866c966..fcbb4d63d25f 100644
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>
drivers/video/rockchip/rk_vop.c +8 -5
index a54af172ec06..9ba7a1134e65 100644
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk_client.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>

@@ -195,7 +195,8 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 	struct udevice *disp;
 	int ret, remote, i, offset;
 	struct display_plat *disp_uc_plat;
-	struct udevice *clk;
+	struct udevice *dev_clk;
+	struct clk clk;
 
 	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
 	debug("vop_id=%d\n", vop_id);

@@ -237,11 +238,13 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
 		return ret;
 	}
 
-	ret = rkclk_get_clk(CLK_NEW, &clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
 	if (!ret) {
-		ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id,
-					  timing.pixelclock.typ);
+		clk.id = DCLK_VOP0 + remote_vop_id;
+		ret = clk_request(dev_clk, &clk);
 	}
+	if (!ret)
+		ret = clk_set_rate(&clk, timing.pixelclock.typ);
 	if (ret) {
 		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 		return ret;
include/clk.h deleted +0 -132

132 lines not on this page · raw message

include/clk_client.h new file +174 -0

174 lines not on this page · raw message

include/clk_uclass.h new file +95 -0

95 lines not on this page · raw message

test/dm/clk.c +77 -33

132 lines not on this page · raw message

Signature · 1 line
2.8.3
author
#1 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Quoted 23 lines · Stephen Warren

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Quoted 5 lines

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Simon, does this look good?

(Note I'll be away on vacation Jun 4-15 so won't be able to respond for a while)

#2 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Hi Stephen,

2016-06-02 19:00 GMT+02:00 Stephen Warren <[email protected]>:

Quoted 25 lines · Stephen Warren
Quoted 24 lines

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Quoted 9 lines
Quoted 5 lines

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Simon, does this look good?

could you rebase the patch to current mainline?. I couldn't apply it some days ago. Thanks.

Signature · 1 line
- Daniel
author
#3 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Quoted 35 lines · Daniel Schwierzeck

Hi Stephen,

2016-06-02 19:00 GMT+02:00 Stephen Warren <[email protected]>:

Quoted 32 lines · Stephen Warren
Quoted 29 lines

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Quoted 5 lines
Quoted 2 lines

Simon, does this look good?

could you rebase the patch to current mainline?. I couldn't apply it some days ago. Thanks.

It seems to work fine for me; see log below. What problem are you seeing?

[swarren at swarren-lx1 u-boot]$ git checkout u-boot/master HEAD is now at 8b528709c5bb... spl: fit: Fix load address of fit header

[swarren at swarren-lx1 u-boot]$ git am -3 -s ~/\[U-Boot\]\ \[PATCH\]\
clk\:\ convert\ API\ to\ match\ reset_mailbox\ style.eml
Applying: clk: convert API to match reset/mailbox style Using index info to reconstruct a base tree...
M arch/sandbox/dts/test.dts
M drivers/clk/clk_rk3288.c
M drivers/clk/uniphier/clk-uniphier-mio.c
M drivers/gpio/rk_gpio.c
M drivers/mmc/rockchip_dw_mmc.c
M drivers/mmc/uniphier-sd.c
M drivers/video/rockchip/rk_vop.c
Falling back to patching base and 3-way merge...
Removing include/clk.h
Auto-merging drivers/video/rockchip/rk_vop.c
Auto-merging drivers/mmc/uniphier-sd.c
Auto-merging drivers/mmc/rockchip_dw_mmc.c
Auto-merging drivers/gpio/rk_gpio.c
Auto-merging drivers/clk/uniphier/clk-uniphier-mio.c Auto-merging drivers/clk/clk_rk3288.c
Auto-merging arch/sandbox/dts/test.dts

#4 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Am 02.06.2016 um 22:03 schrieb Stephen Warren:

Quoted 19 lines
Quoted 2 lines

could you rebase the patch to current mainline?. I couldn't apply it some days ago. Thanks.

It seems to work fine for me; see log below. What problem are you seeing?

[swarren at swarren-lx1 u-boot]$ git checkout u-boot/master HEAD is now at 8b528709c5bb... spl: fit: Fix load address of fit header

[swarren at swarren-lx1 u-boot]$ git am -3 -s ~/\[U-Boot\]\ \[PATCH\]\
clk\:\ convert\ API\ to\ match\ reset_mailbox\ style.eml
Applying: clk: convert API to match reset/mailbox style Using index info to reconstruct a base tree...

M    arch/sandbox/dts/test.dts
M    drivers/clk/clk_rk3288.c
M    drivers/clk/uniphier/clk-uniphier-mio.c
M    drivers/gpio/rk_gpio.c
M    drivers/mmc/rockchip_dw_mmc.c
M    drivers/mmc/uniphier-sd.c
M    drivers/video/rockchip/rk_vop.c
Quoted 10 lines

Falling back to patching base and 3-way merge... Removing include/clk.h
Auto-merging drivers/video/rockchip/rk_vop.c Auto-merging drivers/mmc/uniphier-sd.c Auto-merging drivers/mmc/rockchip_dw_mmc.c Auto-merging drivers/gpio/rk_gpio.c Auto-merging drivers/clk/uniphier/clk-uniphier-mio.c Auto-merging drivers/clk/clk_rk3288.c Auto-merging arch/sandbox/dts/test.dts

I always get this:

daniel at workstation:/work/u-boot$ pwclient get 625342 Saved patch to U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch

daniel at workstation:/work/u-boot$ git am -3 U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch
Applying: clk: convert API to match reset/mailbox style
fatal: sha1 information is lacking or useless (arch/sandbox/dts/test.dts).
error: could not build fake ancestor
Patch failed at 0001 clk: convert API to match reset/mailbox style
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

I'm seeing the same error with "[PATCH] clk: convert API to match reset_mailbox style.eml".

I've tried with git 2.7.4 and 2.8.3 and also with a fresh git clone but nothing helps.

Signature · 9 lines
- Daniel

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#5 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Quoted 48 lines · Daniel Schwierzeck

Am 02.06.2016 um 22:03 schrieb Stephen Warren:

Quoted 19 lines
Quoted 2 lines

could you rebase the patch to current mainline?. I couldn't apply it some days ago. Thanks.

It seems to work fine for me; see log below. What problem are you seeing?

[swarren at swarren-lx1 u-boot]$ git checkout u-boot/master HEAD is now at 8b528709c5bb... spl: fit: Fix load address of fit header

[swarren at swarren-lx1 u-boot]$ git am -3 -s ~/\[U-Boot\]\ \[PATCH\]\
clk\:\ convert\ API\ to\ match\ reset_mailbox\ style.eml
Applying: clk: convert API to match reset/mailbox style Using index info to reconstruct a base tree...

M    arch/sandbox/dts/test.dts
M    drivers/clk/clk_rk3288.c
M    drivers/clk/uniphier/clk-uniphier-mio.c
M    drivers/gpio/rk_gpio.c
M    drivers/mmc/rockchip_dw_mmc.c
M    drivers/mmc/uniphier-sd.c
M    drivers/video/rockchip/rk_vop.c
Quoted 10 lines

Falling back to patching base and 3-way merge... Removing include/clk.h
Auto-merging drivers/video/rockchip/rk_vop.c Auto-merging drivers/mmc/uniphier-sd.c Auto-merging drivers/mmc/rockchip_dw_mmc.c Auto-merging drivers/gpio/rk_gpio.c Auto-merging drivers/clk/uniphier/clk-uniphier-mio.c Auto-merging drivers/clk/clk_rk3288.c Auto-merging arch/sandbox/dts/test.dts

I always get this:

daniel at workstation:/work/u-boot$ pwclient get 625342 Saved patch to U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch

daniel at workstation:/work/u-boot$ git am -3 U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch
Applying: clk: convert API to match reset/mailbox style
fatal: sha1 information is lacking or useless (arch/sandbox/dts/test.dts).
error: could not build fake ancestor
Patch failed at 0001 clk: convert API to match reset/mailbox style
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

Quoted 3 lines

I'm seeing the same error with "[PATCH] clk: convert API to match reset_mailbox style.eml".

I've tried with git 2.7.4 and 2.8.3 and also with a fresh git clone but nothing helps.

Oh right, it looks like "-3" is required to make the commit apply correctly since there have been some minor context changes since I created the patch, and that option uses the file SHA information in the patch, and when I ran "git format-patch" the commit wasn't based directly on upstream (I had some irrelevant intervening commits) so the file SHAs in the patch don't exist outside my local repo, and hence the messages you see.

You can resolve this by:

git fetch git://github.com/swarren/u-boot.git tmp git cherry-pick d0b430a197317dd843a09e33359c251ea5f41e6c

It's probably not worth my reposting the patch until it has comments.

#6 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Am 03.06.2016 um 00:02 schrieb Stephen Warren:

Quoted 66 lines · Daniel Schwierzeck
Quoted 51 lines

Am 02.06.2016 um 22:03 schrieb Stephen Warren:

Quoted 20 lines
Quoted 2 lines

could you rebase the patch to current mainline?. I couldn't apply it some days ago. Thanks.

It seems to work fine for me; see log below. What problem are you seeing?

[swarren at swarren-lx1 u-boot]$ git checkout u-boot/master HEAD is now at 8b528709c5bb... spl: fit: Fix load address of fit header

[swarren at swarren-lx1 u-boot]$ git am -3 -s ~/\[U-Boot\]\ \[PATCH\]\
clk\:\ convert\ API\ to\ match\ reset_mailbox\ style.eml
Applying: clk: convert API to match reset/mailbox style Using index info to reconstruct a base tree...

M    arch/sandbox/dts/test.dts
M    drivers/clk/clk_rk3288.c
M    drivers/clk/uniphier/clk-uniphier-mio.c
M    drivers/gpio/rk_gpio.c
M    drivers/mmc/rockchip_dw_mmc.c
M    drivers/mmc/uniphier-sd.c
M    drivers/video/rockchip/rk_vop.c
Quoted 10 lines

Falling back to patching base and 3-way merge... Removing include/clk.h
Auto-merging drivers/video/rockchip/rk_vop.c Auto-merging drivers/mmc/uniphier-sd.c Auto-merging drivers/mmc/rockchip_dw_mmc.c Auto-merging drivers/gpio/rk_gpio.c Auto-merging drivers/clk/uniphier/clk-uniphier-mio.c Auto-merging drivers/clk/clk_rk3288.c Auto-merging arch/sandbox/dts/test.dts

I always get this:

daniel at workstation:/work/u-boot$ pwclient get 625342 Saved patch to U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch

daniel at workstation:/work/u-boot$ git am -3 U-Boot-clk-convert-API-to-match-reset-mailbox-style.patch
Applying: clk: convert API to match reset/mailbox style
fatal: sha1 information is lacking or useless (arch/sandbox/dts/test.dts).
error: could not build fake ancestor
Patch failed at 0001 clk: convert API to match reset/mailbox style The copy of the patch that failed is found in: .git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".

Quoted 5 lines

I'm seeing the same error with "[PATCH] clk: convert API to match reset_mailbox style.eml".

I've tried with git 2.7.4 and 2.8.3 and also with a fresh git clone but nothing helps.

Oh right, it looks like "-3" is required to make the commit apply correctly since there have been some minor context changes since I created the patch, and that option uses the file SHA information in the patch, and when I ran "git format-patch" the commit wasn't based directly on upstream (I had some irrelevant intervening commits) so the file SHAs in the patch don't exist outside my local repo, and hence the messages you see.

Quoted 7 lines

You can resolve this by:

git fetch git://github.com/swarren/u-boot.git tmp git cherry-pick d0b430a197317dd843a09e33359c251ea5f41e6c

It's probably not worth my reposting the patch until it has comments.

ok, that worked. Thanks.

Signature · 9 lines
- Daniel

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#7 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

In reply to Stephen Warren

Hi Stephen,

Quoted 28 lines · Stephen Warren
Quoted 27 lines · Stephen Warren

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

Quoted 8 lines
Quoted 2 lines

test/py passes for sandbox (which invokes the dm clk test amongst others).

Simon, does this look good?

(Note I'll be away on vacation Jun 4-15 so won't be able to respond for a while)

I am back next week, so will take a look then. I will give it a try on the rockchip device.

Regards,
Simon

#8 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

In reply to Stephen Warren

Hi Stephen,

Quoted 23 lines · Stephen Warren

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Quoted 5 lines

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Sorry for the delay on this. It took more thinking and testing than I had time for before I went away.

It looks really clean to me. Just some minor things I'd like to change.

Acked-by Simon Glass <[email protected]>
Quoted 36 lines
Cc Mateusz Kulikowski <[email protected]>
Cc Daniel Schwierzeck <[email protected]>
Cc Purna Chandra Mandal <[email protected]>
Cc Masahiro Yamada <[email protected]>
Signed-off-by Stephen Warren <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/clock.h   |  12 --
 arch/arm/mach-rockchip/board.c               |  41 +++++-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c |  17 ++-
 arch/arm/mach-snapdragon/clock-apq8016.c     |  10 +-
 arch/arm/mach-zynq/clk.c                     |   1 -
 arch/mips/mach-pic32/cpu.c                   |  47 +++---
 arch/sandbox/dts/test.dts                    |  17 ++-
 arch/sandbox/include/asm/clk.h               |  39 +++++
 arch/sandbox/include/asm/test.h              |   9 --
 board/microchip/pic32mzda/pic32mzda.c        |  23 ++-
 cmd/clk.c                                    |   2 +-
 drivers/clk/Makefile                         |   1 +
 drivers/clk/clk-uclass.c                     | 204 +++++++++++++++++++--------
 drivers/clk/clk_fixed_rate.c                 |  13 +-
 drivers/clk/clk_pic32.c                      |  32 ++---
 drivers/clk/clk_rk3036.c                     |  83 +++--------
 drivers/clk/clk_rk3288.c                     | 141 ++++--------------
 drivers/clk/clk_sandbox.c                    |  85 ++++++-----
 drivers/clk/clk_sandbox_test.c               | 101 +++++++++++++
 drivers/clk/uniphier/clk-uniphier-core.c     |  26 ++--
 drivers/clk/uniphier/clk-uniphier-mio.c      |   1 -
 drivers/gpio/rk_gpio.c                       |   1 -
 drivers/i2c/rk_i2c.c                         |   8 +-
 drivers/mmc/msm_sdhci.c                      |  15 +-
 drivers/mmc/rockchip_dw_mmc.c                |   8 +-
 drivers/mmc/uniphier-sd.c                    |  17 +--
 drivers/serial/serial_msm.c                  |  15 +-
 drivers/serial/serial_pic32.c                |   9 +-
 drivers/spi/rk_spi.c                         |   8 +-
Quoted 8 lines
 drivers/usb/host/ehci-generic.c              |  16 +--
 drivers/video/rockchip/rk_edp.c              |  13 +-
 drivers/video/rockchip/rk_hdmi.c             |  14 +-
 drivers/video/rockchip/rk_lvds.c             |   1 -
 drivers/video/rockchip/rk_vop.c              |  13 +-
 include/clk.h                                | 132 -----------------
 include/clk_client.h                         | 174 +++++++++++++++++++++++
 include/clk_uclass.h                         |  95 +++++++++++++

Can we use clk.h and clk-uclass.h instead? I'm not keen on the _client suffix. Client should be the defauilt.

Quoted 31 lines
 test/dm/clk.c                                | 110 ++++++++++-----
 38 files changed, 948 insertions(+), 606 deletions(-)
 create mode 100644 arch/sandbox/include/asm/clk.h
 create mode 100644 drivers/clk/clk_sandbox_test.c
 delete mode 100644 include/clk.h
 create mode 100644 include/clk_client.h
 create mode 100644 include/clk_uclass.h
arch/arm/include/asm/arch-rockchip/clock.h +0 -12
index d66b26f18ef3..317e5128ed2b 100644
@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  */
 void *rockchip_get_cru(void);
 
-/**
- * rkclk_get_clk() - get a pointer to a given clock
- *
- * This is an internal function - use outside the clock subsystem indicates
- * that work is needed!
- *
- * @clk_id:    Clock requested
- * @devp:      Returns a pointer to that clock
- * @return 0 if OK, -ve on error
- */
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
-
 struct rk3288_cru;
 struct rk3288_grf;

[snip]

Quoted 22 lines
arch/sandbox/include/asm/clk.h new file +16 -0
new file mode 100644
index 000000000000..7fd2868f9080
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_CLK_H
+#define __SANDBOX_CLK_H
+
+#include <common.h>
+
+struct udevice;
+
+enum {
+       SANDBOX_CLK_ID_SPI,
+       SANDBOX_CLK_ID_I2C,

arch/sandbox/include/asm/clk.h line 26

Quoted 10 lines
arch/sandbox/include/asm/clk.h new file +10 -0
+
+       SANDBOX_CLK_ID_COUNT,
+};
+
+enum {
+       SANDBOX_CLK_TEST_ID_FIXED,
+       SANDBOX_CLK_TEST_ID_SPI,
+       SANDBOX_CLK_TEST_ID_I2C,
+
+       SANDBOX_CLK_TEST_ID_COUNT,

What's the difference between these two enums? Can you add a comment to each?

arch/sandbox/include/asm/clk.h line 30

Quoted 4 lines
arch/sandbox/include/asm/clk.h new file +4 -0
+};
+
+ulong sandbox_clk_query_rate(struct udevice *dev, int id);
+int sandbox_clk_query_enable(struct udevice *dev, int id);

Can you add function comments for these?

arch/sandbox/include/asm/clk.h line 37

Quoted 7 lines
arch/sandbox/include/asm/clk.h new file +7 -0
+
+int sandbox_clk_test_get(struct udevice *dev);
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
+int sandbox_clk_test_enable(struct udevice *dev, int id);
+int sandbox_clk_test_disable(struct udevice *dev, int id);
+int sandbox_clk_test_free(struct udevice *dev);

and these?

arch/sandbox/include/asm/clk.h line 39

Quoted 2 lines
arch/sandbox/include/asm/clk.h new file +2 -0
+
+#endif

Regards,
Simon

#9 lore raw

PATCH 1/1 clk: convert API to match reset/mailbox style

Hi Stephen,

Quoted 173 lines · Simon Glass

Hi Stephen,

Quoted 23 lines · Stephen Warren

From: Stephen Warren <[email protected]>

The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings.
* Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API.
* clk.h is split into clk_client.h and clk_uclass.h to make it obvious which parts are relevant to consumers and providers. This aligns with the recently added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.

Quoted 5 lines

Buildman shows no clock-related errors for any board for which buildman can download a toolchain.

test/py passes for sandbox (which invokes the dm clk test amongst others).

Sorry for the delay on this. It took more thinking and testing than I had time for before I went away.

It looks really clean to me. Just some minor things I'd like to change.

Acked-by Simon Glass <[email protected]>
Quoted 36 lines
Cc Mateusz Kulikowski <[email protected]>
Cc Daniel Schwierzeck <[email protected]>
Cc Purna Chandra Mandal <[email protected]>
Cc Masahiro Yamada <[email protected]>
Signed-off-by Stephen Warren <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/clock.h   |  12 --
 arch/arm/mach-rockchip/board.c               |  41 +++++-
 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c |  17 ++-
 arch/arm/mach-snapdragon/clock-apq8016.c     |  10 +-
 arch/arm/mach-zynq/clk.c                     |   1 -
 arch/mips/mach-pic32/cpu.c                   |  47 +++---
 arch/sandbox/dts/test.dts                    |  17 ++-
 arch/sandbox/include/asm/clk.h               |  39 +++++
 arch/sandbox/include/asm/test.h              |   9 --
 board/microchip/pic32mzda/pic32mzda.c        |  23 ++-
 cmd/clk.c                                    |   2 +-
 drivers/clk/Makefile                         |   1 +
 drivers/clk/clk-uclass.c                     | 204 +++++++++++++++++++--------
 drivers/clk/clk_fixed_rate.c                 |  13 +-
 drivers/clk/clk_pic32.c                      |  32 ++---
 drivers/clk/clk_rk3036.c                     |  83 +++--------
 drivers/clk/clk_rk3288.c                     | 141 ++++--------------
 drivers/clk/clk_sandbox.c                    |  85 ++++++-----
 drivers/clk/clk_sandbox_test.c               | 101 +++++++++++++
 drivers/clk/uniphier/clk-uniphier-core.c     |  26 ++--
 drivers/clk/uniphier/clk-uniphier-mio.c      |   1 -
 drivers/gpio/rk_gpio.c                       |   1 -
 drivers/i2c/rk_i2c.c                         |   8 +-
 drivers/mmc/msm_sdhci.c                      |  15 +-
 drivers/mmc/rockchip_dw_mmc.c                |   8 +-
 drivers/mmc/uniphier-sd.c                    |  17 +--
 drivers/serial/serial_msm.c                  |  15 +-
 drivers/serial/serial_pic32.c                |   9 +-
 drivers/spi/rk_spi.c                         |   8 +-
Quoted 8 lines
 drivers/usb/host/ehci-generic.c              |  16 +--
 drivers/video/rockchip/rk_edp.c              |  13 +-
 drivers/video/rockchip/rk_hdmi.c             |  14 +-
 drivers/video/rockchip/rk_lvds.c             |   1 -
 drivers/video/rockchip/rk_vop.c              |  13 +-
 include/clk.h                                | 132 -----------------
 include/clk_client.h                         | 174 +++++++++++++++++++++++
 include/clk_uclass.h                         |  95 +++++++++++++

Can we use clk.h and clk-uclass.h instead? I'm not keen on the _client suffix. Client should be the defauilt.

Quoted 31 lines
 test/dm/clk.c                                | 110 ++++++++++-----
 38 files changed, 948 insertions(+), 606 deletions(-)
 create mode 100644 arch/sandbox/include/asm/clk.h
 create mode 100644 drivers/clk/clk_sandbox_test.c
 delete mode 100644 include/clk.h
 create mode 100644 include/clk_client.h
 create mode 100644 include/clk_uclass.h
arch/arm/include/asm/arch-rockchip/clock.h +0 -12
index d66b26f18ef3..317e5128ed2b 100644
@@ -62,18 +62,6 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
  */
 void *rockchip_get_cru(void);
 
-/**
- * rkclk_get_clk() - get a pointer to a given clock
- *
- * This is an internal function - use outside the clock subsystem indicates
- * that work is needed!
- *
- * @clk_id:    Clock requested
- * @devp:      Returns a pointer to that clock
- * @return 0 if OK, -ve on error
- */
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp);
-
 struct rk3288_cru;
 struct rk3288_grf;

[snip]

Quoted 22 lines
arch/sandbox/include/asm/clk.h new file +16 -0
new file mode 100644
index 000000000000..7fd2868f9080
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_CLK_H
+#define __SANDBOX_CLK_H
+
+#include <common.h>
+
+struct udevice;
+
+enum {
+       SANDBOX_CLK_ID_SPI,
+       SANDBOX_CLK_ID_I2C,

arch/sandbox/include/asm/clk.h line 26

Quoted 10 lines
arch/sandbox/include/asm/clk.h new file +10 -0
+
+       SANDBOX_CLK_ID_COUNT,
+};
+
+enum {
+       SANDBOX_CLK_TEST_ID_FIXED,
+       SANDBOX_CLK_TEST_ID_SPI,
+       SANDBOX_CLK_TEST_ID_I2C,
+
+       SANDBOX_CLK_TEST_ID_COUNT,

What's the difference between these two enums? Can you add a comment to each?

arch/sandbox/include/asm/clk.h line 30

Quoted 4 lines
arch/sandbox/include/asm/clk.h new file +4 -0
+};
+
+ulong sandbox_clk_query_rate(struct udevice *dev, int id);
+int sandbox_clk_query_enable(struct udevice *dev, int id);

Can you add function comments for these?

arch/sandbox/include/asm/clk.h line 37

Quoted 7 lines
arch/sandbox/include/asm/clk.h new file +7 -0
+
+int sandbox_clk_test_get(struct udevice *dev);
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate);
+int sandbox_clk_test_enable(struct udevice *dev, int id);
+int sandbox_clk_test_disable(struct udevice *dev, int id);
+int sandbox_clk_test_free(struct udevice *dev);

and these?

Quoted 3 lines

arch/sandbox/include/asm/clk.h line 39

Quoted 2 lines
arch/sandbox/include/asm/clk.h new file +2 -0
+
+#endif

Also can you please take a look at these build errors?

08: sandbox: gpio: doc: Fix parameter documentation

   aarch64:  +   uniphier_ld11 espresso7420
      mips:  +   tplink_wdr4300
  blackfin:  +   cm-bf527
       arm:  +   uniphier_ld4_sld8 s5pc210_universal uniphier_sld3

smdkc100 odroid peach-pit smdkv310 peach-pi smdk5250 smdk5420 origen odroid-xu3 snow s5p_goni spring arndale trats trats2 -arm-unknown-linux-gnueabi-ld.bfd: region `.sram' overflowed by 44 bytes
+ ret = clk_get_by_index(dev, i, &clk);
+ ^
+In file included from ../drivers/usb/host/ehci-generic.c:8:0:
+../include/clk_client.h:78:5: note: expected 'struct clk *' but
argument is of type 'struct clk **'
+ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+ ^
+ if (clk_enable(&clk))
+ ^
+../include/clk_client.h:161:5: note: expected 'struct clk *' but
argument is of type 'struct clk **'
+ int clk_enable(struct clk *clk);
+ clk_free(&clk);
+ ^
+../include/clk_client.h:133:5: note: expected 'struct clk *' but
argument is of type 'struct clk **'
+ int clk_free(struct clk *clk); +/usr/local/google/c/big/buildall.c/toolchains/bfin-uclinux/bin/../bfin-uclinux/bin/ld.real:
region ram is full (u-boot section .bss)
+make[1]: *** [u-boot] Error 1
+../drivers/serial/serial_s5p.c:20:17: fatal error: clk.h: No such
file or directory
+ #include <clk.h>
+ ^
+compilation terminated.
+make[2]: *** [drivers/serial/serial_s5p.o] Error 1
+make[1]: *** [drivers/serial] Error 2 +../drivers/clk/exynos/clk-exynos7420.c:12:17: fatal error: clk.h: No
such file or directory
+make[4]: *** [drivers/clk/exynos/clk-exynos7420.o] Error 1
+make[3]: *** [drivers/clk/exynos] Error 2
+make[2]: *** [drivers/clk] Error 2
+make[1]: *** [drivers] Error 2
+arm-unknown-linux-gnueabi-ld.bfd: region `.sram' overflowed by 60 bytes w+../drivers/usb/host/ehci-generic.c: In function 'ehci_usb_probe':
w+../drivers/usb/host/ehci-generic.c:32:9: warning: passing argument 3
of 'clk_get_by_index' from incompatible pointer type w+../drivers/usb/host/ehci-generic.c:35:7: warning: passing argument 1
of 'clk_enable' from incompatible pointer type w+../drivers/usb/host/ehci-generic.c:37:3: warning: passing argument 1
of 'clk_free' from incompatible pointer type

(also firefly-rk3288)

Regards,
Simon