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drivers/ddr/fsl: Fix timing_cfg_2 register

PATCH New York Sun 1 participant 2 messages May 19, 2016 – Jun 4, 2016

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York Sun

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PATCH 1/1 drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far.

Signed-off-by York Sun <[email protected]>

---

 drivers/ddr/fsl/ctrl_regs.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ddr/fsl/ctrl_regs.c +1 -1
index 9073917..60fed84 100644
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 14)
+		| ((wr_lat & 0x10) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
Signature · 1 line
1.7.9.5
author Applied
#1 lore raw

PATCH 1/1 drivers/ddr/fsl: Fix timing_cfg_2 register

Quoted 11 lines · York Sun

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far.

Signed-off-by York Sun <[email protected]>

---

 drivers/ddr/fsl/ctrl_regs.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied to fsl-qoriq master branch. Awaiting upstream.

York