armv8: fsl-layerscape: Add support of LS1012A SoC and platform

The QorIQ LS1012A processor is a new Freescale' SoC optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance.

LS1012AQDS, LS1012ARDB and LS1012AFRDM are a high-performance development platform using LS1012A SoC.

Changes for v2: Add support of board, fpga info and qixis_reset for QDS Changes for v3: Incorporated York's comments
Changes for v4:
- Incorporated york's comments
- updated file license
- Incorporated review comments from Edward L Swarthou, Alex
- Removed DDR init magic numbers
Changes for v5: Updated DDR init defines as macro

Abhimanyu Saini (2):
board: freescale: common: Conditionally compile IFC QXIS func
board: freescale: common: Add flag for LBMAP brdcfg reg offset

Prabhakar Kushwaha (9):
armv8: fsl-layerscape: Put SMMU config code in SMMU_BASE
armv8: fsl-layerscape: Avoid LS1043A specifc defines
driver: mtd: spi: Adding support for QSPI flash
armv8: fsl-layerscape: fix compile warning "rcw_tmp"
armv8: fsl-layerscape: Organize SoC overview at common location
armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
armv8: ls1012a: Add support of ls1012aqds board
armv8: ls1012a: Add support of ls1012ardb board
armv8: ls1012a: Add support of ls1012afrdm board

 arch/arm/Kconfig                                   |  30 +++
 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
 .../armv8/fsl-layerscape/{ => doc}/README.lsch2    |   0
 .../armv8/fsl-layerscape/{ => doc}/README.lsch3    |   0
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 129 ++++++++++++
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  16 +-
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |  74 +++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   4 +-
 arch/arm/dts/Makefile                              |   5 +-
 arch/arm/dts/fsl-ls1012a-frdm.dts                  |  16 ++
 arch/arm/dts/fsl-ls1012a-frdm.dtsi                 |  37 ++++
 arch/arm/dts/fsl-ls1012a-qds.dts                   |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi                  | 123 +++++++++++
 arch/arm/dts/fsl-ls1012a-rdb.dts                   |  16 ++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi                  |  39 ++++
 arch/arm/dts/fsl-ls1012a.dtsi                      | 119 +++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  29 +++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   1 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   4 +
 .../include/asm/arch-fsl-layerscape/ns_access.h    |  10 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   1 +
 board/freescale/common/qixis.c                     |  13 +-
 board/freescale/ls1012afrdm/Kconfig                |  15 ++
 board/freescale/ls1012afrdm/MAINTAINERS            |   6 +
 board/freescale/ls1012afrdm/Makefile               |   7 +
 board/freescale/ls1012afrdm/README                 |  58 +++++
 board/freescale/ls1012afrdm/ls1012afrdm.c          | 192 +++++++++++++++++
 board/freescale/ls1012aqds/Kconfig                 |  15 ++
 board/freescale/ls1012aqds/MAINTAINERS             |   6 +
 board/freescale/ls1012aqds/Makefile                |   7 +
 board/freescale/ls1012aqds/README                  |  59 ++++++
 board/freescale/ls1012aqds/ls1012aqds.c            | 234 +++++++++++++++++++++
 board/freescale/ls1012aqds/ls1012aqds_qixis.h      |  35 +++
 board/freescale/ls1012ardb/Kconfig                 |  15 ++
 board/freescale/ls1012ardb/MAINTAINERS             |   6 +
 board/freescale/ls1012ardb/Makefile                |   7 +
 board/freescale/ls1012ardb/README                  |  54 +++++
 board/freescale/ls1012ardb/ls1012ardb.c            | 224 ++++++++++++++++++++
 board/freescale/ls1043aqds/README                  |  37 +---
 board/freescale/ls1043ardb/README                  |  37 +---
 board/freescale/ls2080aqds/README                  |  45 +---
 board/freescale/ls2080ardb/README                  |  45 +---
 configs/ls1012afrdm_qspi_defconfig                 |  29 +++
 configs/ls1012aqds_qspi_defconfig                  |  32 +++
 configs/ls1012ardb_qspi_defconfig                  |  32 +++
 drivers/mtd/spi/sf_params.c                        |   1 +
 drivers/mtd/spi/spi_flash.c                        |   5 +-
 include/configs/ls1012a_common.h                   | 145 +++++++++++++
 include/configs/ls1012afrdm.h                      |  44 ++++
 include/configs/ls1012aqds.h                       | 191 +++++++++++++++++
 include/configs/ls1012ardb.h                       | 107 ++++++++++
 include/fsl_mmdc.h                                 | 160 ++++++++++++++
 include/linux/usb/xhci-fsl.h                       |   6 +-
 55 files changed, 2384 insertions(+), 163 deletions(-)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch2 (100%)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch3 (100%)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
 create mode 100644 board/freescale/ls1012afrdm/Kconfig
 create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
 create mode 100644 board/freescale/ls1012afrdm/Makefile
 create mode 100644 board/freescale/ls1012afrdm/README
 create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
 create mode 100644 board/freescale/ls1012aqds/Kconfig
 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1012aqds/Makefile
 create mode 100644 board/freescale/ls1012aqds/README
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 create mode 100644 board/freescale/ls1012ardb/Kconfig
 create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1012ardb/Makefile
 create mode 100644 board/freescale/ls1012ardb/README
 create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
 create mode 100644 configs/ls1012afrdm_qspi_defconfig
 create mode 100644 configs/ls1012aqds_qspi_defconfig
 create mode 100644 configs/ls1012ardb_qspi_defconfig
 create mode 100644 include/configs/ls1012a_common.h
 create mode 100644 include/configs/ls1012afrdm.h
 create mode 100644 include/configs/ls1012aqds.h
 create mode 100644 include/configs/ls1012ardb.h
 create mode 100644 include/fsl_mmdc.h

1.9.1

It is not mandatory for Layerscape SoCs to have SMMU. SoCs like LS1012A are layerscape SoC without SMMU IP.

So put SMMU configuration code under SMMU_BASE.

---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
Changes for v5: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
 1 file changed, 2 insertions(+)

index 04831ca..d743ffe 100644
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
 	bl	ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
 	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
 	str	w0, [x1, #0x10]
+#endif
 
 	/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)

1.9.1

This set has been applied to fsl-qoriq master branch. Awaiting upstream. Thanks.

York

Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.

So Avoid LS1043A specific defines in arch/arm

---
Changes for v2: Sending as it is Changes for v3: Sending as it is Changes for v4: Sending as it is Changes for v5: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/soc.c               | 2 +-
 arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

index 0fb5c7f..0ae61d6 100644
@@ -224,7 +224,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {

index f71c2c1..c4fb7c9 100644
@@ -55,7 +55,7 @@ enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,

1.9.1

Serial number, vendor id and page size are added for QSPI flash common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011.

---
Changes for v2: Sending as it is
Changes for v3: Sending as it is
Changes for v4: Sending as it is
Changes for v5: Sending as it is

 drivers/mtd/spi/sf_params.c | 1 +
 drivers/mtd/spi/spi_flash.c | 5 +++--
 2 files changed, 4 insertions(+), 2 deletions(-)

index 4f37e33..c577d9e 100644
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,		     WR_QPP},
 	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,                   WR_QPP},
 	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,		     WR_QPP},
 	{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,		     WR_QPP},

index fa0e799..64d4e0f 100644
@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * sector that is not overlaid by the parameter sectors.
 	 * The uniform sector erase command has no effect on parameter sectors.
 	 */
-	if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+	if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+	    (ext_jedec & 0xff00) == 0x4d00) {
 		int ret;
 		u8 id[6];
 

@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * have 256b pages.
 	 */
 	if (ext_jedec == 0x4d00) {
-		if ((jedec == 0x0215) || (jedec == 0x216))
+		if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
 			flash->page_size = 256;
 		else
 			flash->page_size = 512;

1.9.1

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function ?get_sys_info?:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ?rcw_tmp? [-Wunused-variable]
u32 rcw_tmp;

---
Changes for v2: Sending as it is Changes for v3: Sending as it is Changes for v4: Sending as it is Changes for v5: Sending as it is

 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

index 453a93d..4fc3186 100644
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+	defined(CONFIG_SYS_DPAA_FMAN)
+
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);

1.9.1

SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc

Also move README.lsch2 and README.lsch3 in same folder.

---
Changes for v3: New patch in the list
Changes for v4: Sending as it is
Changes for v5: Sending as it is

 .../armv8/fsl-layerscape/{ => doc}/README.lsch2    |  0
 .../armv8/fsl-layerscape/{ => doc}/README.lsch3    |  0
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   | 86 ++++++++++++++++++++++
 board/freescale/ls1043aqds/README                  | 37 +---------
 board/freescale/ls1043ardb/README                  | 37 +---------
 board/freescale/ls2080aqds/README                  | 45 +----------
 board/freescale/ls2080ardb/README                  | 45 +----------
 7 files changed, 96 insertions(+), 154 deletions(-)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch2 (100%)
 rename arch/arm/cpu/armv8/fsl-layerscape/{ => doc}/README.lsch3 (100%)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2

similarity index 100%
rename from arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
rename to arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

index a6fd7a3..913537d 100644
@@ -8,41 +8,8 @@ debugging environment.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------

index 0556e73..709ddbb 100644
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043ARDB board Overview
  -----------------------

1.9.1

The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance.

This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4

---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments
- Placed SoC overview in README.soc
Changes for v4
- Incorporated Edward L Swarthout's comments
- Updated DDR speed
- Added defines for MMDC controller
Changes for v5: Updated constant with macro for DDR

 arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
 arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc   |  43 ++++++
 .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |  11 ++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   2 +
 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c |  74 ++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   2 +
 arch/arm/include/asm/arch-fsl-layerscape/config.h  |  29 ++++
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   1 +
 .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   4 +
 .../include/asm/arch-fsl-layerscape/ns_access.h    |  10 ++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   1 +
 include/fsl_mmdc.h                                 | 160 +++++++++++++++++++++
 include/linux/usb/xhci-fsl.h                       |   6 +-
 14 files changed, 347 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
 create mode 100644 include/fsl_mmdc.h

index 5f86ef9..eb2cbc3 100644
@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif

index 4fc3186..3a77b21 100644
@@ -59,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;

@@ -83,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+	sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN

index d743ffe..5af6b73 100644
@@ -183,6 +183,7 @@ ENTRY(lowlevel_init)
 	ret
 ENDPROC(lowlevel_init)
 
+#ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7

@@ -260,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_cache)
+#endif
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */

index 0ae61d6..dd633f3 100644
@@ -12,8 +12,10 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
+#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif

index fbdaa52..44fe0c0 100644
@@ -14,8 +14,11 @@
 #else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
 #endif
+
+#ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#endif
 
 /*
  * Reserve secure memory

@@ -200,6 +203,32 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS                         1
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
+
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES		4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif

index 702b9fa..1cebe2f 100644
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF

index c4fb7c9..487cba8 100644
@@ -134,6 +134,7 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	TX_CLK,
 	SERDES_PRCTL_COUNT
 };
 

index 57b99d4..e98e055 100644
@@ -60,7 +60,11 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE				0xC0000
+#else
 #define PCIE_LUT_BASE				0x10000
+#endif
 #define PCIE_LUT_LCTRL0				0x7F8
 #define PCIE_LUT_DBG				0x7FC
 

index a3ccdb0..db76066 100644
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
 	CSU_CSLX_IIC4 = 77,
 	CSU_CSLX_WDT4,
 	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
 	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
 	CSU_CSLX_FTM2 = 86,
 	CSU_CSLX_FTM1,
 	CSU_CSLX_FTM4,

@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_IIC4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
 	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
 	 {CSU_CSLX_FTM2, CSU_ALL_RW},
 	 {CSU_CSLX_FTM1, CSU_ALL_RW},
 	 {CSU_CSLX_FTM4, CSU_ALL_RW},

index 831d817..02ecc62 100644
@@ -41,6 +41,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
+#define SVR_LS1012		0x870400
 #define SVR_LS1043		0x879200
 #define SVR_LS1023		0x879208
 #define SVR_LS2045		0x870120

index c5e42e6..253eddf 100644
@@ -59,10 +59,14 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \

1.9.1

From: Abhimanyu Saini <[email protected]>

Check if qixis supports memory-mapped read/write before compiling IFC based qixis read/write functions.

---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is
Chages for v5: Sending as it is

 board/freescale/common/qixis.c | 2 ++
 1 file changed, 2 insertions(+)

index 113295f..2e35d41 100644
@@ -27,6 +27,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
 	void *p = (void *)QIXIS_BASE;

@@ -40,6 +41,7 @@ void qixis_write(unsigned int reg, u8 value)
 
 	out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {

1.9.1

From: Abhimanyu Saini <[email protected]>

Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP configuration register instead of hardcoding it in set_lbmap() function.

---
Chages for v2: New patch in this patch-set
Chages for v3: Sending as it is
Chages for v4: Sending as it is
Chages for v5: Sending as it is

 board/freescale/common/qixis.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

index 2e35d41..0db0ed6 100644
@@ -14,6 +14,13 @@
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {

@@ -144,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
 	u8 reg;
 
-	reg = QIXIS_READ(brdcfg[0]);
+	reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
 	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-	QIXIS_WRITE(brdcfg[0], reg);
+	QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)

1.9.1

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance development platform, with a complete debugging environment. The LS1012AQDS board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

---
Changes for v2:
- Added support of qixis over i2c
- print fpga, board info using qixis
Changes for v3: Incorporated York's comments Changes for v4: Incorporated Alex and York's comments
- Removed ddr magic number
- updated license
- move PCie, SATA, SDHC define from common to qds.h
- use arch_fixup_fdt
Changes for v5: Use macro for DDR init

 arch/arm/Kconfig                              |  10 ++
 arch/arm/dts/Makefile                         |   3 +-
 arch/arm/dts/fsl-ls1012a-qds.dts              |  14 ++
 arch/arm/dts/fsl-ls1012a-qds.dtsi             | 123 ++++++++++++++
 arch/arm/dts/fsl-ls1012a.dtsi                 | 119 +++++++++++++
 board/freescale/ls1012aqds/Kconfig            |  15 ++
 board/freescale/ls1012aqds/MAINTAINERS        |   6 +
 board/freescale/ls1012aqds/Makefile           |   7 +
 board/freescale/ls1012aqds/README             |  59 +++++++
 board/freescale/ls1012aqds/ls1012aqds.c       | 234 ++++++++++++++++++++++++++
 board/freescale/ls1012aqds/ls1012aqds_qixis.h |  35 ++++
 configs/ls1012aqds_qspi_defconfig             |  32 ++++
 include/configs/ls1012a_common.h              | 145 ++++++++++++++++
 include/configs/ls1012aqds.h                  | 191 +++++++++++++++++++++
 14 files changed, 992 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi
 create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi
 create mode 100644 board/freescale/ls1012aqds/Kconfig
 create mode 100644 board/freescale/ls1012aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1012aqds/Makefile
 create mode 100644 board/freescale/ls1012aqds/README
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c
 create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h
 create mode 100644 configs/ls1012aqds_qspi_defconfig
 create mode 100644 include/configs/ls1012a_common.h
 create mode 100644 include/configs/ls1012aqds.h

index 7a77b6a..30fc32a 100644
@@ -696,6 +696,15 @@ config TARGET_HIKEY
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+	bool "Support ls1012aqds"
+	select ARM64
+	help
+	  Support for Freescale LS1012AQDS platform.
+	  The LS1012A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7

@@ -852,6 +861,7 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"

index 92c7545..47ec7a2 100644
@@ -120,7 +120,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
-	fsl-ls1043a-rdb.dtb
+	fsl-ls1043a-rdb.dtb \
+	fsl-ls1012a-qds.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 

new file mode 100644
index 0000000..76db36c
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};

new file mode 100644
index 0000000..1257ec8
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+	default "ls1012aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012aqds"
+
+endif

new file mode 100644
index 0000000..27c4aff
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_qspi_defconfig

new file mode 100644
index 0000000..0b813f9
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o

new file mode 100644
index 0000000..584f604
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

new file mode 100644
index 0000000..2bc178c
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

1.9.1

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance development platform, with a complete debugging environment. The LS1012ARDB board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

---
Changes for v2: Sending as it is
Changes for v3: Incorporated York's comments Changes for v4: Incorporated Alex and York's comments
- removed ddr init magic numbers
- updated file license
- define pcie, sata, sdhc define in rdb.h
- use arch_fixup_fdt
Changes for v5: Use macro for DDR init

 arch/arm/Kconfig                        |  10 ++
 arch/arm/dts/Makefile                   |   3 +-
 arch/arm/dts/fsl-ls1012a-rdb.dts        |  16 +++
 arch/arm/dts/fsl-ls1012a-rdb.dtsi       |  39 ++++++
 board/freescale/ls1012ardb/Kconfig      |  15 +++
 board/freescale/ls1012ardb/MAINTAINERS  |   6 +
 board/freescale/ls1012ardb/Makefile     |   7 +
 board/freescale/ls1012ardb/README       |  54 ++++++++
 board/freescale/ls1012ardb/ls1012ardb.c | 224 ++++++++++++++++++++++++++++++++
 configs/ls1012ardb_qspi_defconfig       |  32 +++++
 include/configs/ls1012ardb.h            | 107 +++++++++++++++
 11 files changed, 512 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi
 create mode 100644 board/freescale/ls1012ardb/Kconfig
 create mode 100644 board/freescale/ls1012ardb/MAINTAINERS
 create mode 100644 board/freescale/ls1012ardb/Makefile
 create mode 100644 board/freescale/ls1012ardb/README
 create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c
 create mode 100644 configs/ls1012ardb_qspi_defconfig
 create mode 100644 include/configs/ls1012ardb.h

index 30fc32a..9be8c2b 100644
@@ -705,6 +705,15 @@ config TARGET_LS1012AQDS
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1012ARDB
+	bool "Support ls1012ardb"
+	select ARM64
+	help
+	  Support for Freescale LS1012ARDB platform.
+	  The LS1012A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7

@@ -862,6 +871,7 @@ source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"

index 47ec7a2..f021699 100644
@@ -121,7 +121,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
-	fsl-ls1012a-qds.dtb
+	fsl-ls1012a-qds.dtb \
+	fsl-ls1012a-rdb.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 

new file mode 100644
index 0000000..f683812
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};

new file mode 100644
index 0000000..bf407ae
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A RDB Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};

new file mode 100644
index 0000000..3f67c28
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+	default "ls1012ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012ardb"
+
+endif

new file mode 100644
index 0000000..79a2a7d
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1012ardb/
+F:	include/configs/ls1012ardb.h
+F:	configs/ls1012ardb_qspi_defconfig

new file mode 100644
index 0000000..05fa9d9
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o

new file mode 100644
index 0000000..456eebd
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

1.9.1

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development platform, with a complete debugging environment. The LS1012AFRDM board supports the QorIQ LS1012A processor and is optimized to support the high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.

---
Changes for v4: New patch in this patch-set
Changes for v5: Use macro for DDR init

 arch/arm/Kconfig                          |  10 ++
 arch/arm/dts/Makefile                     |   3 +-
 arch/arm/dts/fsl-ls1012a-frdm.dts         |  16 +++
 arch/arm/dts/fsl-ls1012a-frdm.dtsi        |  37 ++++++
 board/freescale/ls1012afrdm/Kconfig       |  15 +++
 board/freescale/ls1012afrdm/MAINTAINERS   |   6 +
 board/freescale/ls1012afrdm/Makefile      |   7 ++
 board/freescale/ls1012afrdm/README        |  58 +++++++++
 board/freescale/ls1012afrdm/ls1012afrdm.c | 192 ++++++++++++++++++++++++++++++
 configs/ls1012afrdm_qspi_defconfig        |  29 +++++
 include/configs/ls1012afrdm.h             |  44 +++++++
 11 files changed, 416 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dts
 create mode 100644 arch/arm/dts/fsl-ls1012a-frdm.dtsi
 create mode 100644 board/freescale/ls1012afrdm/Kconfig
 create mode 100644 board/freescale/ls1012afrdm/MAINTAINERS
 create mode 100644 board/freescale/ls1012afrdm/Makefile
 create mode 100644 board/freescale/ls1012afrdm/README
 create mode 100644 board/freescale/ls1012afrdm/ls1012afrdm.c
 create mode 100644 configs/ls1012afrdm_qspi_defconfig
 create mode 100644 include/configs/ls1012afrdm.h

index 9be8c2b..71169b2 100644
@@ -714,6 +714,15 @@ config TARGET_LS1012ARDB
 	  development platform that supports the QorIQ LS1012A
 	  Layerscape Architecture processor.
 
+config TARGET_LS1012AFRDM
+	bool "Support ls1012afrdm"
+	select ARM64
+	help
+	  Support for Freescale LS1012AFRDM platform.
+	  The LS1012A Freedom  board (FRDM) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7

@@ -872,6 +881,7 @@ source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"

index f021699..e8ad6c6 100644
@@ -122,7 +122,8 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
 	fsl-ls1043a-rdb.dtb \
 	fsl-ls1012a-qds.dtb \
-	fsl-ls1012a-rdb.dtb
+	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 

new file mode 100644
index 0000000..983e599
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};

new file mode 100644
index 0000000..25dcdd2
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A FREEDOM Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};

new file mode 100644
index 0000000..a34521c
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif

new file mode 100644
index 0000000..842f86f
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <[email protected]>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig

new file mode 100644
index 0000000..dbfa2ce
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o

new file mode 100644
index 0000000..349758b
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y

1.9.1