board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot

PATCH New Shengzhou Liu 2 participants 2 messages May 31, 2016 – Jun 4, 2016

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Shengzhou Liu

author

2016-05-31 07:39 UTC #0 lore raw

PATCH 1/1 board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot

We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence.

Signed-off-by Shengzhou Liu <[email protected]>

---
 board/freescale/b4860qds/ddr.c | 8 +++-----
 board/freescale/t102xqds/ddr.c | 5 ++---
 board/freescale/t102xrdb/ddr.c | 4 ++--
 board/freescale/t104xrdb/ddr.c | 7 ++-----
 board/freescale/t208xqds/ddr.c | 5 ++---
 board/freescale/t208xrdb/ddr.c | 6 +++---
 board/freescale/t4qds/ddr.c    | 7 +++----
 board/freescale/t4rdb/ddr.c    | 5 ++---
 8 files changed, 19 insertions(+), 28 deletions(-)

board/freescale/b4860qds/ddr.c +3 -5

index eb10a6f..31b186e 100644
@@ -179,15 +179,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }

board/freescale/t102xqds/ddr.c +2 -3

index 2d4d10f..fa1394d 100644
@@ -172,14 +172,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();

board/freescale/t102xrdb/ddr.c +2 -2

index adf9fd5..b13692b 100644
@@ -234,12 +234,12 @@ phys_size_t initdram(int board_type)
 	puts("Initializing....using SPD\n");
 #endif
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();

board/freescale/t104xrdb/ddr.c +2 -5

index cf79d2d..22d6a5f 100644
@@ -124,15 +124,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();

board/freescale/t208xqds/ddr.c +2 -3

index f1aff54..f96470f 100644
@@ -108,13 +108,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }

board/freescale/t208xrdb/ddr.c +3 -3

index 053f128..f6c8ca3 100644
@@ -101,12 +101,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }

board/freescale/t4qds/ddr.c +3 -4

index 62d58c5..d533924 100644
@@ -117,13 +117,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }

board/freescale/t4rdb/ddr.c +2 -3

index 27b37b5..230f031 100644
@@ -110,13 +110,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }

Signature · 1 line

2.1.0.27.g96db324

York Sun

2016-06-04 15:57 UTC #1 lore raw

PATCH 1/1 board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot

Quoted 4 lines · Shengzhou Liu

We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by Shengzhou Liu <[email protected]>

Quoted 11 lines

---
 board/freescale/b4860qds/ddr.c | 8 +++-----
 board/freescale/t102xqds/ddr.c | 5 ++---
 board/freescale/t102xrdb/ddr.c | 4 ++--
 board/freescale/t104xrdb/ddr.c | 7 ++-----
 board/freescale/t208xqds/ddr.c | 5 ++---
 board/freescale/t208xrdb/ddr.c | 6 +++---
 board/freescale/t4qds/ddr.c    | 7 +++----
 board/freescale/t4rdb/ddr.c    | 5 ++---
 8 files changed, 19 insertions(+), 28 deletions(-)

Applied to u-boot-mpc85xx master. Awaiting upstream. Thanks.

York