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dm: gpio: Add driver for MPC85xx GPIO controller

PATCH New Mario Six 3 participants 8 messages May 25, 2016 – Jun 4, 2016

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Mario Six

author
#0 lore raw

v5 cover dm: gpio: Add driver for MPC85xx GPIO controller

The functions for accessing GPIOs on MPC85xx are hardcoded in arch/powerpc/include/asm/mpc85xx_gpio.h This leads to problems if another GPIO controller supporting the driver model is to be used simultaneously.

Therefore, this patch moves the "static" functions into a DM-compatible driver, and also introduces a set of functions into the GPIO uclass that expose the controller's capability to switch individual GPIOs into open-drain-mode.

v3/v4 also implement shadowing of the GPDAT register to work around a known issue in some MPC85xx GPIO controllers (as pointed out by Joakim Tjernlund).

Furthermore, v4 adds tests for the open drain setting feature and extends the sandbox GPIO driver accordingly.

Mario Six (4):
dm: gpio: Add driver for MPC85XX GPIO controller
dm: gpio: Add methods for open drain setting
dm: gpio: Implement open drain for MPC85XX GPIO
dm: test: Add GPIO open drain tests

 arch/powerpc/include/asm/arch-mpc85xx/gpio.h |   2 +
 arch/powerpc/include/asm/immap_85xx.h        |   2 +
 arch/sandbox/include/asm/gpio.h              |  20 +++
 drivers/gpio/Kconfig                         |  26 +++
 drivers/gpio/Makefile                        |   1 +
 drivers/gpio/gpio-uclass.c                   |  32 ++++
 drivers/gpio/mpc85xx_gpio.c                  | 228 +++++++++++++++++++++++++++
 drivers/gpio/sandbox.c                       |  35 ++++
 include/asm-generic/gpio.h                   |  34 ++++
 test/dm/gpio.c                               |   7 +
 10 files changed, 387 insertions(+)
 create mode 100644 drivers/gpio/mpc85xx_gpio.c

--
2.7.0.GIT

author
#1 lore raw

PATCH v5 1/4 dm: gpio: Add driver for MPC85XX GPIO controller

From: "[email protected]" <[email protected]>

This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller at fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well.

---

v5:
- Added 'Reviewed-by: Simon Glass <[email protected]>'

v4:
None

v3:
- Added shadow for the GPDAT register, as suggested by Joakim Tjernlund
- Switched to u32 for bit masks
- Added some comments

v2:
- Added missing commit message
- Improved the Kconfig description
- Fixed and documented the mpc85xx_gpio_data members
- Introduced GPIO_MASK macro to simplify the code
- Fixed white space issues in function headers
- Removed unnecessary empty line
- Use fdtdec_get_addr_size_auto_noparent to read the register base data

---
 arch/powerpc/include/asm/arch-mpc85xx/gpio.h |   2 +
 arch/powerpc/include/asm/immap_85xx.h        |   2 +
 drivers/gpio/Kconfig                         |  26 ++++
 drivers/gpio/Makefile                        |   1 +
 drivers/gpio/mpc85xx_gpio.c                  | 187 +++++++++++++++++++++++++++
 5 files changed, 218 insertions(+)
 create mode 100644 drivers/gpio/mpc85xx_gpio.c
arch/powerpc/include/asm/arch-mpc85xx/gpio.h +2 -0
index da7352a..41b6677 100644
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
+#ifndef CONFIG_MPC85XX_GPIO
 #include <asm/mpc85xx_gpio.h>
+#endif
 
 #endif
arch/powerpc/include/asm/immap_85xx.h +2 -0
index 07d2adf..c045a24 100644
@@ -265,6 +265,7 @@ typedef struct ccsr_pcix {
 #define PIWAR_WRITE_SNOOP	0x00005000
 #define PIWAR_MEM_2G		0x0000001e
 
+#ifndef CONFIG_MPC85XX_GPIO
 typedef struct ccsr_gpio {
 	u32	gpdir;
 	u32	gpodr;
@@ -273,6 +274,7 @@ typedef struct ccsr_gpio {
 	u32	gpimr;
 	u32	gpicr;
 } ccsr_gpio_t;
+#endif
 
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
drivers/gpio/Kconfig +26 -0
index 93a7e8c..b674a47 100644
@@ -173,4 +173,30 @@ config DM_PCA953X
 
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
+
+config MPC85XX_GPIO
+	bool "Freescale MPC85XX GPIO driver"
+	depends on DM_GPIO
+	help
+	  This driver supports the built-in GPIO controller of MPC85XX CPUs.
+	  Each GPIO bank is identified by its own entry in the device tree,
+	  i.e.
+
+	  gpio-controller at fc00 {
+		#gpio-cells = <2>;
+		compatible = "fsl,pq3-gpio";
+		reg = <0xfc00 0x100>
+	  }
+
+	  By default, each bank is assumed to have 32 GPIOs, but the ngpios
+	  setting is honored, so the number of GPIOs for each bank is
+	  configurable to match the actual GPIO count of the SoC (e.g. the
+	  32/32/23 banks of the P1022 SoC).
+
+	  The standard functions of input/output mode, and output value setting
+	  are supported; the open-drain capability of the controller is not
+	  supported yet.
+
+	  The driver has been tested on MPC85XX, but it is likely that other
+	  PowerQUICC III devices will work as well.
 endmenu
drivers/gpio/Makefile +1 -0
index ddec1ef..21b2cc2 100644
@@ -35,6 +35,7 @@ obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
+obj-$(CONFIG_MPC85XX_GPIO)	+= mpc85xx_gpio.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
drivers/gpio/mpc85xx_gpio.c new file +187 -0

187 lines not on this page · raw message

--
2.7.0.GIT

#2 lore raw

PATCH v5 1/4 dm: gpio: Add driver for MPC85XX GPIO controller

Quoted 24 lines · Mario Six

From: "mario.six at gdsys.cc" <[email protected]>

This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller at fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well.

Quoted 6 lines

---

v5:
- Added 'Reviewed-by: Simon Glass <[email protected]>'

This set has been applied to u-boot-mpc85xx master. Awaiting upstream. Thanks.

York

author
#3 lore raw

PATCH v5 2/4 dm: gpio: Add methods for open drain setting

In reply to Mario Six

From: "[email protected]" <[email protected]>

Certain GPIO devices have the capability to switch their GPIOs into open-drain mode, that is, instead of actively driving the output (Push-pull output), the pin is connected to the collector (for a NPN transistor) or the drain (for a MOSFET) of a transistor, respectively. The pin then either forms an open circuit or a connection to ground, depending on the state of the transistor.

This patch adds functions to the GPIO uclass to switch GPIOs to open-drain mode on devices that support it.

---

v5:
- Added 'Reviewed-by: Simon Glass <[email protected]> '

v4:
None

v3:
None

v2:
- Added missing commit message
- Fixed error return value of dm_gpio_get_open_drain
- Fixed return value passing in dm_gpio_set_open_drain and added comment
- Added description of open-drain mode

---
 drivers/gpio/gpio-uclass.c | 32 ++++++++++++++++++++++++++++++++
 include/asm-generic/gpio.h | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)
drivers/gpio/gpio-uclass.c +32 -0
index 732b6c2..4559739 100644
@@ -367,6 +367,38 @@ int dm_gpio_set_value(const struct gpio_desc *desc, int value)
 	return 0;
 }
 
+int dm_gpio_get_open_drain(struct gpio_desc *desc)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "get_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		return ops->get_open_drain(desc->dev, desc->offset);
+	else
+		return -ENOSYS;
+}
+
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "set_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		ret = ops->set_open_drain(desc->dev, desc->offset, value);
+	else
+		return 0; /* feature not supported -> ignore setting */
+
+	return ret;
+}
+
 int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
 {
 	struct udevice *dev = desc->dev;
include/asm-generic/gpio.h +34 -0
index 2500c10..4aa0004 100644
@@ -251,6 +251,8 @@ struct dm_gpio_ops {
 				int value);
 	int (*get_value)(struct udevice *dev, unsigned offset);
 	int (*set_value)(struct udevice *dev, unsigned offset, int value);
+	int (*get_open_drain)(struct udevice *dev, unsigned offset);
+	int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
 	/**
 	 * get_function() Get the GPIO function
 	 *
@@ -550,6 +552,38 @@ int dm_gpio_get_value(const struct gpio_desc *desc);
 int dm_gpio_set_value(const struct gpio_desc *desc, int value);
 
 /**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ *	   -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
  * dm_gpio_set_dir() - Set the direction for a GPIO
  *
  * This sets up the direction according tot the provided flags. It will do

--
2.7.0.GIT

author
#4 lore raw

PATCH v5 3/4 dm: gpio: Implement open drain for MPC85XX GPIO

In reply to Mario Six

From: "[email protected]" <[email protected]>

This patch implements the open-drain setting feature for the MPC85XX GPIO controller.

---

v5:
None

v4:
- Added forgotten mpc85xx_gpio_{get,set}_open_drain functions

v3:
- Added comments

v2:
- Added missing commit message
- Fixed white space issues in function headers

---
 drivers/gpio/Kconfig        |  6 +++---
 drivers/gpio/mpc85xx_gpio.c | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)
drivers/gpio/Kconfig +3 -3
index b674a47..8595e2e 100644
@@ -193,9 +193,9 @@ config MPC85XX_GPIO
 	  configurable to match the actual GPIO count of the SoC (e.g. the
 	  32/32/23 banks of the P1022 SoC).
 
-	  The standard functions of input/output mode, and output value setting
-	  are supported; the open-drain capability of the controller is not
-	  supported yet.
+	  Aside from the standard functions of input/output mode, and output
+	  value setting, the open-drain feature, which can configure individual
+	  GPIOs to work as open-drain outputs, is supported.
 
 	  The driver has been tested on MPC85XX, but it is likely that other
 	  PowerQUICC III devices will work as well.
drivers/gpio/mpc85xx_gpio.c +41 -0

59 lines not on this page · raw message

--
2.7.0.GIT

#5 lore raw

PATCH v5 3/4 dm: gpio: Implement open drain for MPC85XX GPIO

Quoted 17 lines · Mario Six

From: "mario.six at gdsys.cc" <[email protected]>

This patch implements the open-drain setting feature for the MPC85XX GPIO controller.

---

v5:
None

v4:
- Added forgotten mpc85xx_gpio_{get,set}_open_drain functions

v3:
- Added comments

Quoted 8 lines

v2:
- Added missing commit message
- Fixed white space issues in function headers

---
 drivers/gpio/Kconfig        |  6 +++---
 drivers/gpio/mpc85xx_gpio.c | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 3 deletions(-)
author
#6 lore raw

PATCH v5 4/4 dm: test: Add GPIO open drain tests

In reply to Mario Six

Add some tests for the new open drain setting feature of the GPIO uclass, and extend the capabilities of the sandbox GPIO driver accordingly.

---

v5:
- Use 'sandbox_gpio_*' functions in tests
- Add 'sandbox_gpio_{get,set}_open_drain' prototypes to arch/sandbox/include/asm/gpio.h

v4:
Patch added

---
 arch/sandbox/include/asm/gpio.h | 20 ++++++++++++++++++++
 drivers/gpio/sandbox.c          | 35 +++++++++++++++++++++++++++++++++++
 test/dm/gpio.c                  |  7 +++++++
 3 files changed, 62 insertions(+)
arch/sandbox/include/asm/gpio.h +20 -0
index 8317db1..427af2c 100644
@@ -41,6 +41,26 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
 int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
 
 /**
+ * Set or reset the simulated open drain mode of a GPIO (used only in sandbox
+ * test code)
+ *
+ * @param gp	GPIO number
+ * @param value	value to set (0 for enabled open drain mode, non-zero for
+ * 		disabled)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value);
+
+/**
+ * Return the state of the simulated open drain mode of a GPIO (used only in
+ * sandbox test code)
+ *
+ * @param gp	GPIO number
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
+
+/**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
  *
  * @param gp	GPIO number
drivers/gpio/sandbox.c +35 -0
index a9b1efc..f6435a0 100644
@@ -15,6 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Flags for each GPIO */
 #define GPIOF_OUTPUT	(1 << 0)	/* Currently set as an output */
 #define GPIOF_HIGH	(1 << 1)	/* Currently set high */
+#define GPIOF_ODR	(1 << 2)	/* Currently set to open drain mode */
 
 struct gpio_state {
 	const char *label;	/* label given by requester */
@@ -70,6 +71,16 @@ int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
 }
 
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	return get_gpio_flag(dev, offset, GPIOF_ODR);
+}
+
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	return set_gpio_flag(dev, offset, GPIOF_ODR, value);
+}
+
 int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
 {
 	return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
@@ -124,6 +135,28 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return sandbox_gpio_set_value(dev, offset, value);
 }
 
+/* read GPIO ODR value of port 'offset' */
+static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	debug("%s: offset:%u\n", __func__, offset);
+
+	return sandbox_gpio_get_open_drain(dev, offset);
+}
+
+/* write GPIO ODR value to port 'offset' */
+static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
+
+	if (!sandbox_gpio_get_direction(dev, offset)) {
+		printf("sandbox_gpio: error: set_open_drain on input gpio %u\n",
+		       offset);
+		return -1;
+	}
+
+	return sandbox_gpio_set_open_drain(dev, offset, value);
+}
+
 static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
@@ -154,6 +187,8 @@ static const struct dm_gpio_ops gpio_sandbox_ops = {
 	.direction_output	= sb_gpio_direction_output,
 	.get_value		= sb_gpio_get_value,
 	.set_value		= sb_gpio_set_value,
+	.get_open_drain		= sb_gpio_get_open_drain,
+	.set_open_drain		= sb_gpio_set_open_drain,
 	.get_function		= sb_gpio_get_function,
 	.xlate			= sb_gpio_xlate,
 };
test/dm/gpio.c +7 -0
index 727db18..b994523 100644
@@ -75,6 +75,13 @@ static int dm_test_gpio(struct unit_test_state *uts)
 	ut_assertok(ops->set_value(dev, offset, 1));
 	ut_asserteq(1, ops->get_value(dev, offset));
 
+	/* Make it an open drain output, and reset it */
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 1));
+	ut_asserteq(1, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 0));
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+
 	/* Make it an input */
 	ut_assertok(ops->direction_input(dev, offset));
 	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));

--
2.7.0.GIT

#7 lore raw

PATCH v5 4/4 dm: test: Add GPIO open drain tests

Quoted 13 lines · Mario Six

Add some tests for the new open drain setting feature of the GPIO uclass, and extend the capabilities of the sandbox GPIO driver accordingly.

---

v5:
- Use 'sandbox_gpio_*' functions in tests
- Add 'sandbox_gpio_{get,set}_open_drain' prototypes to arch/sandbox/include/asm/gpio.h

Quoted 8 lines

v4:
Patch added

---
 arch/sandbox/include/asm/gpio.h | 20 ++++++++++++++++++++
 drivers/gpio/sandbox.c          | 35 +++++++++++++++++++++++++++++++++++
 test/dm/gpio.c                  |  7 +++++++
 3 files changed, 62 insertions(+)