PCI: layerscape: Add 'dma-coherent' property
Subsystems (4)
PATCH 1/1 PCI: layerscape: Add 'dma-coherent' property
Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
--- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/pci/layerscape-pci.txt +4 -0
@@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example:
@@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
Signature · 1 line
2.1.0.27.g96db324
PATCH 1/1 arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +3 -0
@@ -479,6 +479,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -503,6 +504,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -527,6 +529,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <2>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
Signature · 1 line
2.1.0.27.g96db324
PATCH 1/1 arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
Quoted 5 lines · Liu Gang
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
Quoted 7 lines
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
Signed-off-by Liu Gang <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+)
Why not ls2080a as well?
What about non-PCI devices?
Pretty much everything on these chips should be coherent as long as it's properly configured.
-Scott
PATCH 1/1 arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
Quoted 11 lines
From: Scott Wood
Quoted 8 lines · Liu Gang
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
Quoted 6 lines
Quoted 4 lines
Signed-off-by Liu Gang <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+)Why not ls2080a as well?
[Liu Gang] ls2080 should also include this property, we can add it after verification.
Quoted 4 lines
What about non-PCI devices?
Pretty much everything on these chips should be coherent as long as it's properly configured.
[Liu Gang] you are right. For the layerscape platforms including CCI or CCN internal bus, theoretically, pretty much IP blocks (PCI/non-PCI) should be coherent. But this depends on the properly hardware and software configurations. (ls1012a PCI devices cannot implement the coherent duo to hardware issue)
So I think we'd better to add this property after each IP block's verification.
Thanks!
Liu Gang
Quoted 2 lines
-Scott
PATCH 1/1 PCI: layerscape: Add 'dma-coherent' property
In reply to Liu GangQuoted 6 lines · Liu Gang
Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
Note that depending on the exact details it may actually be *necessary* for correctness - if the properties of the system are such that cacheable writes from the root complex might allocate directly into some level of cache without going to RAM, then having the CPU think the device is non-coherent and thus invalidate the cache before reading back from the buffer will result in data loss. But yeah, the performance is the most visible aspect ;)
Robin.
Quoted 31 lines
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
Signed-off-by Liu Gang <[email protected]>--- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+)Documentation/devicetree/bindings/pci/layerscape-pci.txt +4
-0@@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example:@@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
Rob Herring
maintainerPATCH 1/1 PCI: layerscape: Add 'dma-coherent' property
In reply to Liu GangQuoted 7 lines · Liu Gang
Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
Quoted 7 lines
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
Signed-off-by Liu Gang <[email protected]>--- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+)
Quoted 26 lines
Documentation/devicetree/bindings/pci/layerscape-pci.txt +4
-0@@ -24,6 +24,9 @@ Required properties: The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. This is used to get SCFG PEXN registers +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. Example:@@ -38,6 +41,7 @@ Example: #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + dma-coherent; num-lanes = <4>; bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */Signature · 1 line
2.1.0.27.g96db324
Shawn Guo
AppliedPATCH 1/1 PCI: layerscape: Add 'dma-coherent' property
In reply to Liu GangQuoted 11 lines · Liu Gang
Add 'dma-coherent' description for PCI nodes.
The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly.
The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance.
Signed-off-by Liu Gang <[email protected]>
Applied both, thanks.