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armv8/ls2080a: configure PMU's PCTBENR to enable WDT

PATCH Superseded Yunhui Cui 3 participants 3 messages Jun 7, 2016 – Jun 8, 2016 Arm (32-bit)

v4 of 5 Superseded Latest is v5 →

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Yunhui Cui

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#0 lore raw

PATCH v4 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

From: Yunhui Cui <[email protected]>

The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.

Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c                | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 16 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +15 -0
index d939900..1ac1067 100644
@@ -639,6 +639,10 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+	u32 pmu_val;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 

@@ -653,6 +657,17 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A
+/*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+pmu_val = in_le32(pctbenr);
+pmu_val |= 0xff;
+out_le32(pctbenr, pmu_val);
+#endif
+
 	/* Enable clock for timer
 	 * This is a global setting.
 	 */
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +1 -0
index 1d3b336..ba3b94d 100644
@@ -26,6 +26,7 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET	(CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
Signature · 1 line
2.1.0.27.g96db324
#1 lore raw

PATCH v4 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Quoted 33 lines · Yunhui Cui

From: Yunhui Cui <[email protected]>

The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.

Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c                | 15 +++++++++++++++
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 16 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +5 -0
index d939900..1ac1067 100644
@@ -639,6 +639,10 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
+#ifdef CONFIG_LS2080A
+	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+	u32 pmu_val;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 

@@ -653,6 +657,17 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A

arch/arm/cpu/armv8/fsl-layerscape/cpu.c int timer_init(void) · line 670

Quoted 10 lines
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +10 -0
+/*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+pmu_val = in_le32(pctbenr);
+pmu_val |= 0xff;
+out_le32(pctbenr, pmu_val);
+#endif
+

You could use setbits_le32() instead of three lines. Also inappropriate indentation.

York

#2 lore raw

PATCH v4 1/1 armv8/ls2080a: configure PMU's PCTBENR to enable WDT

Quoted 48 lines · York Sun
Quoted 10 lines · Yunhui Cui

From: Yunhui Cui <[email protected]>

The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance.

Signed-off-by Yunhui Cui <[email protected]>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c                | 15

+++++++++++++++

Quoted 22 lines
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  1 +
 2 files changed, 16 insertions(+)
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +5 -0
index d939900..1ac1067 100644
@@ -639,6 +639,10 @@ int timer_init(void)  #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;  #endif
+#ifdef CONFIG_LS2080A
+	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
+	u32 pmu_val;
+#endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 

@@ -653,6 +657,17 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
+#ifdef CONFIG_LS2080A

arch/arm/cpu/armv8/fsl-layerscape/cpu.c int timer_init(void) · line 670

Quoted 10 lines
arch/arm/cpu/armv8/fsl-layerscape/cpu.c +10 -0
+/*
+ * In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+pmu_val = in_le32(pctbenr);
+pmu_val |= 0xff;
+out_le32(pctbenr, pmu_val);
+#endif
+

You could use setbits_le32() instead of three lines. Also inappropriate indentation.

Quoted 1 line

York

OK,thanks for your review and suggestions, I will send v5 to update it.

Yunhui