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MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

PATCH New Paul Burton 2 participants 4 messages Jun 9, 2016 – Jun 10, 2016 MIPS

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Paul Burton

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#0 lore raw

PATCH 1/2 MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro") accidentally modified invalidate_dcache_range to operate on the L1 Icache instead of the Dcache. Fix the cache op used to operate on the Dcache.

Signed-off-by Paul Burton <[email protected]>
Fixes fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

---

 arch/mips/lib/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/lib/cache.c +1 -1
index 5f520c0..db81953 100644
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	if (start_addr == stop)
 		return;
 
-	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
 }
Signature · 1 line
2.8.3
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#1 lore raw

PATCH 2/2 MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex

For consistency with the other cache-related Kconfig entries & the values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int entry instead of a hex entry.

Signed-off-by Paul Burton <[email protected]>
Fixes 372286217f05 ("MIPS: Split I & D cache line size config")

---

 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/mips/Kconfig +1 -1
index 5c30ae9..21066f0 100644
@@ -253,7 +253,7 @@ config SYS_DCACHE_SIZE
 	  The total size of the L1 Dcache, if known at compile time.
 
 config SYS_DCACHE_LINE_SIZE
-	hex
+	int
 	default 0
 	help
 	  The size of L1 Dcache lines, if known at compile time.
Signature · 1 line
2.8.3
#2 lore raw

PATCH 2/2 MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex

Am 09.06.2016 um 14:09 schrieb Paul Burton:

Quoted 11 lines

For consistency with the other cache-related Kconfig entries & the values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int entry instead of a hex entry.

Signed-off-by Paul Burton <[email protected]>
Fixes 372286217f05 ("MIPS: Split I & D cache line size config")

---

 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

applied to u-boot-mips, thanks.

BTW: there is a similar patch from Purna [1] but I applied this one because it contains a "Fixes:" line.

[1] http://patchwork.ozlabs.org/patch/630747/

Signature · 9 lines
- Daniel

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#3 lore raw

PATCH 1/2 MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

In reply to Paul Burton

Am 09.06.2016 um 14:09 schrieb Paul Burton:

Quoted 8 lines

Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro") accidentally modified invalidate_dcache_range to operate on the L1 Icache instead of the Dcache. Fix the cache op used to operate on the Dcache.

Signed-off-by Paul Burton <[email protected]>
Fixes fb64cda57998 ("MIPS: Abstract cache op loops with a macro")

applied to u-boot-mips, thanks.

Signature · 9 lines
- Daniel

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