ARM: dts: Add operating-points-v2 tables for TI platforms
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.
These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Regards,
Dave
[1] https://www.mail-archive.com/linux-kernel at vger.kernel.org/msg1147940.html
Dave Gerlach (8):
ARM: dts: am335x: Update MPU regulator range for TI boards
ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq
driver
ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu
ARM: dts: am4372: Add operating-points-v2 table
ARM: dts: am437x-gp-evm: Hook dcdc2 as the cpu0-supply
ARM: dts: dra7: Add dt node for the syscon control module wkup
ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x
ARM: dts: dra7: Move to operating-points-v2 table
arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-boneblack.dts | 11 ++++ arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am33xx.dtsi | 88 ++++++++++++++++++++++++++----- arch/arm/boot/dts/am4372.dtsi | 39 ++++++++++++++ arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++ arch/arm/boot/dts/dra7.dtsi | 48 +++++++++++++++++ arch/arm/boot/dts/dra72x.dtsi | 16 ------ arch/arm/boot/dts/dra74x.dtsi | 25 +-------- 10 files changed, 181 insertions(+), 56 deletions(-)
Signature · 1 line
2.7.3
PATCH 1/8 ARM: dts: am335x: Update MPU regulator range for TI boards
Now that we are moving to OPPv2 bindings and able to add 1GHz OPP for MPU, let's update the max MPU voltage range to align with the maximum possible value allowed in the operating-points table, which is max target voltage of 132500 uV + 2%.
--- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/boot/dts/am335x-bone-common.dtsi +1 -1
@@ -318,7 +318,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <925000>; - regulator-max-microvolt = <1325000>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; };
arch/arm/boot/dts/am335x-evm.dts +1 -1
@@ -640,7 +640,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; };
arch/arm/boot/dts/am335x-evmsk.dts +1 -1
@@ -560,7 +560,7 @@ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; + regulator-max-microvolt = <1351500>; regulator-boot-on; regulator-always-on; };
Signature · 1 line
2.7.3
PATCH 2/8 ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver
In reply to Dave GerlachDrop the operating-points table present in am33xx.dtsi and add an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime. Also, drop the voltage-tolerance value and provide voltages for each OPP using the <target min max> format instead.
Information from AM335x Data Manual, SPRS717i, Revised December 2015, Table 5-7.
--- arch/arm/boot/dts/am33xx.dtsi | 88 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 75 insertions(+), 13 deletions(-)
arch/arm/boot/dts/am33xx.dtsi +75 -13
@@ -45,19 +45,9 @@ device_type = "cpu"; reg = <0>; - /* - * To consider voltage drop between PMIC and SoC, - * tolerance value is reduced to 2% from 4% and - * voltage value is increased as a precaution. - */ - operating-points = < - /* kHz uV */ - 720000 1285000 - 600000 1225000 - 500000 1125000 - 275000 1125000 - >; - voltage-tolerance = <2>; /* 2 percentage */ + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; + ti,syscon-rev = <&scm_conf 0x600>; clocks = <&dpll_mpu_ck>; clock-names = "cpu";
@@ -66,6 +56,78 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50 at 300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>; + opp-suspend; + }; + + opp100 at 275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0x00FF>; + opp-suspend; + }; + + opp100 at 300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0020>; + opp-suspend; + }; + + opp100 at 500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp100 at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0x06 0x0040>; + }; + + opp120 at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + opp120 at 720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0x06 0x0080>; + }; + + oppturbo at 720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x01 0xFFFF>; + }; + + oppturbo at 800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0x06 0x0100>; + }; + + oppnitro at 1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0x04 0x0200>; + }; + }; + pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>;
Signature · 1 line
2.7.3
PATCH 2/8 ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver
arch/arm/boot/dts/am33xx.dtsi line 70
Quoted 12 lines · Dave Gerlach
arch/arm/boot/dts/am33xx.dtsi +12
-0+ cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + /* + * The three following nodes are marked with opp-suspend + * because the can not be enabled simultaneously on a + * single SoC. + */ + opp50 at 300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0x06 0x0010>;
Is there any place in either of the patchsets you have sent, that details the usage of the above two values? I mean which defines, what is 0x6 and what is 0x1 ?
Signature · 1 line
viresh
PATCH 3/8 ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu
In reply to Dave GerlachAlthough all PG2.0 silicon may not support 1GHz OPP for the MPU, older Beaglebone Blacks may have PG2.0 silicon populated and these particular parts are guaranteed to support the OPP, so enable it for PG2.0 on am335x-boneblack only.
--- arch/arm/boot/dts/am335x-boneblack.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm/boot/dts/am335x-boneblack.dts +11 -0
@@ -33,6 +33,17 @@ status = "okay"; }; +&cpu0_opp_table { + /* + * All PG 2.0 silicon may not support 1GHz but some of the early + * BeagleBone Blacks have PG 2.0 silicon which is guaranteed + * to support 1GHz OPP so enable it for PG 2.0 on this board. + */ + oppnitro at 1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = <
Signature · 1 line
2.7.3
PATCH 4/8 ARM: dts: am4372: Add operating-points-v2 table
In reply to Dave GerlachAdd an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime.
Information from AM437x Data Manual, SPRS851B, Revised April 2015, Table 5-2.
--- arch/arm/boot/dts/am4372.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
arch/arm/boot/dts/am4372.dtsi +39 -0
@@ -44,10 +44,49 @@ clocks = <&dpll_mpu_ck>; clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>; + ti,syscon-rev = <&scm_conf 0x600>; + clock-latency = <300000>; /* From omap-cpufreq driver */ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp50 at 300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000 931000 969000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp100 at 600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000 1078000 1122000>; + opp-supported-hw = <0xFF 0x04>; + }; + + opp120 at 720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1200000 1176000 1224000>; + opp-supported-hw = <0xFF 0x08>; + }; + + oppturbo at 800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1260000 1234800 1285200>; + opp-supported-hw = <0xFF 0x10>; + }; + + oppnitro at 1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1325000 1298500 1351500>; + opp-supported-hw = <0xFF 0x20>; + }; + }; + gic: interrupt-controller at 48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller;
Signature · 1 line
2.7.3
PATCH 5/8 ARM: dts: am437x-gp-evm: Hook dcdc2 as the cpu0-supply
In reply to Dave GerlachHook dcdc2 as the cpu0-supply.
--- arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/boot/dts/am437x-gp-evm.dts +4 -0
@@ -975,3 +975,7 @@ clock-names = "ext-clk", "int-clk"; status = "okay"; }; + +&cpu { + cpu0-supply = <&dcdc2>; +};
Signature · 1 line
2.7.3
PATCH 6/8 ARM: dts: dra7: Add dt node for the syscon control module wkup
In reply to Dave GerlachCreate a system control module node for the control module portion that resides under l4_wkup.
--- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/dra7.dtsi +5 -0
@@ -233,6 +233,11 @@ prm_clockdomains: clockdomains { }; }; + + scm_wkup: scm_conf at c000 { + compatible = "syscon"; + reg = <0xc000 0x1000>; + }; }; axi at 0 {
Signature · 1 line
2.7.3
PATCH 7/8 ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x
In reply to Dave GerlachNearly all of the information in the cpus node, especially for cpu0, is the same between dra74x and dra72x so move the common information to the parent dra7.dtsi to avoid duplication of data.
--- arch/arm/boot/dts/dra7.dtsi | 27 +++++++++++++++++++++++++++ arch/arm/boot/dts/dra72x.dtsi | 16 ---------------- arch/arm/boot/dts/dra74x.dtsi | 24 ------------------------ 3 files changed, 27 insertions(+), 40 deletions(-)
arch/arm/boot/dts/dra7.dtsi +27 -0
@@ -73,6 +73,33 @@ interrupt-parent = <&gic>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; + + clocks = <&dpll_mpu_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + + /* cooling options */ + cooling-min-level = <0>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself.
arch/arm/boot/dts/dra72x.dtsi +0 -16
@@ -12,22 +12,6 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu at 0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; - }; - pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>;
arch/arm/boot/dts/dra74x.dtsi +0 -24
@@ -13,30 +13,6 @@ compatible = "ti,dra742", "ti,dra74", "ti,dra7"; cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu at 0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; - - clocks = <&dpll_mpu_ck>; - clock-names = "cpu"; - - clock-latency = <300000>; /* From omap-cpufreq driver */ - - /* cooling options */ - cooling-min-level = <0>; - cooling-max-level = <2>; - #cooling-cells = <2>; /* min followed by max */ - }; cpu at 1 { device_type = "cpu"; compatible = "arm,cortex-a15";
Signature · 1 line
2.7.3
PATCH 8/8 ARM: dts: dra7: Move to operating-points-v2 table
In reply to Dave GerlachAdd an operating-points-v2 table with all OPPs available for all silicon revisions along with necessary data for use by ti-opp driver to selectively enable the appropriate OPPs at runtime and handle voltage transitions
As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range.
Information from SPRS953, Revised December 2015.
--- arch/arm/boot/dts/dra7.dtsi | 26 +++++++++++++++++++++----- arch/arm/boot/dts/dra74x.dtsi | 1 + 2 files changed, 22 insertions(+), 5 deletions(-)
arch/arm/boot/dts/dra7.dtsi +21 -5
@@ -82,11 +82,9 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; + ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; + ti,syscon-rev = <&scm_wkup 0x204>; clocks = <&dpll_mpu_ck>; clock-names = "cpu";
@@ -100,6 +98,24 @@ }; }; + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp_nom at 1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od at 1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself.
arch/arm/boot/dts/dra74x.dtsi +1 -0
@@ -17,6 +17,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; }; };
Signature · 1 line
2.7.3
cover ARM: dts: Add operating-points-v2 tables for TI platforms
In reply to Dave GerlachQuoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Signature · 1 line
viresh
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Quoted 11 lines · Viresh Kumar
Quoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Acked-by Viresh Kumar <[email protected]>
Applying all the dts changes into omap-for-v4.8/dt thanks.
Tony
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Quoted 11 lines · Tony Lindgren
Quoted 10 lines · Viresh Kumar
Quoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Quoted 6 lines
Quoted 1 line
Acked-by Viresh Kumar <[email protected]>Applying all the dts changes into omap-for-v4.8/dt thanks.
Tony
Viresh, are we ready with the cpufreq series?
https://patchwork.kernel.org/patch/9122961/
https://patchwork.kernel.org/patch/9122921/
Also current series: https://patchwork.kernel.org/patch/9123071/
Seems to have comments pending.
Dave is on vacation for another week or so, doubt he can respond in time -> Should we wait on this series till we get the cpufreq support in?
Signature · 2 lines
Regards, Nishanth Menon
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Quoted 20 lines · Nishanth Menon
Quoted 11 lines · Tony Lindgren
Quoted 10 lines · Viresh Kumar
Quoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Quoted 6 lines
Quoted 1 line
Acked-by Viresh Kumar <[email protected]>Applying all the dts changes into omap-for-v4.8/dt thanks.
Tony
Viresh, are we ready with the cpufreq series?
Quoted 8 lines
https://patchwork.kernel.org/patch/9122961/
https://patchwork.kernel.org/patch/9122921/Also current series: https://patchwork.kernel.org/patch/9123071/
Seems to have comments pending.Dave is on vacation for another week or so, doubt he can respond in time -> Should we wait on this series till we get the cpufreq support in?
Rafael handles all the merges, etc. It would be better if you can reply to that thread instead.
Signature · 1 line
viresh
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Quoted 24 lines · Viresh Kumar
Quoted 23 lines · Nishanth Menon
Quoted 11 lines · Tony Lindgren
Quoted 10 lines · Viresh Kumar
Quoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Quoted 6 lines
Quoted 1 line
Acked-by Viresh Kumar <[email protected]>Applying all the dts changes into omap-for-v4.8/dt thanks.
Tony
Viresh, are we ready with the cpufreq series?
https://patchwork.kernel.org/patch/9122961/
https://patchwork.kernel.org/patch/9122921/
Quoted 9 lines
Quoted 5 lines
Also current series: https://patchwork.kernel.org/patch/9123071/
Seems to have comments pending.Dave is on vacation for another week or so, doubt he can respond in time -> Should we wait on this series till we get the cpufreq support in?
Rafael handles all the merges, etc. It would be better if you can reply to that thread instead.
Sorry for the delay responding here, the only issue with this series would be that we haven't received an ACK on the DT binding doc from cpufreq series [1] from a DT maintainer, so if comments are received there these patches could potentially change. I had pinged but still no response either way.
Regards,
Dave
cover ARM: dts: Add operating-points-v2 tables for TI platforms
Hi,
Quoted 40 lines · Dave Gerlach
Quoted 24 lines · Viresh Kumar
Quoted 23 lines · Nishanth Menon
Quoted 11 lines · Tony Lindgren
Quoted 10 lines · Viresh Kumar
Quoted 8 lines · Dave Gerlach
Hi,
This series adds operating-points-v2 tables for am335x, am437x, dra7xx, and am57xx based platforms along with some support patches so that we can enable more OPPs for the CPU on these platforms.These patches rely on the ti-cpufreq series sent here [1] and provide opp-supported-hw data for each OPP so that only the appropriate OPPs for a specific piece of silicon get enabled.
Quoted 6 lines
Quoted 1 line
Acked-by Viresh Kumar <[email protected]>Applying all the dts changes into omap-for-v4.8/dt thanks.
Tony
Viresh, are we ready with the cpufreq series?
https://patchwork.kernel.org/patch/9122961/
https://patchwork.kernel.org/patch/9122921/Quoted 9 lines
Quoted 5 lines
Also current series: https://patchwork.kernel.org/patch/9123071/
Seems to have comments pending.Dave is on vacation for another week or so, doubt he can respond in time -> Should we wait on this series till we get the cpufreq support in?
Rafael handles all the merges, etc. It would be better if you can reply to that thread instead.
Sorry for the delay responding here, the only issue with this series would be that we haven't received an ACK on the DT binding doc from cpufreq series [1] from a DT maintainer, so if comments are received there these patches could potentially change. I had pinged but still no response either way.
Quoted 4 lines
Regards,
Dave
Seems this got merged and is already part of master, even though the binding it uses is not yet finalized or accepted. I am about to send v2 of the ti-cpufreq series that makes use of these bindings, and I will be sending a series to fix these nodes that has already been merged, however it should *NOT* be merged. until the binding and driver have been merged, as it could still potentially change.
Also, this series replaced the OPP v1 tables for am33xx and dra7, so cpufreq is no longer enabled at the moment for these platforms. To fix this we could revert patches:
f80bc97fd0a9 ("ARM: dts: dra7: Move to operating-points-v2 table") c36e6ec90487 ("ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu") 4317be116210 ("ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver")
until the ti-cpufreq driver series is merged, at which point we can add them back in to re-enable cpufreq with the new driver.
Regards,
Dave