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mmc: fsl_esdhc: don't set XFERTYP_RSPTYP_48_BUSY for CMD with busy response

PATCH Superseded Yangbo Lu 3 participants 13 messages May 20, 2016 – Jul 28, 2016

Subsystems (2)
PowerPC MMC, SD and SDIO

v1 of 2 Superseded Latest is v2 →

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Yangbo Lu

author
#0 lore raw

PATCH 1/4 mmc: fsl_esdhc: don't set XFERTYP_RSPTYP_48_BUSY for CMD with busy response

For CMD with busy response, the eSDHC driver would poll DAT0 until CMD completion rather than polling IRQSTAT. So, don't set XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC) in IRQSTAT.

Signed-off-by Yangbo Lu <[email protected]>
---
 drivers/mmc/fsl_esdhc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)
drivers/mmc/fsl_esdhc.c +10 -2
index 3acf9e8..b06dd69 100644
@@ -126,8 +126,16 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 		xfertyp |= XFERTYP_CICEN;
 	if (cmd->resp_type & MMC_RSP_136)
 		xfertyp |= XFERTYP_RSPTYP_136;
-	else if (cmd->resp_type & MMC_RSP_BUSY)
-		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+	/*
+	 * For CMD with busy response, the eSDHC driver would poll DAT0
+	 * until CMD completion rather than polling IRQSTAT. So, don't
+	 * set XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC)
+	 * in IRQSTAT.
+	 *
+	 * Remove:
+	 * else if (cmd->resp_type & MMC_RSP_BUSY)
+	 *      xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+	 */
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
Signature · 1 line
2.1.0.27.g96db324
author
#1 lore raw

PATCH 2/4 mmc: send STOP command when the READ/WIRTE commands fail

The STOP command should be sent to stop data transfer when the READ/WRITE commands fail. Otherwise, any subsequent command will fail to be sent.

Signed-off-by Yangbo Lu <[email protected]>
---
 drivers/mmc/mmc.c         | 28 +++++++++++++++++++---------
 drivers/mmc/mmc_private.h |  1 +
 drivers/mmc/mmc_write.c   |  8 ++------
 3 files changed, 22 insertions(+), 15 deletions(-)
drivers/mmc/mmc.c +19 -9
index d3c22ab..713a934 100644
@@ -197,6 +197,21 @@ struct mmc *find_mmc_device(int dev_num)
 	return NULL;
 }
 
+int mmc_send_stop(struct mmc *mmc)
+{
+	struct mmc_cmd cmd;
+	int err;
+
+	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+	cmd.cmdarg = 0;
+	cmd.resp_type = MMC_RSP_R1b;
+
+	err = mmc_send_cmd(mmc, &cmd, NULL);
+	if (err)
+		printf("mmc fail to send stop cmd\n");
+	return err;
+}
+
 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 			   lbaint_t blkcnt)
 {

@@ -220,19 +235,14 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
 	data.blocksize = mmc->read_bl_len;
 	data.flags = MMC_DATA_READ;
 
-	if (mmc_send_cmd(mmc, &cmd, &data))
+	if (mmc_send_cmd(mmc, &cmd, &data)) {
+		mmc_send_stop(mmc);
 		return 0;
+	}
 
 	if (blkcnt > 1) {
-		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-		cmd.cmdarg = 0;
-		cmd.resp_type = MMC_RSP_R1b;
-		if (mmc_send_cmd(mmc, &cmd, NULL)) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-			printf("mmc fail to send stop cmd\n");
-#endif
+		if (mmc_send_stop(mmc))
 			return 0;
-		}
 	}
 
 	return blkcnt;
drivers/mmc/mmc_private.h +1 -0
index d3f6bfe..df507fc 100644
@@ -16,6 +16,7 @@ extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 			struct mmc_data *data);
 extern int mmc_send_status(struct mmc *mmc, int timeout);
 extern int mmc_set_blocklen(struct mmc *mmc, int len);
+int mmc_send_stop(struct mmc *mmc);
 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
 void mmc_adapter_card_type_ident(void);
 #endif
drivers/mmc/mmc_write.c +2 -6
index 7b186f8..4f00657 100644
@@ -148,6 +148,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
 
 	if (mmc_send_cmd(mmc, &cmd, &data)) {
 		printf("mmc write failed\n");
+		mmc_send_stop(mmc);
 		return 0;
 	}
 

@@ -155,13 +156,8 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start,
 	 * token, not a STOP_TRANSMISSION request.
 	 */
 	if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
-		cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-		cmd.cmdarg = 0;
-		cmd.resp_type = MMC_RSP_R1b;
-		if (mmc_send_cmd(mmc, &cmd, NULL)) {
-			printf("mmc fail to send stop cmd\n");
+		if (mmc_send_stop(mmc))
 			return 0;
-		}
 	}
 
 	/* Waiting for the ready status */
Signature · 1 line
2.1.0.27.g96db324
#2 lore raw

PATCH 2/4 mmc: send STOP command when the READ/WIRTE commands fail

Quoted 10 lines · Yangbo Lu

The STOP command should be sent to stop data transfer when the READ/WRITE commands fail. Otherwise, any subsequent command will fail to be sent.

Signed-off-by Yangbo Lu <[email protected]>
---
 drivers/mmc/mmc.c         | 28 +++++++++++++++++++---------
 drivers/mmc/mmc_private.h |  1 +
 drivers/mmc/mmc_write.c   |  8 ++------
 3 files changed, 22 insertions(+), 15 deletions(-)

Pantelis,

Would you please review this set?

Thanks.

York

author
#3 lore raw

PATCH 3/4 mmc: fsl_esdhc: add error recovery for data transfer with Auto CMD12

In reply to Yangbo Lu

For data transfer with Auto CMD12, the host will not send an Auto CMD12 to stop when the transfer fails. So this patch adds a flag to indicate the READ/WRITE command error, and makes the driver continue to send a CMD12 manually.

Signed-off-by Yangbo Lu <[email protected]>
---
 drivers/mmc/fsl_esdhc.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)
drivers/mmc/fsl_esdhc.c +20 -2
index b06dd69..744037e 100644
@@ -96,6 +96,9 @@ struct fsl_esdhc_priv {
 	struct udevice *dev;
 	int non_removable;
 	struct gpio_desc cd_gpio;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+	int rw_err;
+#endif
 };
 
 /* Return the XFERTYP flags for a given command and data packet */

@@ -350,8 +353,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
-	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
-		return 0;
+	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) {
+		if (priv->rw_err)
+			priv->rw_err = 0;
+		else
+			return 0;
+	}
 #endif
 
 	esdhc_write32(&regs->irqstat, -1);

@@ -506,6 +513,13 @@ out:
 		/* If this was CMD11, then notify that power cycle is needed */
 		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
 			printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+		if (cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK ||
+		    cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK ||
+		    cmd->cmdidx == MMC_CMD_WRITE_SINGLE_BLOCK ||
+		    cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)
+			priv->rw_err = 1;
+#endif
 	}
 
 	esdhc_write32(&regs->irqstat, -1);

@@ -796,6 +810,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
 
 	priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+	priv->rw_err = 0;
+#endif
+
 	mmc = mmc_create(&priv->cfg, priv);
 	if (mmc == NULL)
 		return -1;
Signature · 1 line
2.1.0.27.g96db324
author
#4 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

In reply to Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26 ++++++++++++++++++++++++++
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)
arch/powerpc/include/asm/config_mpc85xx.h +8 -0
index eccc146..197ee42 100644
@@ -148,6 +148,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4

@@ -369,6 +370,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5

@@ -530,6 +532,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474

@@ -568,6 +571,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_ERRATUM_USB14
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474

@@ -686,6 +690,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007798
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X

@@ -802,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_ERRATUM_A006261
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1

@@ -823,6 +829,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #endif
 #if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
 #define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_MAX_CPUS			1
 #endif

@@ -882,6 +889,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #elif defined(CONFIG_PPC_T2081)
 #define CONFIG_SYS_NUM_FM1_DTSEC	6
 #define CONFIG_SYS_NUM_FM1_10GEC	2
drivers/mmc/fsl_esdhc.c +26 -0
index 744037e..fba87d2 100644
@@ -470,6 +470,32 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
 		esdhc_pio_read_write(mmc, data);
 #else
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
+		int timeout = 5000;
+		if (data->flags & MMC_DATA_WRITE) {
+			while (esdhc_read32(&regs->prsstat) & PRSSTAT_WTA)
+				;
+
+			/* Poll on DATA0 line for 500 ms */
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_DAT0)) {
+				udelay(100);
+				timeout--;
+				if (timeout <= 0) {
+					err = TIMEOUT;
+					break;
+				}
+			}
+			if (!err) {
+				esdhc_write32(&regs->sysctl,
+					      esdhc_read32(&regs->sysctl) |
+					      SYSCTL_RSTD);
+				while ((esdhc_read32(&regs->sysctl) &
+					SYSCTL_RSTD))
+					;
+			}
+			goto out;
+		}
+#endif
 		do {
 			irqstat = esdhc_read32(&regs->irqstat);
include/configs/ls1021aqds.h +1 -0
index 62cf6e5..a656976 100644
@@ -415,6 +415,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_GENERIC_MMC
 
 #define CONFIG_CMD_FAT
include/configs/ls1021atwr.h +1 -0
index b2e431a..912af90 100644
@@ -303,6 +303,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_GENERIC_MMC
 
 #define CONFIG_CMD_FAT
include/configs/ls1043a_common.h +1 -0
index e900c50..e1e1518 100644
@@ -186,6 +186,7 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_FAT
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DOS_PARTITION
include/configs/ls2080a_simu.h +1 -0
index 0dbe95f..a431b66 100644
@@ -134,6 +134,7 @@
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
include/configs/ls2080aqds.h +1 -0
index 91fad0a..5c38bdf 100644
@@ -328,6 +328,7 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
include/configs/ls2080ardb.h +1 -0
index 15a1172..518aa17 100644
@@ -310,6 +310,7 @@ unsigned long get_board_sys_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
include/fsl_esdhc.h +1 -0
index fa760a5..2d049b7 100644
@@ -91,6 +91,7 @@
 #define PRSSTAT_CINS		(0x00010000)
 #define PRSSTAT_BREN		(0x00000800)
 #define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_WTA		(0x00000100)
 #define PRSSTAT_SDSTB		(0X00000008)
 #define PRSSTAT_DLA		(0x00000004)
 #define PRSSTAT_CICHB		(0x00000002)
Signature · 1 line
2.1.0.27.g96db324
#5 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Quoted 33 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Signed-off-by Yangbo Lu <[email protected]>
Quoted 11 lines
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26 ++++++++++++++++++++++++++
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)

Yangbo,

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

author
#6 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Quoted 53 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 32 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)
Quoted 7 lines

Yangbo,

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

Thanks.

#7 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Quoted 55 lines · Yangbo Lu
Quoted 55 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 32 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)

Yangbo,

Quoted 8 lines
Quoted 5 lines

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

If use your patch by default, is there performance degression? I don't know fsl_esdhc controller..so i just ask this. :)

Quoted 11 lines

Thanks.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

author
#8 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Hi Jaehoon,

Quoted 68 lines

-----Original Message-----
From: Jaehoon Chung [mailto:jh80.chung at samsung.com]
Sent: Wednesday, July 27, 2016 7:21 PM
To: Yangbo Lu; york sun; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 13 lines · Yangbo Lu
Quoted 13 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 5 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never

completed.

Quoted 41 lines
Quoted 41 lines
Quoted 22 lines

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)

Yangbo,

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

Quoted 9 lines
Quoted 5 lines
Quoted 2 lines

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

If use your patch by default, is there performance degression? I don't know fsl_esdhc controller..so i just ask this. :)

[Lu Yangbo-B47093] The original code polls 'Transfer Complete' interrupt or 'DMA' interrupt for transfer completion. This patch will change to poll DAT0/BUSY line.
There should be no difference, but I think the udelay(100) in polling DAT0/BUSY may have a little affect on performance. Anyway the patch will only apply to the silicon which has this erratum.

Thanks.

Quoted 11 lines
Quoted 11 lines

Thanks.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#9 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Hi Yangbo,

Quoted 77 lines · Yangbo Lu

Hi Jaehoon,

Quoted 74 lines

-----Original Message-----
From: Jaehoon Chung [mailto:jh80.chung at samsung.com]
Sent: Wednesday, July 27, 2016 7:21 PM
To: Yangbo Lu; york sun; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 13 lines · Yangbo Lu
Quoted 13 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 5 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never

completed.

Quoted 46 lines
Quoted 36 lines
Quoted 22 lines

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)
Quoted 7 lines

Yangbo,

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

Quoted 8 lines
Quoted 3 lines

If use your patch by default, is there performance degression? I don't know fsl_esdhc controller..so i just ask this. :)

[Lu Yangbo-B47093] The original code polls 'Transfer Complete' interrupt or 'DMA' interrupt for transfer completion. This patch will change to poll DAT0/BUSY line.
There should be no difference, but I think the udelay(100) in polling DAT0/BUSY may have a little affect on performance. Anyway the patch will only apply to the silicon which has this erratum.

Thanks for explanation! :)
I think you can split to config files and mmc side.

And

while (esdhc_read32(&regs->prsstat) & PRSSTAT_WTA);

This code has the potential infinite loop..

while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD));

Ditto. In my experience, it's good that potential infinite loop case is removed. Because we can't sure that this condition has to hit. :)

Best Regards,
Jaehoon Chung

Quoted 18 lines

Thanks.

Quoted 11 lines
Quoted 11 lines

Thanks.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

author
#10 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Hi Jaehoon,

Quoted 96 lines

-----Original Message-----
From: Jaehoon Chung [mailto:jh80.chung at samsung.com]
Sent: Thursday, July 28, 2016 1:01 PM
To: Yangbo Lu; york sun; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Hi Yangbo,

Quoted 41 lines · Yangbo Lu

Hi Jaehoon,

Quoted 38 lines

-----Original Message-----
From: Jaehoon Chung [mailto:jh80.chung at samsung.com]
Sent: Wednesday, July 27, 2016 7:21 PM
To: Yangbo Lu; york sun; u-boot at lists.denx.de
Subject: Re: [U-Boot] [PATCH 4/4] mmc: add workaround for eSDHC erratum
A009620

Quoted 13 lines · Yangbo Lu
Quoted 13 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 5 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never

completed.

Quoted 10 lines
Quoted 10 lines
Quoted 10 lines

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and

poll

Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines

the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer

complete)

Quoted 36 lines
Quoted 36 lines
Quoted 35 lines
Quoted 25 lines
Quoted 11 lines

or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)
Quoted 7 lines

Yangbo,

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

Quoted 5 lines
Quoted 3 lines

If use your patch by default, is there performance degression? I don't know fsl_esdhc controller..so i just ask this. :)

[Lu Yangbo-B47093] The original code polls 'Transfer Complete'

Quoted 8 lines

interrupt or 'DMA' interrupt for transfer completion.

Quoted 2 lines

This patch will change to poll DAT0/BUSY line.
There should be no difference, but I think the udelay(100) in polling

DAT0/BUSY may have a little affect on performance.

Quoted 1 line

Anyway the patch will only apply to the silicon which has this erratum.

Thanks for explanation! :)
I think you can split to config files and mmc side.

[Lu Yangbo-B47093] Ok, this should be no problem :)

Quoted 5 lines

And

while (esdhc_read32(&regs->prsstat) & PRSSTAT_WTA);

Quoted 8 lines

This code has the potential infinite loop..

while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD));

Ditto. In my experience, it's good that potential infinite loop case is removed.
Because we can't sure that this condition has to hit. :)

[Lu Yangbo-B47093] I think you're right. Although this would be ok from hardware perspective, there is still potential risk. But how to remove them, is there any good idea? Is it proper to add timeout checking here ?

Thanks.

Quoted 21 lines

Best Regards,
Jaehoon Chung

Quoted 18 lines

Thanks.

Quoted 11 lines
Quoted 11 lines

Thanks.

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#11 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

In reply to Yangbo Lu
Quoted 55 lines · Yangbo Lu
Quoted 55 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 32 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never completed.

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)

Yangbo,

Quoted 9 lines
Quoted 5 lines

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-fsl-layerscape/config.h

York

author
#12 lore raw

PATCH 4/4 mmc: add workaround for eSDHC erratum A009620

Quoted 74 lines

-----Original Message-----
From: york sun
Sent: Wednesday, July 27, 2016 10:48 PM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 13 lines · Yangbo Lu
Quoted 13 lines

-----Original Message-----
From: york sun
Sent: Tuesday, July 26, 2016 1:38 AM
To: Yangbo Lu; u-boot at lists.denx.de
Subject: Re: [PATCH 4/4] mmc: add workaround for eSDHC erratum A009620

Quoted 5 lines · Yangbo Lu

Erratum Title:
Data timeout error not getting set in case of command with busy response (R1b) as well as for busy period after last write block transfer.

Quoted 5 lines
Quoted 5 lines
Quoted 5 lines

Description:
In the event that a busy timeout occurs for a command with a busy response (e.g. R1b response) as well as busy period after the last write block, the eSDHC does not set the IRQSTAT[DTOE] bit or the IRQSTAT[TC]. Therefore, the current command transfer is never

completed.

Quoted 38 lines
Quoted 38 lines
Quoted 22 lines

Workaround:
Workaround for CMD with busy:
Don't set the XFRTYP[RSP]=2'b11 for commands with busy response and poll the busy status of the card from the PRSSTAT[DLSL]

Workaround for busy period after last write block:
1. After the command completion interrupt (IRQSTAT[CC]), wait for de-assertion of PRSTAT[WTA].
2. Once PRSTAT[WTA] is de-asserted, start the software timer and poll the busy signal (DAT0) using PRSTAT[DLSL[0]].
3. Wait for DAT0 signal to go high (which indicate transfer complete) or software timer expiry (which indicate data timeout error).
4. Issue soft reset for data (SYSCTL[RSTD]).
5. In case of data timeout error (detected in step 3) perform the error recovery.

The workaround for CMD with busy has already been applied in eSDHC driver. This patch is to add workaround for the 2nd issue, and the fixup platforms include PowerPC(P1010/P2020/P5020/P5040/T1024/T1040/ T2080/T4240) and ARM(LS1021A/LS1043A/LS2080A).

Quoted 4 lines
Signed-off-by Yangbo Lu <[email protected]>
---
 arch/powerpc/include/asm/config_mpc85xx.h |  8 ++++++++
 drivers/mmc/fsl_esdhc.c                   | 26

++++++++++++++++++++++++++

Quoted 8 lines
 include/configs/ls1021aqds.h              |  1 +
 include/configs/ls1021atwr.h              |  1 +
 include/configs/ls1043a_common.h          |  1 +
 include/configs/ls2080a_simu.h            |  1 +
 include/configs/ls2080aqds.h              |  1 +
 include/configs/ls2080ardb.h              |  1 +
 include/fsl_esdhc.h                       |  1 +
 9 files changed, 41 insertions(+)

Yangbo,

Quoted 9 lines
Quoted 5 lines

Why do you put the macro CONFIG_SYS_FSL_ERRATUM_ESDHC_A009620 in board header file if the erratum applies to the SoC?

York

[Lu Yangbo-B47093] Thanks a lot, York.
Could you suggest any better place where I can put this macro? I didn't find such a good place :(

Quoted 4 lines

arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-fsl-layerscape/config.h

York

[Lu Yangbo-B47093] Got it. Thanks a lot, York :) I will send the new version.