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Exynos big-endian repost

PATCH New Ben Dooks 4 participants 23 messages Jun 21, 2016 – Aug 10, 2016

Subsystems (8)
Arm (32-bit) Arm sub-architectures Crypto API Arm Samsung Exynos +4 more subsystems
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Ben Dooks

author
#0 lore raw

Here are my patches for getting big-endian working on Exynos platform which have been developed with Matthew Leach.

author
#1 lore raw

PATCH v2 1/1 01/11] ARM: EXYNOS: fixup debug macros for big-endian

The exynos low-level debug macros need to be fixed if the system is being built big endian. Add the necessary endian swaps for accessing the registers to get output working again

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/include/debug/samsung.S | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/include/debug/samsung.S +8 -0
index 8d8d922..f4eeed2 100644
@@ -15,11 +15,13 @@
 
 	.macro fifo_level_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		and	\rd, \rd, #S5PV210_UFSTAT_TXMASK
 	.endm
 
 	.macro  fifo_full_s5pv210 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S5PV210_UFSTAT_TXFULL
 	.endm
 

@@ -28,6 +30,7 @@
 
 	.macro fifo_level_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		and	\rd, \rd, #S3C2440_UFSTAT_TXMASK
 	.endm
 

@@ -37,6 +40,7 @@
 
 	.macro  fifo_full_s3c2440 rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2440_UFSTAT_TXFULL
 	.endm
 

@@ -50,6 +54,7 @@
 
 	.macro	busyuart, rd, rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...

@@ -61,6 +66,7 @@
 1001:
 		@ busy waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
 

@@ -69,6 +75,7 @@
 
 	.macro	waituart,rd,rx
 		ldr	\rd, [\rx, # S3C2410_UFCON]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UFCON_FIFOMODE	@ fifo enabled?
 		beq	1001f				@
 		@ FIFO enabled...

@@ -80,6 +87,7 @@
 1001:
 		@ idle waiting for non fifo
 		ldr	\rd, [\rx, # S3C2410_UTRSTAT]
+ARM_BE8(rev \rd, \rd)
 		tst	\rd, #S3C2410_UTRSTAT_TXFE
 		beq	1001b
Signature · 1 line
2.8.1
Applied
#2 lore raw

PATCH v2 1/1 01/11] ARM: EXYNOS: fixup debug macros for big-endian

Quoted 8 lines · Ben Dooks

The exynos low-level debug macros need to be fixed if the system is being built big endian. Add the necessary endian swaps for accessing the registers to get output working again

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/include/debug/samsung.S | 8 ++++++++
 1 file changed, 8 insertions(+)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#3 lore raw

PATCH v2 1/1 02/11] ARM: Samsung: fixup endian issues in cpu detection

In reply to Ben Dooks

If the system is built for big endian, then the cpu identificaiton register will be read in the wrong order. Fix this by using readl_relaxed() on the register.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/plat-samsung/cpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/plat-samsung/cpu.c +4 -4
index 71333bb..bd12a55 100644
@@ -29,14 +29,14 @@ EXPORT_SYMBOL(samsung_rev);
 
 void __init s3c64xx_init_cpu(void)
 {
-	samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
+	samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118);
 	if (!samsung_cpu_id) {
 		/*
 		 * S3C6400 has the ID register in a different place,
 		 * and needs a write before it can be read.
 		 */
-		__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
-		samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
+		writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
+		samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
 	}
 
 	samsung_cpu_rev = 0;

@@ -46,7 +46,7 @@ void __init s3c64xx_init_cpu(void)
 
 void __init s5p_init_cpu(void __iomem *cpuid_addr)
 {
-	samsung_cpu_id = __raw_readl(cpuid_addr);
+	samsung_cpu_id = readl_relaxed(cpuid_addr);
 	samsung_cpu_rev = samsung_cpu_id & 0xFF;
 
 	pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
Signature · 1 line
2.8.1
Applied
#4 lore raw

PATCH v2 1/1 02/11] ARM: Samsung: fixup endian issues in cpu detection

Quoted 8 lines · Ben Dooks

If the system is built for big endian, then the cpu identificaiton register will be read in the wrong order. Fix this by using readl_relaxed() on the register.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/plat-samsung/cpu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#5 lore raw

PATCH v2 1/1 03/11] ARM: EXYNOS: fixups for big-endian operation

In reply to Ben Dooks

If the kernel is built big endian, then using the __raw read and write IO accessors is not going to work as they end up writing big-endian data to little-endian IO registers. Fix this by using the readl and writel relaxed versions which ensure little endian IO.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/firmware.c | 16 ++++++++--------
 arch/arm/mach-exynos/headsmp.S  |  3 +++
 arch/arm/mach-exynos/platsmp.c  |  4 ++--
 3 files changed, 13 insertions(+), 10 deletions(-)
arch/arm/mach-exynos/firmware.c +8 -8
index 1bfd1b0..96b5e92 100644
@@ -41,9 +41,9 @@ static int exynos_do_idle(unsigned long mode)
 	case FW_DO_IDLE_AFTR:
 		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 			exynos_save_cp15();
-		__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
+		writel_relaxed(virt_to_phys(exynos_cpu_resume_ns),
 			     sysram_ns_base_addr + 0x24);
-		__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
+		writel_relaxed(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
 		if (soc_is_exynos3250()) {
 			flush_cache_all();
 			exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,

@@ -97,7 +97,7 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 	if (soc_is_exynos4412())
 		boot_reg += 4 * cpu;
 
-	__raw_writel(boot_addr, boot_reg);
+	writel_relaxed(boot_addr, boot_reg);
 	return 0;
 }
 

@@ -113,7 +113,7 @@ static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
 	if (soc_is_exynos4412())
 		boot_reg += 4 * cpu;
 
-	*boot_addr = __raw_readl(boot_reg);
+	*boot_addr = readl_relaxed(boot_reg);
 	return 0;
 }
 

@@ -234,20 +234,20 @@ void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
 {
 	unsigned int tmp;
 
-	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 
 	if (mode & BOOT_MODE_MASK)
 		tmp &= ~BOOT_MODE_MASK;
 
 	tmp |= mode;
-	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 }
 
 void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
 {
 	unsigned int tmp;
 
-	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
+	tmp = readl_relaxed(REG_CPU_STATE_ADDR + cpu * 4);
 	tmp &= ~mode;
-	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
+	writel_relaxed(tmp, REG_CPU_STATE_ADDR + cpu * 4);
 }
arch/arm/mach-exynos/headsmp.S +3 -0
index b54f970..d3d24ab 100644
@@ -12,12 +12,15 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 /*
  * exynos4 specific entry point for secondary CPUs.  This provides
  * a "holding pen" into which all secondary cores are held until we're
  * ready for them to initialise.
  */
 ENTRY(exynos4_secondary_startup)
+ARM_BE8(setend	be)
 	mrc	p15, 0, r0, c0, c0, 5
 	and	r0, r0, #15
 	adr	r4, 1f
arch/arm/mach-exynos/platsmp.c +2 -2
index 85c3be6..98ffe1e 100644
@@ -264,7 +264,7 @@ int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
 			ret = PTR_ERR(boot_reg);
 			goto fail;
 		}
-		__raw_writel(boot_addr, boot_reg);
+		writel_relaxed(boot_addr, boot_reg);
 		ret = 0;
 	}
 fail:

@@ -289,7 +289,7 @@ int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr)
 			ret = PTR_ERR(boot_reg);
 			goto fail;
 		}
-		*boot_addr = __raw_readl(boot_reg);
+		*boot_addr = readl_relaxed(boot_reg);
 		ret = 0;
 	}
 fail:
Signature · 1 line
2.8.1
Applied
#6 lore raw

PATCH v2 1/1 03/11] ARM: EXYNOS: fixups for big-endian operation

Quoted 11 lines · Ben Dooks

If the kernel is built big endian, then using the __raw read and write IO accessors is not going to work as they end up writing big-endian data to little-endian IO registers. Fix this by using the readl and writel relaxed versions which ensure little endian IO.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/firmware.c | 16 ++++++++--------
 arch/arm/mach-exynos/headsmp.S  |  3 +++
 arch/arm/mach-exynos/platsmp.c  |  4 ++--
 3 files changed, 13 insertions(+), 10 deletions(-)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#7 lore raw

PATCH v2 1/1 04/11] ARM: EXYNOS: fixup endian in pm/pmu

In reply to Ben Dooks

Fix the PMU code endian access code to deal with kernels built for big endian operation.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/common.h     | 4 ++--
 arch/arm/mach-exynos/pm.c         | 4 ++--
 arch/arm/mach-exynos/pm_domains.c | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)
arch/arm/mach-exynos/common.h +2 -2
index 5365bf1..19e9d25 100644
@@ -174,12 +174,12 @@ extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);
 
 static inline void pmu_raw_writel(u32 val, u32 offset)
 {
-	__raw_writel(val, pmu_base_addr + offset);
+	writel_relaxed(val, pmu_base_addr + offset);
 }
 
 static inline u32 pmu_raw_readl(u32 offset)
 {
-	return __raw_readl(pmu_base_addr + offset);
+	return readl_relaxed(pmu_base_addr + offset);
 }
 
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
arch/arm/mach-exynos/pm.c +2 -2
index c43b776..52d78eb 100644
@@ -132,9 +132,9 @@ static void exynos_set_wakeupmask(long mask)
 
 static void exynos_cpu_set_boot_vector(long flags)
 {
-	__raw_writel(virt_to_phys(exynos_cpu_resume),
+	writel_relaxed(virt_to_phys(exynos_cpu_resume),
 		     exynos_boot_vector_addr());
-	__raw_writel(flags, exynos_boot_vector_flag());
+	writel_relaxed(flags, exynos_boot_vector_flag());
 }
 
 static int exynos_aftr_finisher(unsigned long flags)
arch/arm/mach-exynos/pm_domains.c +3 -3
index 875a2ba..0e075d9 100644
@@ -70,12 +70,12 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 	}
 
 	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
-	__raw_writel(pwr, base);
+	writel_relaxed(pwr, base);
 
 	/* Wait max 1ms */
 	timeout = 10;
 
-	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
+	while ((readl_relaxed(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
 		if (!timeout) {
 			op = (power_on) ? "enable" : "disable";
 			pr_err("Power domain %s %s failed\n", domain->name, op);

@@ -185,7 +185,7 @@ static __init int exynos4_pm_init_power_domain(void)
 			clk_put(pd->oscclk);
 
 no_clk:
-		on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
+		on = readl_relaxed(pd->base + 0x4) & INT_LOCAL_PWR_EN;
 
 		pm_genpd_init(&pd->pd, NULL, !on);
 		of_genpd_add_provider_simple(np, &pd->pd);
Signature · 1 line
2.8.1
Applied
#8 lore raw

PATCH v2 1/1 04/11] ARM: EXYNOS: fixup endian in pm/pmu

Quoted 9 lines · Ben Dooks

Fix the PMU code endian access code to deal with kernels built for big endian operation.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/common.h     | 4 ++--
 arch/arm/mach-exynos/pm.c         | 4 ++--
 arch/arm/mach-exynos/pm_domains.c | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#9 lore raw

PATCH v2 1/1 05/11] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly

In reply to Ben Dooks

Now the initial fixes have the big-endian code working on EXYNOS, make sure we explicitly mark our arch as being big endian capable.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-exynos/Kconfig +1 -0
index e65aa7d..14906bf 100644
@@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS
 	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ARM_AMBA
 	select ARM_GIC
 	select COMMON_CLK_SAMSUNG
Signature · 1 line
2.8.1
#10 lore raw

PATCH v2 1/1 05/11] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly

Quoted 13 lines · Ben Dooks

Now the initial fixes have the big-endian code working on EXYNOS, make sure we explicitly mark our arch as being big endian capable.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-exynos/Kconfig +0 -0
index e65aa7d..14906bf 100644

arch/arm/mach-exynos/Kconfig menuconfig ARCH_EXYNOS · line 19

Quoted 7 lines
arch/arm/mach-exynos/Kconfig +1 -0
@@ -13,6 +13,7 @@ menuconfig ARCH_EXYNOS
 	select ARCH_HAS_BANDGAP
 	select ARCH_HAS_HOLES_MEMORYMODEL
 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_SUPPORTS_BIG_ENDIAN
 	select ARM_AMBA
 	select ARM_GIC
 	select COMMON_CLK_SAMSUNG

I'll wait with this one till other patches get in.

Best regards,
Krzysztof

Applied
#11 lore raw

PATCH v2 1/1 05/11] ARM: EXYNOS: Enable ARCH_SUPPORTS_BIG_ENDIAN explicitly

In reply to Ben Dooks
Quoted 7 lines · Ben Dooks

Now the initial fixes have the big-endian code working on EXYNOS, make sure we explicitly mark our arch as being big endian capable.

Signed-off-by Ben Dooks <[email protected]>
---
 arch/arm/mach-exynos/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Thanks, applied.

Best regards,
Krzysztof

author
#12 lore raw

PATCH v2 1/1 06/11] ARM: Samsung: fixup usage of __raw IO

In reply to Ben Dooks

Fix the use of __raw accesors in pm-common.c to use the _relaxed variants to deal with any issues due to endian related fetches.

Signed-off-by Ben Dooks <[email protected]>

---

---
 arch/arm/plat-samsung/pm-common.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm/plat-samsung/pm-common.c +4 -4
index 515cd53..6534c3f 100644
@@ -31,7 +31,7 @@
 void s3c_pm_do_save(struct sleep_save *ptr, int count)
 {
 	for (; count > 0; count--, ptr++) {
-		ptr->val = __raw_readl(ptr->reg);
+		ptr->val = readl_relaxed(ptr->reg);
 		S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
 	}
 }

@@ -51,9 +51,9 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
 {
 	for (; count > 0; count--, ptr++) {
 		pr_debug("restore %p (restore %08lx, was %08x)\n",
-				ptr->reg, ptr->val, __raw_readl(ptr->reg));
+				ptr->reg, ptr->val, readl_relaxed(ptr->reg));
 
-		__raw_writel(ptr->val, ptr->reg);
+		writel_relaxed(ptr->val, ptr->reg);
 	}
 }
 

@@ -71,5 +71,5 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count)
 void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
 {
 	for (; count > 0; count--, ptr++)
-		__raw_writel(ptr->val, ptr->reg);
+		writel_relaxed(ptr->val, ptr->reg);
 }
Signature · 1 line
2.8.1
Applied
#13 lore raw

PATCH v2 1/1 06/11] ARM: Samsung: fixup usage of __raw IO

Quoted 8 lines · Ben Dooks

Fix the use of __raw accesors in pm-common.c to use the _relaxed variants to deal with any issues due to endian related fetches.

Signed-off-by Ben Dooks <[email protected]>

---

---
 arch/arm/plat-samsung/pm-common.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#14 lore raw

PATCH v2 1/1 07/11] ARM: EXYNOS: fixup for __raw operations in suspend.c

In reply to Ben Dooks

Fix the PMU code endian access code to deal with kernels built for big endian operation by changing the __raw IO accessors to the _relaxed variants.

Signed-off-by Ben Dooks <[email protected]>

---

---
 arch/arm/mach-exynos/suspend.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
arch/arm/mach-exynos/suspend.c +6 -6
index f216909..3750575 100644
@@ -301,7 +301,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
 	unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 	unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 
-	__raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
+	writel_relaxed(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 
 	if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
 		mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);

@@ -373,8 +373,8 @@ static void exynos5420_pm_prepare(void)
 	 * needs to restore it back in case, the primary cpu fails to
 	 * suspend for any reason.
 	 */
-	exynos5420_cpu_state = __raw_readl(sysram_base_addr +
-						EXYNOS5420_CPU_STATE);
+	exynos5420_cpu_state = readl_relaxed(sysram_base_addr +
+					     EXYNOS5420_CPU_STATE);
 
 	exynos_pm_enter_sleep_mode();
 

@@ -504,11 +504,11 @@ static void exynos5420_pm_resume(void)
 	/* Restore the CPU0 low power state register */
 	tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 	pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
-		EXYNOS5_ARM_CORE0_SYS_PWR_REG);
+		       EXYNOS5_ARM_CORE0_SYS_PWR_REG);
 
 	/* Restore the sysram cpu state register */
-	__raw_writel(exynos5420_cpu_state,
-		sysram_base_addr + EXYNOS5420_CPU_STATE);
+	writel_relaxed(exynos5420_cpu_state,
+		       sysram_base_addr + EXYNOS5420_CPU_STATE);
 
 	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
 			S5P_CENTRAL_SEQ_OPTION);
Signature · 1 line
2.8.1
Applied
#15 lore raw

PATCH v2 1/1 07/11] ARM: EXYNOS: fixup for __raw operations in suspend.c

Quoted 9 lines · Ben Dooks

Fix the PMU code endian access code to deal with kernels built for big endian operation by changing the __raw IO accessors to the _relaxed variants.

Signed-off-by Ben Dooks <[email protected]>

---

---
 arch/arm/mach-exynos/suspend.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Thanks, applied for v4.8.

Best regards,
Krzysztof

author
#16 lore raw

PATCH v2 1/1 08/11] irqchip: exynos: fix usage of __raw IO

In reply to Ben Dooks

Fix the use of __raw IO accesors when the readl/writel_relaxed are better. This should fix issues if the kernel is running as big endian.

Signed-off-by Ben Dooks <[email protected]>

---
CC: Thomas Gleixner <[email protected]>
CC: Jason Cooper <[email protected]>
CC: Marc Zyngier <[email protected]>w

---
 drivers/irqchip/exynos-combiner.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)
drivers/irqchip/exynos-combiner.c +7 -7
index ead15be..b78a169 100644
@@ -55,14 +55,14 @@ static void combiner_mask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 }
 
 static void combiner_unmask_irq(struct irq_data *data)
 {
 	u32 mask = 1 << (data->hwirq % 32);
 
-	__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+	writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 }
 
 static void combiner_handle_cascade_irq(struct irq_desc *desc)

@@ -75,7 +75,7 @@ static void combiner_handle_cascade_irq(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
-	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+	status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
 	spin_unlock(&irq_controller_lock);
 	status &= chip_data->irq_mask;
 

@@ -135,7 +135,7 @@ static void __init combiner_init_one(struct combiner_chip_data *combiner_data,
 	combiner_data->parent_irq = irq;
 
 	/* Disable all interrupts */
-	__raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
+	writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
 }
 
 static int combiner_irq_domain_xlate(struct irq_domain *d,

@@ -218,7 +218,7 @@ static int combiner_suspend(void)
 
 	for (i = 0; i < max_nr; i++)
 		combiner_data[i].pm_save =
-			__raw_readl(combiner_data[i].base + COMBINER_ENABLE_SET);
+			readl_relaxed(combiner_data[i].base + COMBINER_ENABLE_SET);
 
 	return 0;
 }

@@ -235,9 +235,9 @@ static void combiner_resume(void)
 	int i;
 
 	for (i = 0; i < max_nr; i++) {
-		__raw_writel(combiner_data[i].irq_mask,
+		writel_relaxed(combiner_data[i].irq_mask,
 			     combiner_data[i].base + COMBINER_ENABLE_CLEAR);
-		__raw_writel(combiner_data[i].pm_save,
+		writel_relaxed(combiner_data[i].pm_save,
 			     combiner_data[i].base + COMBINER_ENABLE_SET);
 	}
 }
Signature · 1 line
2.8.1
Applied
#17 lore raw

PATCH v2 1/1 08/11] irqchip: exynos: fix usage of __raw IO

Ben,

Quoted 4 lines · Ben Dooks

Fix the use of __raw IO accesors when the readl/writel_relaxed are better. This should fix issues if the kernel is running as big endian.

Quoted 8 lines
Signed-off-by Ben Dooks <[email protected]>

---
CC: Thomas Gleixner <[email protected]>
CC: Jason Cooper <[email protected]>
CC: Marc Zyngier <[email protected]>w

---
 drivers/irqchip/exynos-combiner.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Applied patches 8 and 9 of this series to irqchip/misc with minor subject line reformatting (watch double square brackets).

thx,

Jason.

author
#18 lore raw

PATCH v2 1/1 09/11] irqchip/s3c24xx: fixup IO accessors for big endian

In reply to Ben Dooks

Instead of using the __raw accesors, use the _relaxed versions to deal with any issues due to endian-ness of the CPU.

Signed-off-by Ben Dooks <[email protected]>

---
CC: Thomas Gleixner <[email protected]> (maintainer:IRQCHIP DRIVERS)
CC: Jason Cooper <[email protected]> (maintainer:IRQCHIP DRIVERS)
CC: Marc Zyngier <[email protected]> (maintainer:IRQCHIP DRIVERS)
CC: linux-kernel at vger.kernel.org (open list:IRQCHIP DRIVERS)
CC: linux-arm-kernel at lists.infradead.org

---
 drivers/irqchip/irq-s3c24xx.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)
drivers/irqchip/irq-s3c24xx.c +18 -18
index 5dc5a76..c25ce5a 100644
@@ -92,9 +92,9 @@ static void s3c_irq_mask(struct irq_data *data)
 	unsigned long mask;
 	unsigned int irqno;
 
-	mask = __raw_readl(intc->reg_mask);
+	mask = readl_relaxed(intc->reg_mask);
 	mask |= (1UL << irq_data->offset);
-	__raw_writel(mask, intc->reg_mask);
+	writel_relaxed(mask, intc->reg_mask);
 
 	if (parent_intc) {
 		parent_data = &parent_intc->irqs[irq_data->parent_irq];

@@ -119,9 +119,9 @@ static void s3c_irq_unmask(struct irq_data *data)
 	unsigned long mask;
 	unsigned int irqno;
 
-	mask = __raw_readl(intc->reg_mask);
+	mask = readl_relaxed(intc->reg_mask);
 	mask &= ~(1UL << irq_data->offset);
-	__raw_writel(mask, intc->reg_mask);
+	writel_relaxed(mask, intc->reg_mask);
 
 	if (parent_intc) {
 		irqno = irq_find_mapping(parent_intc->domain,

@@ -136,9 +136,9 @@ static inline void s3c_irq_ack(struct irq_data *data)
 	struct s3c_irq_intc *intc = irq_data->intc;
 	unsigned long bitval = 1UL << irq_data->offset;
 
-	__raw_writel(bitval, intc->reg_pending);
+	writel_relaxed(bitval, intc->reg_pending);
 	if (intc->reg_intpnd)
-		__raw_writel(bitval, intc->reg_intpnd);
+		writel_relaxed(bitval, intc->reg_intpnd);
 }
 
 static int s3c_irq_type(struct irq_data *data, unsigned int type)

@@ -172,9 +172,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
 	unsigned long newvalue = 0, value;
 
 	/* Set the GPIO to external interrupt mode */
-	value = __raw_readl(gpcon_reg);
+	value = readl_relaxed(gpcon_reg);
 	value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
-	__raw_writel(value, gpcon_reg);
+	writel_relaxed(value, gpcon_reg);
 
 	/* Set the external interrupt to pointed trigger type */
 	switch (type)

@@ -208,9 +208,9 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
 			return -EINVAL;
 	}
 
-	value = __raw_readl(extint_reg);
+	value = readl_relaxed(extint_reg);
 	value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
-	__raw_writel(value, extint_reg);
+	writel_relaxed(value, extint_reg);
 
 	return 0;
 }

@@ -315,8 +315,8 @@ static void s3c_irq_demux(struct irq_desc *desc)
 
 	chained_irq_enter(chip, desc);
 
-	src = __raw_readl(sub_intc->reg_pending);
-	msk = __raw_readl(sub_intc->reg_mask);
+	src = readl_relaxed(sub_intc->reg_pending);
+	msk = readl_relaxed(sub_intc->reg_mask);
 
 	src &= ~msk;
 	src &= irq_data->sub_bits;

@@ -337,7 +337,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
 	int pnd;
 	int offset;
 
-	pnd = __raw_readl(intc->reg_intpnd);
+	pnd = readl_relaxed(intc->reg_intpnd);
 	if (!pnd)
 		return false;
 

@@ -352,7 +352,7 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
 	 *
 	 * Thanks to Klaus, Shannon, et al for helping to debug this problem
 	 */
-	offset = __raw_readl(intc->reg_intpnd + 4);
+	offset = readl_relaxed(intc->reg_intpnd + 4);
 
 	/* Find the bit manually, when the offset is wrong.
 	 * The pending register only ever contains the one bit of the next

@@ -406,7 +406,7 @@ int s3c24xx_set_fiq(unsigned int irq, bool on)
 		intmod = 0;
 	}
 
-	__raw_writel(intmod, S3C2410_INTMOD);
+	writel_relaxed(intmod, S3C2410_INTMOD);
 	return 0;
 }
 

@@ -508,14 +508,14 @@ static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
 
 	last = 0;
 	for (i = 0; i < 4; i++) {
-		pend = __raw_readl(reg_source);
+		pend = readl_relaxed(reg_source);
 
 		if (pend == 0 || pend == last)
 			break;
 
-		__raw_writel(pend, intc->reg_pending);
+		writel_relaxed(pend, intc->reg_pending);
 		if (intc->reg_intpnd)
-			__raw_writel(pend, intc->reg_intpnd);
+			writel_relaxed(pend, intc->reg_intpnd);
 
 		pr_info("irq: clearing pending status %08x\n", (int)pend);
 		last = pend;
Signature · 1 line
2.8.1
author
#19 lore raw

PATCH v2 1/1 10/11] [V2] memory: samsung: endian fixes for IO

In reply to Ben Dooks

Use the relaxed versions of the IO accessors to avoid any issues if running in big endian.

Signed-off-by Ben Dooks <[email protected]>

---
V1..V2: Fix indentation changes
---
Cc: Pavel Fedin <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Pankaj Dubey <[email protected]>
Cc: linux-arm-kernel at lists.codethink.co.uk

---
 drivers/memory/samsung/exynos-srom.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
drivers/memory/samsung/exynos-srom.c +10 -10
index 96756fb..5714bdf 100644
@@ -91,17 +91,17 @@ static int exynos_srom_configure_bank(struct exynos_srom *srom,
 	if (width == 2)
 		cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
 
-	bw = __raw_readl(srom->reg_base + EXYNOS_SROM_BW);
+	bw = readl_relaxed(srom->reg_base + EXYNOS_SROM_BW);
 	bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
-	__raw_writel(bw, srom->reg_base + EXYNOS_SROM_BW);
-
-	__raw_writel(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
-		    (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
-		    (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
-		    (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
-		    (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
-		    (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
-		    srom->reg_base + EXYNOS_SROM_BC0 + bank);
+	writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
+
+	writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
+		       (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
+		       (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
+		       (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
+		       (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
+		       (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
+		       srom->reg_base + EXYNOS_SROM_BC0 + bank);
 
 	return 0;
 }
Signature · 1 line
2.8.1
author
#20 lore raw

PATCH v2 1/1 11/11] hwrng: exynos - fixup IO accesors

In reply to Ben Dooks

The __raw IO functions are not endian safe, so use the readl_relaxed and writel_relaxed versions of these.

Signed-off-by Ben Dooks <[email protected]>

---
CC: Matt Mackall <[email protected]>
CC: Krzysztof Kozlowski <[email protected]>
CC: linux-crypto at vger.kernel.org
CC: linux-arm-kernel at lists.infradead.org
CC: linux-samsung-soc at vger.kernel.org

---
 drivers/char/hw_random/exynos-rng.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/char/hw_random/exynos-rng.c +2 -2
index ed44561..23d3585 100644
@@ -45,12 +45,12 @@ struct exynos_rng {
 
 static u32 exynos_rng_readl(struct exynos_rng *rng, u32 offset)
 {
-	return	__raw_readl(rng->mem + offset);
+	return	readl_relaxed(rng->mem + offset);
 }
 
 static void exynos_rng_writel(struct exynos_rng *rng, u32 val, u32 offset)
 {
-	__raw_writel(val, rng->mem + offset);
+	writel_relaxed(val, rng->mem + offset);
 }
 
 static int exynos_rng_configure(struct exynos_rng *exynos_rng)
Signature · 1 line
2.8.1
maintainer
#21 lore raw

PATCH v2 1/1 11/11] hwrng: exynos - fixup IO accesors

Quoted 4 lines · Ben Dooks

The __raw IO functions are not endian safe, so use the readl_relaxed and writel_relaxed versions of these.

Signed-off-by Ben Dooks <[email protected]>

This patch has already been merged.

Cheers,

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
author
#22 lore raw

PATCH v2 1/1 11/11] hwrng: exynos - fixup IO accesors

Quoted 9 lines · Herbert Xu
Quoted 4 lines · Ben Dooks

The __raw IO functions are not endian safe, so use the readl_relaxed and writel_relaxed versions of these.

Signed-off-by Ben Dooks <[email protected]>

This patch has already been merged.

Cheers,

Apologies, only meant to repost the core patches.

Signature · 2 lines
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius