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STi SoC changes for v4.8

GIT PULL Patrice Chotard 2 participants 3 messages Jul 7, 2016 – Jul 11, 2016

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The following changes since commit 4c2e07c6a29e0129e975727b9f57eede813eea85:

Linux 4.7-rc5 (2016-06-26 17:52:03 -0700)

are available in the git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git
tags/sti-soc-for-v4.8

for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681:

ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44
+0200)

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Highlights:
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution, we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a more generic for the STi SoCs family

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Patrice Chotard (1):
ARM: sti: Implement dummy L2 cache's write_sec

Peter Griffin (1):
ARM: STi: Update machine _namestr to be more generic.

  arch/arm/mach-sti/board-dt.c | 11 ++++++++++-
  1 file changed, 10 insertions(+), 1 deletion(-)
#1 lore raw
Quoted 7 lines · CEST Patrice Chotard

Highlights:
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution, we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a more generic for the STi SoCs family

This is also based on -rc5, please send a third version rebased to -rc3 or earlier.

Arnd

#2 lore raw
Quoted 10 lines · Arnd Bergmann
Quoted 7 lines · CEST Patrice Chotard

Highlights:
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution, we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a more generic for the STi SoCs family

This is also based on -rc5, please send a third version rebased to -rc3 or earlier.

Hi Arnd

V3 will be send shortly

Thanks

Patrice

Quoted 2 lines

Arnd