mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"
PATCH 1/1 mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong. SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.
For example, Exynos didn't have CTRL_HISPD. But Highspeed mode is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)
Note: If driver didn't support the Highspeed Mode, use or add the other quirks.
After applied this patch, all Exynos SoCs are just running with 25MHz.
--- drivers/mmc/sdhci.c | 3 --- 1 file changed, 3 deletions(-)
drivers/mmc/sdhci.c +0 -3
@@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, cfg->host_caps |=MMC_MODE_8BIT ; } -if (quirks &SDHCI_QUIRK_NO_HISPD_BIT ) - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); -if (host_caps) cfg->host_caps |= host_caps;
Signature · 1 line
1.9.1
PATCH 1/1 mmc: sdhci: revert "mmc: sdhci: Claer high speed if not supported"
Hi All,
Quoted 11 lines · Jaehoon Chung
This "commit
429790026021d522d51617217d4b86218cca5750" is wrong.SDHCI_QUIRK_NO_HISPD_BITis for skipping to setCTRL_HISPDbit.For example, Exynos didn't have
CTRL_HISPD. But Highspeed mode is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)Note: If driver didn't support the Highspeed Mode, use or add the other quirks.
After applied this patch, all Exynos SoCs are just running with 25MHz.
SDHCI_QUIRK_NO_HISPD had added from me.
At that time, it meant the Controller doesn't have the SDHCI_CTRL_HISPD bit[2]. In exynos, this bit is using as OUTEDGINV (Output Egde Inversion). I added SDHCI_QUIRK_NO_HISPD to prevent wrong bit operation likes this.
And in drivers/mmc/mmc.c 1328 line,
mmc->card_caps &= mmc->cfg->host_caps;
After reading card's capabilities, if card didn't support those, then it's cleared. I don't know why cleared these capabilities before checking the card's capabilities.
After applied commit "42979002602"
Device: SAMSUNG SDHCI
Manufacturer ID: 3
OEM: 5344
Name: SU16G
Tran Speed: 25000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
After reverted commit "42979002602"
Device: SAMSUNG SDHCI
Manufacturer ID: 3
OEM: 5344
Name: SU16G
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
There is no purpose, it needs to revert for Other SoCs.
Best Regards,
Jaehoon Chung
Quoted 21 lines
Signed-off-by Jaehoon Chung <[email protected]>--- drivers/mmc/sdhci.c | 3 --- 1 file changed, 3 deletions(-)drivers/mmc/sdhci.c +0
-3@@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, cfg->host_caps |=MMC_MODE_8BIT ; } -if (quirks &SDHCI_QUIRK_NO_HISPD_BIT ) - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); -if (host_caps) cfg->host_caps |= host_caps;
Quoted 11 lines · Jaehoon Chung
This "commit
429790026021d522d51617217d4b86218cca5750" is wrong.SDHCI_QUIRK_NO_HISPD_BITis for skipping to setCTRL_HISPDbit.For example, Exynos didn't have
CTRL_HISPD. But Highspeed mode is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)Note: If driver didn't support the Highspeed Mode, use or add the other quirks.
After applied this patch, all Exynos SoCs are just running with 25MHz.
Applied on u-boot-mmc.
Best Regards,
Jaehoon Chung
Quoted 21 lines
Signed-off-by Jaehoon Chung <[email protected]>--- drivers/mmc/sdhci.c | 3 --- 1 file changed, 3 deletions(-)drivers/mmc/sdhci.c +0
-3@@ -553,9 +553,6 @@ int sdhci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, cfg->host_caps |=MMC_MODE_8BIT ; } -if (quirks &SDHCI_QUIRK_NO_HISPD_BIT ) - cfg->host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); -if (host_caps) cfg->host_caps |= host_caps;