ARM: Introduce function to switch to hypervisor mode

On SoCs like DRA7, OMAP5 one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader.

Patch 1: Introduces a weak function which can be overridden specific to SoCs to switch to hypervisor mode.

Patch 2: overrides weak function in patch 1 switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for hypervisor mode on OMAP5 based SoCs.

Changes in v2:

* Fixed a compile time error on older defconfigs due to #ifdef issue.

Boot tested on DRA7-EVM and DRA72-EVM.

Keerthy (2):
ARM: Introduce function to switch to hypervisor mode
ARM: OMAP5+: Override switch_to_hypervisor function

 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 21 +++++++++++++++++++++
 arch/arm/cpu/armv7/start.S                     | 15 +++++++++++++++
 arch/arm/include/asm/system.h                  |  1 +
 3 files changed, 37 insertions(+)

1.9.1

On some of the SoCs one cannot enable hypervisor mode directly from the u-boot because the ROM code puts the chip to supervisor mode after it jumps to boot loader. Hence introduce a weak function which can be overridden based on the SoC type and switch to hypervisor mode in a custom way.

---
 arch/arm/cpu/armv7/start.S    | 15 +++++++++++++++
 arch/arm/include/asm/system.h |  1 +
 2 files changed, 16 insertions(+)

index 691e5d3..4fb3d58 100644
@@ -17,6 +17,7 @@
 #include <config.h>
 #include <asm/system.h>
 #include <linux/linkage.h>
+#include <asm/armv7.h>
 
 /*************************************************************************
  *

@@ -30,11 +31,20 @@
 
 	.globl	reset
 	.globl	save_boot_params_ret
+	.global	switch_to_hypervisor_ret
 
 reset:
 	/* Allow the board to save important registers */
 	b	save_boot_params
 save_boot_params_ret:
+/*
+ * check for Hypervisor support
+ */
+	mrc	p15, 0, r0, c0, c1, 1		@ read ID_PFR1
+	and	r0, r0, #CPUID_ARM_VIRT_MASK	@ mask virtualization bits
+	cmp	r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+	beq	switch_to_hypervisor
+switch_to_hypervisor_ret:
 	/*
 	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 	 * except if in HYP mode already

@@ -103,6 +113,11 @@ ENTRY(save_boot_params)
 ENDPROC(save_boot_params)
 	.weak	save_boot_params
 
+ENTRY(switch_to_hypervisor)
+	b	switch_to_hypervisor_ret
+ENDPROC(switch_to_hypervisor)
+	.weak	switch_to_hypervisor
+
 /*************************************************************************
  *
  * cpu_init_cp15

index 2bdc0be..d1a95b0 100644
@@ -226,6 +226,7 @@ void __noreturn psci_system_reset(bool smc);
  * should use 'b' or 'bx' to return to save_boot_params_ret.
  */
 void save_boot_params_ret(void);
+void switch_to_hypervisor_ret(void);
 
 #define isb() __asm__ __volatile__ ("" : : : "memory")
 

1.9.1

Override the switch_to_hypervisor function to switch cpu to hypervisor mode using the available ROM code hook early in the boot phase before the boot loader checks for HYP mode.

Based on the work done by Jonathan Bergsagel jbergsagel at ti.com.

---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

index 66a3b3d..1026232 100644
@@ -24,6 +24,27 @@ ENTRY(save_boot_params)
 	str	r0, [r1]
 	b	save_boot_params_ret
 ENDPROC(save_boot_params)
+
+ENTRY(switch_to_hypervisor)
+/*
+ * Switch to hypervisor mode
+ */
+	adr	r0, save_sp
+	str	sp, [r0]
+	adr	r1, restore_from_hyp
+	ldr	r0, =0x102
+#ifdef CONFIG_TI_SECURE_DEVICE
+	b	omap_smc_sec
+#else
+	b	omap_smc1
+#endif
+restore_from_hyp:
+	adr	r0, save_sp
+	ldr	sp, [r0]
+	b	switch_to_hypervisor_ret
+save_sp:
+	.word	0x0
+ENDPROC(switch_to_hypervisor)
 #endif
 
 ENTRY(omap_smc1)

1.9.1

Hi Tom,

I request you to hold on merge of this series. I am doing some performance measurements. I see some drop. So analyzing and root causing.

Thanks,
Keerthy