arm: cache: always flush cache line size for page table

PATCH Superseded Stefan Agner 4 participants 6 messages Aug 7, 2016 – Aug 15, 2016 Arm (32-bit)

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Stefan Agner

author

2016-08-07 17:43 UTC #0 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

From: Stefan Agner <[email protected]>

The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.

Signed-off-by Stefan Agner <[email protected]>

Tested-by Fabio Estevam <[email protected]>

Reviewed-by Simon Glass <[email protected]>

---

Changes in v4:
- Fixed spelling misstake for real

Changes in v3:
- Fixed spelling misstake

Changes in v2:
- Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour

 arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

arch/arm/lib/cache-cp15.c +12 -1

index 1121dc3..488094e 100644
@@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	phys_addr_t startpt, stoppt;
 	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;

@@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 	      option);
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
-	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+	/*
+	 * Make sure range is cache line aligned
+	 * Only CPU maintains page tables, hence it is safe to always
+	 * flush complete cache lines...
+	 */
+	startpt = (phys_addr_t)&page_table[start];
+	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stoppt = (phys_addr_t)&page_table[end];
+	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+	mmu_page_table_flush(startpt, stoppt);
 }
 
 __weak void dram_bank_mmu_setup(int bank)

Signature · 1 line

2.9.0

Heiko Schocher

2016-08-08 04:22 UTC #1 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

Hello Stefan,

Am 07.08.2016 um 19:43 schrieb Stefan Agner:

Quoted 18 lines

From: Stefan Agner <[email protected]>
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by Stefan Agner <[email protected]>
Tested-by Fabio Estevam <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes in v4:
- Fixed spelling misstake for real
Changes in v3:
- Fixed spelling misstake

Quoted 6 lines

Changes in v2:
- Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour
  arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
  1 file changed, 12 insertions(+), 1 deletion(-)

Reviewed-by Heiko Schocher <[email protected]>

bye,
Heiko

Quoted 33 lines

arch/arm/lib/cache-cp15.c +12 -1

index 1121dc3..488094e 100644
@@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  				     enum dcache_option option)
  {
  	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	phys_addr_t startpt, stoppt;
  	unsigned long upto, end;
 
  	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;

@@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  	      option);
  	for (upto = start; upto < end; upto++)
  		set_section_dcache(upto, option);
-	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+	/*
+	 * Make sure range is cache line aligned
+	 * Only CPU maintains page tables, hence it is safe to always
+	 * flush complete cache lines...
+	 */
+	startpt = (phys_addr_t)&page_table[start];
+	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stoppt = (phys_addr_t)&page_table[end];
+	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+	mmu_page_table_flush(startpt, stoppt);
  }
 
  __weak void dram_bank_mmu_setup(int bank)

Signature · 2 lines

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Lokesh Vutla

2016-08-08 06:10 UTC #2 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

In reply to Stefan Agner

Hi,

Quoted 11 lines · Stefan Agner

From: Stefan Agner <[email protected]>
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by Stefan Agner <[email protected]>
Tested-by Fabio Estevam <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---

I get the following warning when CONFIG_PHYS_64BIT is enabled on arm platforms(dra7xx_evm_defconfig):

arch/arm/lib/cache-cp15.c: In function 'mmu_set_region_dcache_behaviour':
arch/arm/lib/cache-cp15.c:80:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

  startpt = (phys_addr_t)&page_table[start];
            ^
arch/arm/lib/cache-cp15.c:82:11: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  stoppt = (phys_addr_t)&page_table[end];
           ^
arch/arm/lib/cache-cp15.c: In function 'mmu_set_region_dcache_behaviour':
arch/arm/lib/cache-cp15.c:80:12: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  startpt = (phys_addr_t)&page_table[start];
            ^

arch/arm/lib/cache-cp15.c:82:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
stoppt = (phys_addr_t)&page_table[end];

Thanks and regards,
Lokesh

Quoted 46 lines

Changes in v4:
- Fixed spelling misstake for real

Changes in v3:
- Fixed spelling misstake

Changes in v2:
- Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour

 arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

arch/arm/lib/cache-cp15.c +12 -1

index 1121dc3..488094e 100644
@@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	phys_addr_t startpt, stoppt;
 	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;

@@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 	      option);
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
-	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+	/*
+	 * Make sure range is cache line aligned
+	 * Only CPU maintains page tables, hence it is safe to always
+	 * flush complete cache lines...
+	 */
+	startpt = (phys_addr_t)&page_table[start];
+	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stoppt = (phys_addr_t)&page_table[end];
+	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+	mmu_page_table_flush(startpt, stoppt);
 }
 
 __weak void dram_bank_mmu_setup(int bank)

Stefan Agner

author

2016-08-08 07:43 UTC #3 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

Quoted 10 lines · Lokesh Vutla

Hi,
Quoted 7 lines · Stefan Agner
From: Stefan Agner <[email protected]>
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.

Quoted 7 lines

Quoted 4 lines
Signed-off-by Stefan Agner <[email protected]>
Tested-by Fabio Estevam <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
I get the following warning when CONFIG_PHYS_64BIT is enabled on arm platforms(dra7xx_evm_defconfig):

Hm, do I see things right, this is otherwise a 32-bit architecture? Does that work without LPAE? What is the page table size in this case?

Quoted 6 lines

arch/arm/lib/cache-cp15.c: In function 'mmu_set_region_dcache_behaviour':
arch/arm/lib/cache-cp15.c:80:12: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
  startpt = (phys_addr_t)&page_table[start];
            ^

Hm, maybe we should keep using unsigned long then inside this function. Added Thierry to CC since he introduced phys_addr_t to the function signature.

--
Stefan

Quoted 62 lines

arch/arm/lib/cache-cp15.c:82:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

  stoppt = (phys_addr_t)&page_table[end];
           ^
arch/arm/lib/cache-cp15.c: In function 'mmu_set_region_dcache_behaviour':
arch/arm/lib/cache-cp15.c:80:12: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
  startpt = (phys_addr_t)&page_table[start];
            ^

arch/arm/lib/cache-cp15.c:82:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
stoppt = (phys_addr_t)&page_table[end];

Thanks and regards,
Lokesh

Quoted 46 lines

Changes in v4:
- Fixed spelling misstake for real

Changes in v3:
- Fixed spelling misstake

Changes in v2:
- Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour

 arch/arm/lib/cache-cp15.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

arch/arm/lib/cache-cp15.c +12 -1

index 1121dc3..488094e 100644
@@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+	phys_addr_t startpt, stoppt;
 	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;

@@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 	      option);
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
-	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+	/*
+	 * Make sure range is cache line aligned
+	 * Only CPU maintains page tables, hence it is safe to always
+	 * flush complete cache lines...
+	 */
+	startpt = (phys_addr_t)&page_table[start];
+	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stoppt = (phys_addr_t)&page_table[end];
+	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+	mmu_page_table_flush(startpt, stoppt);
 }
 
 __weak void dram_bank_mmu_setup(int bank)

Tom Rini

2016-08-14 20:01 UTC #4 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

Quoted 16 lines · Stefan Agner

Quoted 15 lines · Lokesh Vutla
Hi,
Quoted 11 lines · Stefan Agner
From: Stefan Agner <[email protected]>
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by Stefan Agner <[email protected]>
Tested-by Fabio Estevam <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---

Quoted 5 lines

Quoted 2 lines
I get the following warning when CONFIG_PHYS_64BIT is enabled on arm platforms(dra7xx_evm_defconfig):
Hm, do I see things right, this is otherwise a 32-bit architecture? Does that work without LPAE? What is the page table size in this case?

It's a 32bit architecture with LPAE, iirc, yes.

Signature · 8 lines

Tom
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Stefan Agner

author

2016-08-15 03:44 UTC #5 lore raw

PATCH v4 1/1 arm: cache: always flush cache line size for page table

Quoted 17 lines · Tom Rini

Quoted 16 lines · Stefan Agner
Quoted 15 lines · Lokesh Vutla
Hi,
Quoted 11 lines · Stefan Agner
From: Stefan Agner <[email protected]>
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by Stefan Agner <[email protected]>
Tested-by Fabio Estevam <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
I get the following warning when CONFIG_PHYS_64BIT is enabled on arm platforms(dra7xx_evm_defconfig):
Hm, do I see things right, this is otherwise a 32-bit architecture? Does that work without LPAE? What is the page table size in this case?
It's a 32bit architecture with LPAE, iirc, yes.

Hm, when looking at other functions such as set_section_dcache, page_table is casted to a u64* type, hence I guess this is wrong in mmu_set_region_dcache_behaviour. In fact, that makes it seem unsafe to use this function as is...

--
Stefan