ARM: Move SYS_CACHELINE_SIZE over to Kconfig

Hi Tom,

Quoted 8 lines

arch/arm/Kconfig +0 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
        default 4 if CPU_SA1100
        default 8 if ARM64
 

arch/arm/Kconfig config SYS_ARM_ARCH · line 84

Quoted 3 lines

arch/arm/Kconfig +3 -0

+config SYS_CACHELINE_SIZE
+       int
+       default 64 if CPU_V7 || ARM64

arch/arm/Kconfig config SYS_ARM_ARCH · line 86

Quoted 2 lines

arch/arm/Kconfig +2 -0

+       default 32
+

I do not like this very much.

Next, I would need to change it to

config SYS_CACHELINE_SIZE
int
+ default 128 if CACHE_UNIPHIER

      default 64 if CPU_V7 || ARM64
      default 32

but I do not want to dirty the common place
with my SoC-specific stuff.

Instead, can we have this part look like as follows?

config CACHE_SHIFT_7
bool

config CACHE_SHIFT_6
bool

config SYS_CACHELINE_SIZE
int
default 128 if CACHE_SHIFT_7
default 64 if CACHE_SHIFT_6
default 32

Then, my config option can select 'CACHE_SHIFT_7'.

config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller" depends on ARCH_UNIPHIER_32BIT
+ select CACHE_SHIFT_7
default y

This idea was borrowed from Linux.
(you can grep "_L1_CACHE_SHIFT" in Linux Kconfig files.)

Quoted 12 lines

Hi Tom,

Quoted 8 lines

arch/arm/Kconfig +0 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
        default 4 if CPU_SA1100
        default 8 if ARM64
 

Quoted 3 lines

arch/arm/Kconfig config SYS_ARM_ARCH · line 84

Quoted 3 lines

arch/arm/Kconfig +3 -0

+config SYS_CACHELINE_SIZE
+       int
+       default 64 if CPU_V7 || ARM64

Note! I had a brain fart here last night and used 'printf %x' when I thought I was doing 'printf %d', so, no, ARM64 should get moved up to shift 7 / 128 bytes.

Quoted 5 lines

This idea was borrowed from Linux.
(you can grep "_L1_CACHE_SHIFT" in Linux Kconfig files.)

I'm agreeable to moving over to shift to more obviously align with the Linux Kernel (and it will make other arches easier to migrate too). But the UniPhier case currently looks to me like it's overloading what CONFIG_SYS_CACHELINE_SIZE is doing,

ie in the Linux Kernel it's not
setting the shift to 7, in 32bit. Or is this a 64bit only feature? Thanks!

Hi Tom,

2016-08-22 0:43 GMT+09:00 Tom Rini <[email protected]>:

Quoted 13 lines · Masahiro Yamada

Quoted 12 lines

Hi Tom,

Quoted 8 lines

arch/arm/Kconfig +0 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
        default 4 if CPU_SA1100
        default 8 if ARM64
 

Quoted 7 lines

Quoted 3 lines

arch/arm/Kconfig config SYS_ARM_ARCH · line 84

Quoted 3 lines

arch/arm/Kconfig +3 -0

+config SYS_CACHELINE_SIZE
+       int
+       default 64 if CPU_V7 || ARM64

Note! I had a brain fart here last night and used 'printf %x' when I thought I was doing 'printf %d', so, no, ARM64 should get moved up to shift 7 / 128 bytes.

As far as I know, the line size of the cores from ARM Ltd. (CA-53, 57, 72) is 64 byte.

ARM64 Linux increased the line size up to 128 byte for the Cavium's core because it is multi-platform.

------------------------------>8--------------------------------------

commit 97303480753e48fb313dc0e15daaf11b0451cdb8

Author: Tirumalesh Chalamarla <[email protected]>
Date:   Tue Sep 22 19:59:48 2015 +0200

arm64: Increase the max granular size

Increase the standard cacheline size to avoid having locks in the same cacheline.

Cavium's ThunderX core implements cache lines of 128 byte size. With current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could share the same cache line leading a performance degradation. Increasing the size fixes that.

Increasing the size has no negative impact to cache invalidation on systems with a smaller cache line. There is an impact on memory usage, but that's not too important for arm64 use cases.

Signed-off-by Tirumalesh Chalamarla <[email protected]>

Signed-off-by Robert Richter <[email protected]>

Acked-by Timur Tabi <[email protected]>

Signed-off-by Catalin Marinas <[email protected]>

arch/arm64/include/asm/cache.h +1 -2

index bde4499..5082b30 100644
@@ -18,7 +18,7 @@
 
 #include <asm/cachetype.h>
 
-#define L1_CACHE_SHIFT         6
+#define L1_CACHE_SHIFT         7
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
 /*
 
--------------------------------------8<-------------------------------------

U-Boot does not adopt multi-platform,
so we can make the ARCH_THUNDERX select CACHESHIFT_7 and allow other ARM64 SoCs to stay at CACHESHIFT_6. Just my 2 cents.

Quoted 7 lines

Quoted 2 lines

This idea was borrowed from Linux.
(you can grep "_L1_CACHE_SHIFT" in Linux Kconfig files.)

I'm agreeable to moving over to shift to more obviously align with the Linux Kernel (and it will make other arches easier to migrate too). But the UniPhier case currently looks to me like it's overloading what CONFIG_SYS_CACHELINE_SIZE is doing,

First, I'd like to know if CONFIG_SYS_CACHELINE_SIZE means the line size of L1 cache,
or the largest line size across all the cache levels.

Quoted 3 lines

ie in the Linux Kernel it's not
setting the shift to 7, in 32bit. Or is this a 64bit only feature? Thanks!

CACHE_UNIPHIER is a full-custom outer cache
only implemented in its 32bit SoC lineup.

UniPhier (32bit) is a very unfortunate case
where outer-cache has a different line size
than the L1 line size.

L1  (ARM native, inner):     32byte line (shift 5)
L2  (UniPhier outer cache):  128byte line (shift 7)

For Linux, it is just not upstreamed yet.

If you are interested, check the following:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/400289.html

If I set the shift to 7, it would affect all the other SoCs in multi_v7_defconfig,
which other vendors would probably be unhappy about.

Again, it is no problem in U-Boot, which is not multi-platform.

Good question. This I think ends up being a historical ambiguity. My poking around in git log suggests that when CFG_SYS_CACHELINE_SIZE was added it was implicitly L1. ...

Quoted 76 lines

Hi Tom,

2016-08-22 0:43 GMT+09:00 Tom Rini <[email protected]>:

Quoted 13 lines · Masahiro Yamada

Quoted 12 lines

Hi Tom,

Quoted 8 lines

arch/arm/Kconfig +0 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
        default 4 if CPU_SA1100
        default 8 if ARM64
 

Quoted 7 lines

Quoted 3 lines

arch/arm/Kconfig config SYS_ARM_ARCH · line 84

Quoted 3 lines

arch/arm/Kconfig +3 -0

+config SYS_CACHELINE_SIZE
+       int
+       default 64 if CPU_V7 || ARM64

Note! I had a brain fart here last night and used 'printf %x' when I thought I was doing 'printf %d', so, no, ARM64 should get moved up to shift 7 / 128 bytes.

As far as I know, the line size of the cores from ARM Ltd. (CA-53, 57, 72) is 64 byte.

ARM64 Linux increased the line size up to 128 byte for the Cavium's core because it is multi-platform.

------------------------------>8--------------------------------------

commit 97303480753e48fb313dc0e15daaf11b0451cdb8

Author: Tirumalesh Chalamarla <[email protected]>
Date:   Tue Sep 22 19:59:48 2015 +0200

arm64: Increase the max granular size

Increase the standard cacheline size to avoid having locks in the same cacheline.

Cavium's ThunderX core implements cache lines of 128 byte size. With current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could share the same cache line leading a performance degradation. Increasing the size fixes that.

Increasing the size has no negative impact to cache invalidation on systems with a smaller cache line. There is an impact on memory usage, but that's not too important for arm64 use cases.

Signed-off-by Tirumalesh Chalamarla <[email protected]>

Signed-off-by Robert Richter <[email protected]>

Acked-by Timur Tabi <[email protected]>

Signed-off-by Catalin Marinas <[email protected]>

arch/arm64/include/asm/cache.h +1 -2

index bde4499..5082b30 100644
@@ -18,7 +18,7 @@
 
 #include <asm/cachetype.h>
 
-#define L1_CACHE_SHIFT         6
+#define L1_CACHE_SHIFT         7
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
 /*
 
--------------------------------------8<-------------------------------------

Quoted 4 lines

U-Boot does not adopt multi-platform,
so we can make the ARCH_THUNDERX select CACHESHIFT_7 and allow other ARM64 SoCs to stay at CACHESHIFT_6. Just my 2 cents.

OK, good point, thanks!

Quoted 11 lines

Quoted 7 lines

Quoted 2 lines

This idea was borrowed from Linux.
(you can grep "_L1_CACHE_SHIFT" in Linux Kconfig files.)

I'm agreeable to moving over to shift to more obviously align with the Linux Kernel (and it will make other arches easier to migrate too). But the UniPhier case currently looks to me like it's overloading what CONFIG_SYS_CACHELINE_SIZE is doing,

First, I'd like to know if CONFIG_SYS_CACHELINE_SIZE means the line size of L1 cache,
or the largest line size across all the cache levels.

Good question. This I think ends up being a historical ambiguity. My poking around in git log suggests that when CFG_SYS_CACHELINE_SIZE was added it was implicitly L1. It's gone on to mean "cache alignment required for DMA". It is often defined as L1 and only occasionally defined differently. Presumably because it needs to be higher on those systems for DMA/etc. In sum, I remove my objection to UniPhier maybe overloading something that it shouldn't, it's doing the right thing.

Quoted 25 lines

Quoted 3 lines

ie in the Linux Kernel it's not
setting the shift to 7, in 32bit. Or is this a 64bit only feature? Thanks!

CACHE_UNIPHIER is a full-custom outer cache
only implemented in its 32bit SoC lineup.

UniPhier (32bit) is a very unfortunate case
where outer-cache has a different line size
than the L1 line size.

L1  (ARM native, inner):     32byte line (shift 5)
L2  (UniPhier outer cache):  128byte line (shift 7)

For Linux, it is just not upstreamed yet.

If you are interested, check the following:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/400289.html

Quoted 5 lines

If I set the shift to 7, it would affect all the other SoCs in multi_v7_defconfig,
which other vendors would probably be unhappy about.

Again, it is no problem in U-Boot, which is not multi-platform.

Ah, OK. So then the question is, are we OK with things like the following in the .config file:
CONFIG_SYS_CACHE_SHIFT_6=y
CONFIG_SYS_CACHE_SHIFT_7=y CONFIG_SYS_CACHELINE_SIZE=128

?

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes. Second, we say ARM64 uses 64 bytes not 80 (as found in the Linux Kernel) due to how we use it for forcing alignment from the compiler. Our other option here would be to move up to 128 bytes but as no processors yet use 80 bytes, we'll revisit this logic as needed later.

Finally, it is possible that Uniphier will need to adjust ARCH_DMA_MINALIGN in the case of CACHE_UNIPHIER being enabled as previously it moves ARCH_DMA_MINALIGN up to 128 bytes

Cc Albert Aribaud <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Nagendra T S <[email protected]>

Cc Vaibhav Hiremath <[email protected]>

Cc Lokesh Vutla <[email protected]>

Cc Steve Rae <[email protected]>

Cc Igor Grinberg <[email protected]>

Cc Nikita Kiryanov <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Heiko Schocher <[email protected]>

Cc Mateusz Kulikowski <[email protected]>

Cc Peter Griffin <[email protected]>

Cc Paul Kocialkowski <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Cc "Pali Roh?r" <[email protected]>

Cc Adam Ford <[email protected]>

Cc Steve Sakoman <[email protected]>

Cc Grazvydas Ignotas <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Robert Baldyga <[email protected]>

Cc Minkyu Kang <[email protected]>

Cc Thomas Weber <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc David Feng <[email protected]>

Cc Alison Wang <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

Cc York Sun <[email protected]>

Cc Shengzhou Liu <[email protected]>

Cc Mingkai Hu <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Aneesh Bansal <[email protected]>

Cc Saksham Jain <[email protected]>

Cc Qianyu Gong <[email protected]>

Cc Wang Dongsheng <[email protected]>

Cc Alex Porosanu <[email protected]>

Cc Hongbo Zhang <[email protected]>

Cc tang yuantian <[email protected]>

Cc Rajesh Bhagat <[email protected]>

Cc Josh Wu <[email protected]>

Cc Bo Shen <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Hannes Schmelzer <[email protected]>

Cc Thomas Chou <[email protected]>

Cc Joe Hershberger <[email protected]>

Cc Sam Protsenko <[email protected]>

Cc Bin Meng <[email protected]>

Cc Christophe Ricard <[email protected]>

Cc Anand Moon <[email protected]>

Cc Beniamino Galvani <[email protected]>

Cc Carlo Caione <[email protected]>

Cc huang lin <[email protected]>

Cc Sjoerd Simons <[email protected]>

Cc Xu Ziyuan <[email protected]>

Cc "jk.kernel at gmail.com" <[email protected]>

Cc "Ariel D'Alessandro" <[email protected]>

Cc Kever Yang <[email protected]>

Cc Samuel Egli <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Hans de Goede <[email protected]>

Cc Ian Campbell <[email protected]>

Cc Siarhei Siamashka <[email protected]>

Cc Boris Brezillon <[email protected]>

Cc Andre Przywara <[email protected]>

Cc Bernhard Nortmann <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Ben Whitten <[email protected]>

Cc Tom Warren <[email protected]>

Cc Alexander Graf <[email protected]>

Cc Sekhar Nori <[email protected]>

Cc Vitaly Andrianov <[email protected]>

Cc "Andrew F. Davis" <[email protected]>

Cc Murali Karicheri <[email protected]>

Cc Carlos Hernandez <[email protected]>

Cc Ladislav Michl <[email protected]>

Cc Ash Charles <[email protected]>

Cc Mugunthan V N <[email protected]>

Cc Daniel Allred <[email protected]>

Cc Gong Qianyu <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/Kconfig                                  |  5 +++++

 include/configs/am3517_crane.h                    |  2 --
 include/configs/am3517_evm.h                      |  2 --
 include/configs/am43xx_evm.h                      |  2 --

 include/configs/omap3_beagle.h                    |  2 --
 include/configs/omap3_cairo.h                     |  2 --
 include/configs/omap3_evm.h                       |  2 --
 include/configs/omap3_logic.h                     |  1 -
 include/configs/omap3_overo.h                     |  1 -
 include/configs/omap3_pandora.h                   |  2 --
 include/configs/omap3_zoom1.h                     |  2 --

 include/configs/ti_am335x_common.h                |  1 -
 include/configs/ti_armv7_keystone2.h              |  1 -
 include/configs/ti_omap3_common.h                 |  2 --
 include/configs/ti_omap4_common.h                 |  1 -
 include/configs/ti_omap5_common.h                 |  2 --

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes. Second, we say ARM64 uses 64 bytes not 80 (as found in the Linux Kernel) due to how we use it for forcing alignment from the compiler. Our other option here would be to move up to 128 bytes but as no processors yet use 80 bytes, we'll revisit this logic as needed later.

Finally, it is possible that Uniphier will need to adjust ARCH_DMA_MINALIGN in the case of CACHE_UNIPHIER being enabled as previously it moves ARCH_DMA_MINALIGN up to 128 bytes

Cc Albert Aribaud <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Nagendra T S <[email protected]>

Cc Vaibhav Hiremath <[email protected]>

Cc Lokesh Vutla <[email protected]>

Cc Steve Rae <[email protected]>

Cc Igor Grinberg <[email protected]>

Cc Nikita Kiryanov <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Heiko Schocher <[email protected]>

Cc Mateusz Kulikowski <[email protected]>

Cc Peter Griffin <[email protected]>

Cc Paul Kocialkowski <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Cc "Pali Roh?r" <[email protected]>

Cc Adam Ford <[email protected]>

Cc Steve Sakoman <[email protected]>

Cc Grazvydas Ignotas <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Robert Baldyga <[email protected]>

Cc Minkyu Kang <[email protected]>

Cc Thomas Weber <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc David Feng <[email protected]>

Cc Alison Wang <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

Cc York Sun <[email protected]>

Cc Shengzhou Liu <[email protected]>

Cc Mingkai Hu <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Aneesh Bansal <[email protected]>

Cc Saksham Jain <[email protected]>

Cc Qianyu Gong <[email protected]>

Cc Wang Dongsheng <[email protected]>

Cc Alex Porosanu <[email protected]>

Cc Hongbo Zhang <[email protected]>

Cc tang yuantian <[email protected]>

Cc Rajesh Bhagat <[email protected]>

Cc Josh Wu <[email protected]>

Cc Bo Shen <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Hannes Schmelzer <[email protected]>

Cc Thomas Chou <[email protected]>

Cc Joe Hershberger <[email protected]>

Cc Sam Protsenko <[email protected]>

Cc Bin Meng <[email protected]>

Cc Christophe Ricard <[email protected]>

Cc Anand Moon <[email protected]>

Cc Beniamino Galvani <[email protected]>

Cc Carlo Caione <[email protected]>

Cc huang lin <[email protected]>

Cc Sjoerd Simons <[email protected]>

Cc Xu Ziyuan <[email protected]>

Cc "jk.kernel at gmail.com" <[email protected]>

Cc "Ariel D'Alessandro" <[email protected]>

Cc Kever Yang <[email protected]>

Cc Samuel Egli <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Hans de Goede <[email protected]>

Cc Ian Campbell <[email protected]>

Cc Siarhei Siamashka <[email protected]>

Cc Boris Brezillon <[email protected]>

Cc Andre Przywara <[email protected]>

Cc Bernhard Nortmann <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Ben Whitten <[email protected]>

Cc Tom Warren <[email protected]>

Cc Alexander Graf <[email protected]>

Cc Sekhar Nori <[email protected]>

Cc Vitaly Andrianov <[email protected]>

Cc "Andrew F. Davis" <[email protected]>

Cc Murali Karicheri <[email protected]>

Cc Carlos Hernandez <[email protected]>

Cc Ladislav Michl <[email protected]>

Cc Ash Charles <[email protected]>

Cc Mugunthan V N <[email protected]>

Cc Daniel Allred <[email protected]>

Cc Gong Qianyu <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
  arch/arm/Kconfig                                  |  5 +++++
  arch/arm/cpu/arm11/cpu.c                          |  5 -----
  arch/arm/cpu/arm926ejs/cache.c                    |  5 -----
  arch/arm/cpu/pxa/cache.c                          |  5 -----
  arch/arm/include/asm/arch-armada100/config.h      |  2 --
  arch/arm/include/asm/arch-fsl-layerscape/config.h |  2 --
  arch/arm/include/asm/arch-ls102xa/config.h        |  2 --
  arch/arm/include/asm/arch-mx5/imx-regs.h          |  2 --
  arch/arm/include/asm/arch-mx6/imx-regs.h          |  6 ------
  arch/arm/include/asm/arch-mx7/imx-regs.h          |  2 --
  arch/arm/include/asm/cache.h                      | 10 +++-------
  arch/arm/lib/cache.c                              |  4 ----
  arch/arm/mach-kirkwood/include/mach/config.h      |  2 --
  arch/arm/mach-mvebu/include/mach/config.h         |  2 --
  include/configs/am3517_crane.h                    |  2 --
  include/configs/am3517_evm.h                      |  2 --
  include/configs/am43xx_evm.h                      |  2 --
  include/configs/at91-sama5_common.h               |  2 --
  include/configs/bcm23550_w1d.h                    |  1 -
  include/configs/bcm28155_ap.h                     |  1 -
  include/configs/bcm_ep_board.h                    |  2 --
  include/configs/bur_am335x_common.h               |  1 -
  include/configs/cm_t3517.h                        |  3 ---
  include/configs/cm_t43.h                          |  1 -
  include/configs/colibri_vf.h                      |  4 ----
  include/configs/corvus.h                          |  1 -
  include/configs/dragonboard410c.h                 |  2 --
  include/configs/exynos4-common.h                  |  1 -
  include/configs/exynos5-common.h                  |  1 -
  include/configs/flea3.h                           |  1 -
  include/configs/hikey.h                           |  1 -
  include/configs/kc1.h                             |  1 -
  include/configs/kzm9g.h                           |  2 --
  include/configs/mcx.h                             |  2 --
  include/configs/meson-gxbb-common.h               |  1 -
  include/configs/nokia_rx51.h                      |  2 --
  include/configs/omap3_beagle.h                    |  2 --
  include/configs/omap3_cairo.h                     |  2 --
  include/configs/omap3_evm.h                       |  2 --
  include/configs/omap3_logic.h                     |  1 -
  include/configs/omap3_overo.h                     |  1 -
  include/configs/omap3_pandora.h                   |  2 --
  include/configs/omap3_zoom1.h                     |  2 --
  include/configs/pcm052.h                          |  2 --
  include/configs/rcar-gen2-common.h                |  2 --
  include/configs/rk3036_common.h                   |  2 --
  include/configs/rk3288_common.h                   |  2 --
  include/configs/rk3399_common.h                   |  2 --
  include/configs/rpi.h                             |  6 ------
  include/configs/s5p_goni.h                        |  4 ----
  include/configs/siemens-am33x-common.h            |  2 --
  include/configs/smartweb.h                        |  2 --
  include/configs/smdkc100.h                        |  2 --
  include/configs/sniper.h                          |  2 --
  include/configs/socfpga_common.h                  |  1 -
  include/configs/sunxi-common.h                    |  1 -
  include/configs/tam3517-common.h                  |  2 --
  include/configs/tao3530.h                         |  2 --
  include/configs/taurus.h                          |  2 --
  include/configs/tegra114-common.h                 |  1 -
  include/configs/tegra124-common.h                 |  1 -
  include/configs/tegra186-common.h                 |  1 -
  include/configs/tegra20-common.h                  |  1 -
  include/configs/tegra210-common.h                 |  1 -
  include/configs/tegra30-common.h                  |  1 -
  include/configs/ti814x_evm.h                      |  2 --
  include/configs/ti816x_evm.h                      |  2 --
  include/configs/ti_am335x_common.h                |  1 -
  include/configs/ti_armv7_keystone2.h              |  1 -
  include/configs/ti_omap3_common.h                 |  2 --
  include/configs/ti_omap4_common.h                 |  1 -
  include/configs/ti_omap5_common.h                 |  2 --
  include/configs/tricorder.h                       |  2 --
  include/configs/uniphier.h                        |  6 ------
  include/configs/vexpress_aemv8a.h                 |  1 -
  include/configs/vexpress_common.h                 |  2 --
  include/configs/vf610twr.h                        |  2 --
  include/configs/woodburn_common.h                 |  1 -
  include/configs/xilinx_zynqmp.h                   |  1 -
  include/configs/zynq-common.h                     |  1 -
  80 files changed, 8 insertions(+), 163 deletions(-)

arch/arm/Kconfig +5 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
  	default 4 if CPU_SA1100
  	default 8 if ARM64
 
+config SYS_CACHELINE_SIZE
+	int
+	default 64 if CPU_V7 || ARM64
+	default 32
+
  config SEMIHOSTING
  	bool "support boot from semihosting"
  	help

arch/arm/cpu/arm11/cpu.c +0 -5

index 7244c2e..ef32c3f 100644
@@ -53,11 +53,6 @@ static void cache_flush(void)
  }
 
  #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
  void invalidate_dcache_all(void)
  {
  	asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

arch/arm/cpu/arm926ejs/cache.c +0 -5

index 2119382..02cb24c 100644
@@ -8,11 +8,6 @@
  #include <common.h>
 
  #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
  void invalidate_dcache_all(void)
  {
  	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));

arch/arm/cpu/pxa/cache.c +0 -5

index 7aba112..d26354e 100644
@@ -8,11 +8,6 @@
  #include <common.h>
 
  #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
  void invalidate_dcache_all(void)
  {
  	/* Flush/Invalidate I cache */

arch/arm/include/asm/arch-armada100/config.h +0 -2

index e062da1..6ebc759 100644
@@ -16,8 +16,6 @@
  #define _ARMD1_CONFIG_H
 
  #include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE       32
 
  #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
  #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */

arch/arm/include/asm/arch-fsl-layerscape/config.h +0 -2

index b0ad4b4..5279981 100644
@@ -36,7 +36,6 @@
  #define CONFIG_SYS_FSL_SRDS_1
  #define CONFIG_SYS_FSL_SRDS_2
  #define CONFIG_SYS_PAGE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #ifndef L1_CACHE_BYTES
  #define L1_CACHE_SHIFT		6
  #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)

@@ -150,7 +149,6 @@
 
  #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
  #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE		64
  #define CONFIG_NUM_DDR_CONTROLLERS		1
  #define CONFIG_SYS_FSL_SEC_COMPAT		5
  #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */

arch/arm/include/asm/arch-ls102xa/config.h +0 -2

index d408fe4..56d8f32 100644
@@ -7,8 +7,6 @@
  #ifndef _ASM_ARMV7_LS102XA_CONFIG_
  #define _ASM_ARMV7_LS102XA_CONFIG_
 
-#define CONFIG_SYS_CACHELINE_SIZE		64
-
  #define OCRAM_BASE_ADDR				0x10000000
  #define OCRAM_SIZE				0x00010000
  #define OCRAM_BASE_S_ADDR			0x10010000

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -2

index e73cc07..3e79fa3 100644
@@ -9,8 +9,6 @@
 
  #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
  #if defined(CONFIG_MX51)
  #define IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
  #define IPU_SOC_BASE_ADDR	0x40000000

arch/arm/include/asm/arch-mx6/imx-regs.h +0 -6

index ac37e4f..53bf054 100644
@@ -9,12 +9,6 @@
 
  #define ARCH_MXC
 
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE	64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
  #define ROMCP_ARB_BASE_ADDR             0x00000000
  #define ROMCP_ARB_END_ADDR              0x000FFFFF
 

arch/arm/include/asm/arch-mx7/imx-regs.h +0 -2

index 74917f0..d33be31 100644
@@ -9,8 +9,6 @@
 
  #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define ROM_SW_INFO_ADDR                0x000001E8
  #define ROMCP_ARB_BASE_ADDR             0x00000000
  #define ROMCP_ARB_END_ADDR              0x00017FFF

arch/arm/include/asm/cache.h +3 -7

index 16e65c3..8ec81c6 100644
@@ -43,14 +43,10 @@ void dram_bank_mmu_setup(int bank);
  #endif
 
  /*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the L1 data cache shall be set for us in
+ * CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be higher than what the
+ * particular core uses, but this is OK to use in terms of alignment.
   */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
  #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	64
-#endif
 
  #endif /* _ASM_CACHE_H */

arch/arm/lib/cache.c +0 -4

index d330b09..4f72f89 100644
@@ -10,10 +10,6 @@
  #include <common.h>
  #include <malloc.h>
 
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
  /*
   * Flush range from all levels of d-cache/unified-cache.
   * Affects the range [start, start + size - 1].

arch/arm/mach-kirkwood/include/mach/config.h +0 -2

index 60b60aa..446457f 100644
@@ -24,8 +24,6 @@
  #endif /* CONFIG_KW88F6281 */
 
  #include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE	32
-				/* default Dcache Line length for kirkwood */
  #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
  #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
  #define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */

arch/arm/mach-mvebu/include/mach/config.h +0 -2

index 4df70d7..1b35e08 100644
@@ -26,8 +26,6 @@
  #define MV88F78X60 /* for the DDR training bin_hdr code */
  #endif
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #define CONFIG_SYS_L2_PL310
 
  #ifdef CONFIG_SPL_BUILD

include/configs/am3517_crane.h +0 -2

index a65d1a8..30c4278 100644
@@ -13,8 +13,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /*
   * High Level Configuration Options
   */

include/configs/am3517_evm.h +0 -2

index 4d88aac..ef4a8ba 100644
@@ -18,8 +18,6 @@
  #define CONFIG_OMAP
  #define CONFIG_OMAP_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_SYS_NO_FLASH
 
  #define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */

include/configs/am43xx_evm.h +0 -2

index 0467953..518b904 100644
@@ -11,7 +11,6 @@
 
  #define CONFIG_BOARD_LATE_INIT
  #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       32
  #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 21)	/* 2GB */
  #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 

@@ -49,7 +48,6 @@
  /* Enabling L2 Cache */
  #define CONFIG_SYS_L2_PL310
  #define CONFIG_SYS_PL310_BASE	0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /*
   * Since SPL did pll and ddr initialization for us,

include/configs/at91-sama5_common.h +0 -2

index 9257c5f..051186d 100644
@@ -12,8 +12,6 @@
 
  #include <asm/hardware.h>
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #define CONFIG_SYS_TEXT_BASE		0x26f00000
 
  /* ARM asynchronous clock */

include/configs/bcm23550_w1d.h +0 -1

index 770dd87..b968801 100644
@@ -127,7 +127,6 @@
  /* Commands */
  #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #undef CONFIG_USB_GADGET_VBUS_DRAW
  #define CONFIG_USB_GADGET_VBUS_DRAW	0
  #define CONFIG_USBID_ADDR		0x34052c46

include/configs/bcm28155_ap.h +0 -1

index df0b2ba..f38f081 100644
@@ -126,7 +126,6 @@
  /* Commands */
  #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #define CONFIG_USBID_ADDR		0x34052c46
 
  #endif /* __BCM28155_AP_H */

include/configs/bcm_ep_board.h +0 -2

index 50cd743..b5e5029 100644
@@ -11,8 +11,6 @@
 
  #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /*
   * Memory configuration
   * (these must be defined elsewhere)

include/configs/bur_am335x_common.h +0 -1

index a94b1e2..04da877 100644
@@ -15,7 +15,6 @@
  #define CONFIG_AM33XX
  #define CONFIG_OMAP
  #define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 
  /* Timer information */

include/configs/cm_t3517.h +0 -3

index ea9983b..a89ccb7 100644
@@ -10,8 +10,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /*
   * High Level Configuration Options
   */

@@ -30,7 +28,6 @@
   * Although the default iss 64, we still define it
   * to be on the safe side once the default is changed.
   */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 

include/configs/cm_t43.h +0 -1

index 5d94f13..b896d4d 100644
@@ -79,7 +79,6 @@
  /* Enabling L2 Cache */
  #define CONFIG_SYS_L2_PL310
  #define CONFIG_SYS_PL310_BASE		0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /*
   * Since SPL did pll and ddr initialization for us,

include/configs/colibri_vf.h +0 -4

index 5892595..fb68e59 100644
@@ -12,8 +12,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #include <asm/arch/imx-regs.h>
 
  #define CONFIG_VF610

@@ -207,8 +205,6 @@
 
  #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
  /* USB Host Support */
  #define CONFIG_USB_EHCI
  #define CONFIG_USB_EHCI_VF

include/configs/corvus.h +0 -1

index 28ea15b..746475d 100644
@@ -118,7 +118,6 @@
  #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
  #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
-#define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
  #define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6
 
  /* bootstrap + u-boot + env in nandflash */

include/configs/dragonboard410c.h +0 -2

index 1dbe219..cc7ab83 100644
@@ -27,8 +27,6 @@
  #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)
  #define CONFIG_SYS_BOOTM_LEN		0x1000000 /* 16MB max kernel size */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* UART */
  #define CONFIG_BAUDRATE			115200
 

include/configs/exynos4-common.h +0 -1

index fbe0fa9..fdbaf02 100644
@@ -15,7 +15,6 @@
 
  #define CONFIG_BOARD_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
  #define CONFIG_REVISION_TAG
 
  /* SD/MMC configuration */

include/configs/exynos5-common.h +0 -1

index f2ed798..1538787 100644
@@ -13,7 +13,6 @@
 
  #include "exynos-common.h"
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #define CONFIG_EXYNOS_SPL
 
  #ifdef FTRACE

include/configs/flea3.h +0 -1

index 824aca4..e84803d 100644
@@ -19,7 +19,6 @@
  #define CONFIG_MX35
 
  #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  #define CONFIG_DISPLAY_CPUINFO
 

include/configs/hikey.h +0 -1

index ffcc4d2..142326c 100644
@@ -22,7 +22,6 @@
  #define CONFIG_SUPPORT_RAW_INITRD
 
  /* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  #define CONFIG_IDENT_STRING		"hikey"
 

include/configs/kc1.h +0 -1

index b08cf21..8b95799 100644
@@ -24,7 +24,6 @@
 
  #define CONFIG_SYS_L2_PL310		1
  #define CONFIG_SYS_PL310_BASE		0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /*
   * Platform

include/configs/kzm9g.h +0 -2

index 94f3516..a4b296a 100644
@@ -10,8 +10,6 @@
 
  #undef DEBUG
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #define CONFIG_SH73A0
  #define CONFIG_KZM_A9_GT
  #define CONFIG_ARCH_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"

include/configs/mcx.h +0 -2

index 0c6e111..8387f19 100644
@@ -25,8 +25,6 @@
  #define CONFIG_MACH_TYPE	MACH_TYPE_MCX
  #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
  #include <asm/arch/cpu.h>		/* get chip and board defs */

include/configs/meson-gxbb-common.h +0 -1

index eaf6a9c..3bba2e6 100644
@@ -10,7 +10,6 @@
 
  #define CONFIG_CPU_ARMV8
  #define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #define CONFIG_SYS_NO_FLASH
  #define CONFIG_NR_DRAM_BANKS		1
  #define CONFIG_ENV_IS_NOWHERE		1

include/configs/nokia_rx51.h +0 -2

index cd154a4..cdae544 100644
@@ -19,8 +19,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
  /*
   * High Level Configuration Options
   */

include/configs/omap3_beagle.h +0 -2

index 4dbe2b6..fc5de03 100644
@@ -275,8 +275,6 @@
 
  #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* Defines for SPL */
  #define CONFIG_SPL_OMAP3_ID_NAND
 

include/configs/omap3_cairo.h +0 -2

index 82e0d50..4310bad 100644
@@ -192,8 +192,6 @@
 
  #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* Defines for SPL */
  #define CONFIG_SPL_OMAP3_ID_NAND
 

include/configs/omap3_evm.h +0 -2

index 52a24d3..e87b4c0 100644
@@ -340,8 +340,6 @@
  /* Uncomment to define the board revision statically */
  /* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* Defines for SPL */
  #define CONFIG_SPL_FRAMEWORK
  #define CONFIG_SPL_TEXT_BASE		0x40200800

include/configs/omap3_logic.h +0 -1

index 49a8b3f..05a4361 100644
@@ -82,7 +82,6 @@
  #define CONFIG_ANDROID_BOOT_IMAGE
  #define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
  #define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /* TWL4030 */
  #define CONFIG_TWL4030_PWM

include/configs/omap3_overo.h +0 -1

index fbd0c2a..618a546 100644
@@ -215,7 +215,6 @@
  /* Initial RAM setup */
  #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
  #define CONFIG_SYS_INIT_RAM_SIZE	0x800
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /* NAND boot config */
  #define CONFIG_SYS_NAND_BUSWIDTH_16BIT

include/configs/omap3_pandora.h +0 -2

index 380ec12..9e7bd88 100644
@@ -119,6 +119,4 @@
  #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
  #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #endif				/* __CONFIG_H */

include/configs/omap3_zoom1.h +0 -2

index 99d9fc3..6397051 100644
@@ -176,8 +176,6 @@
  #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
  #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #ifdef CONFIG_CMD_NET
  /* Ethernet (LAN9211 from SMSC9118 family) */
  #define CONFIG_SMC911X

include/configs/pcm052.h +0 -2

index 74e22db..57a7630 100644
@@ -9,8 +9,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #include <asm/arch/imx-regs.h>
 
  #define CONFIG_VF610

include/configs/rcar-gen2-common.h +0 -2

index 80313fc..8f91e8e 100644
@@ -9,8 +9,6 @@
  #ifndef __RCAR_GEN2_COMMON_H
  #define __RCAR_GEN2_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
  #include <asm/arch/rmobile.h>
 
  #define CONFIG_CMD_DFL

include/configs/rk3036_common.h +0 -2

index 21d4683..101a3ed 100644
@@ -6,8 +6,6 @@
  #ifndef __CONFIG_RK3036_COMMON_H
  #define __CONFIG_RK3036_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #include <asm/arch/hardware.h>
 
  #define CONFIG_SYS_NO_FLASH

include/configs/rk3288_common.h +0 -2

index d3d4c68..601186c 100644
@@ -7,8 +7,6 @@
  #ifndef __CONFIG_RK3288_COMMON_H
  #define __CONFIG_RK3288_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #include <asm/arch/hardware.h>
 
  #define CONFIG_SYS_NO_FLASH

include/configs/rk3399_common.h +0 -2

index 6875308..e9626a5 100644
@@ -7,8 +7,6 @@
  #ifndef __CONFIG_RK3399_COMMON_H
  #define __CONFIG_RK3399_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_SYS_NO_FLASH
  #define CONFIG_NR_DRAM_BANKS		1
  #define CONFIG_ENV_SIZE			0x2000

include/configs/rpi.h +0 -6

index dbbb81e..752cc31 100644
@@ -14,12 +14,6 @@
  #define CONFIG_SKIP_LOWLEVEL_INIT
  #endif
 
-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE		32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE		64
-#endif
-
  /* Architecture, CPU, etc.*/
  #define CONFIG_ARCH_CPU_INIT
 

include/configs/s5p_goni.h +0 -4

index 87e51d0..61c5663 100644
@@ -17,8 +17,6 @@
  #define CONFIG_S5PC110		1	/* which is in a S5PC110 */
  #define CONFIG_MACH_GONI	1	/* working with Goni */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #include <linux/sizes.h>
  #include <asm/arch/cpu.h>		/* get chip and board defs */
 

@@ -236,8 +234,6 @@
 
  #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
  #define CONFIG_POWER
  #define CONFIG_POWER_I2C
  #define CONFIG_POWER_MAX8998

include/configs/siemens-am33x-common.h +0 -2

index eab665c..3d25e3d 100644
@@ -36,8 +36,6 @@
  #define CONFIG_SETUP_MEMORY_TAGS
  #define CONFIG_INITRD_TAG
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
  /* commands to include */
 
  #define CONFIG_ENV_VARS_UBOOT_CONFIG

include/configs/smartweb.h +0 -2

index 076a5ce..8ad8f24 100644
@@ -170,8 +170,6 @@
  #define CONFIG_DFU_NAND
  #define CONFIG_SYS_DFU_DATA_BUF_SIZE	SZ_1M
  #define DFU_MANIFEST_POLL_TIMEOUT	25000
-
-#define CONFIG_SYS_CACHELINE_SIZE	0x2000
  #endif
 
  /* General Boot Parameter */

include/configs/smdkc100.h +0 -2

index 84a188a..9d52689 100644
@@ -12,8 +12,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /*
   * High Level Configuration Options
   * (easy to change)

include/configs/sniper.h +0 -2

index fb348a5..e2f5e60 100644
@@ -16,8 +16,6 @@
   * CPU
   */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_ARM_ARCH_CP15_ERRATA
  #define CONFIG_ARM_ERRATA_454179
  #define CONFIG_ARM_ERRATA_430973

include/configs/socfpga_common.h +0 -1

index f654f94..ce5781b 100644
@@ -75,7 +75,6 @@
  /*
   * Cache
   */
-#define CONFIG_SYS_CACHELINE_SIZE 32
  #define CONFIG_SYS_L2_PL310
  #define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
 

include/configs/sunxi-common.h +0 -1

index b9aa62b..f64edd4 100644
@@ -55,7 +55,6 @@
 
  /* CPU */
  #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE	64
  #define CONFIG_TIMER_CLK_FREQ		24000000
 
  /*

include/configs/tam3517-common.h +0 -2

index 73ff416..5213065 100644
@@ -23,8 +23,6 @@
 
  #define CONFIG_SYS_TEXT_BASE 0x80008000
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 
  #include <asm/arch/cpu.h>		/* get chip and board defs */

include/configs/tao3530.h +0 -2

index 6616d73..52bd837 100644
@@ -13,8 +13,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /*
   * High Level Configuration Options
   */

include/configs/taurus.h +0 -2

index 2d091db..513e655 100644
@@ -133,8 +133,6 @@
  #define CONFIG_DFU_NAND
  #define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)
  #define DFU_MANIFEST_POLL_TIMEOUT	25000
-
-#define CONFIG_SYS_CACHELINE_SIZE	SZ_8K
  #endif
 
  /* SPI EEPROM */

include/configs/tegra114-common.h +0 -1

index 21454d4..f07c198 100644
@@ -9,7 +9,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /*
   * NS16550 Configuration

include/configs/tegra124-common.h +0 -1

index 39e74f0..a6055ad 100644
@@ -11,7 +11,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /*
   * NS16550 Configuration

include/configs/tegra186-common.h +0 -1

index aa7b9d0..b7bb1bc 100644
@@ -10,7 +10,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /*
   * NS16550 Configuration

include/configs/tegra20-common.h +0 -1

index 00e85c4..1b24db3 100644
@@ -10,7 +10,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /*
   * Errata configuration

include/configs/tegra210-common.h +0 -1

index 8f35a7b..03aa5b6 100644
@@ -11,7 +11,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  /*
   * NS16550 Configuration

include/configs/tegra30-common.h +0 -1

index 9afd864..4a74505 100644
@@ -10,7 +10,6 @@
  #include "tegra-common.h"
 
  /* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /*
   * Errata configuration

include/configs/ti814x_evm.h +0 -2

index 3c05883..732854e 100644
@@ -16,8 +16,6 @@
  #ifndef __CONFIG_TI814X_EVM_H
  #define __CONFIG_TI814X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_TI81XX
  #define CONFIG_TI814X
  #define CONFIG_SYS_NO_FLASH

include/configs/ti816x_evm.h +0 -2

index 05fd00f..17f12a8 100644
@@ -10,8 +10,6 @@
  #ifndef __CONFIG_TI816X_EVM_H
  #define __CONFIG_TI816X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_TI81XX
  #define CONFIG_TI816X
  #define CONFIG_SYS_NO_FLASH

include/configs/ti_am335x_common.h +0 -1

index bcd56fc..a9b10d0 100644
@@ -14,7 +14,6 @@
 
  #define CONFIG_AM33XX
  #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       64
  #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
  #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
  #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC

include/configs/ti_armv7_keystone2.h +0 -1

index 4aa262e..c830c0c 100644
@@ -200,7 +200,6 @@
  #define CONFIG_USB_STORAGE
  #define CONFIG_EFI_PARTITION
  #define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE		64
  #define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
  #define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
  #define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE

include/configs/ti_omap3_common.h +0 -2

index 32877d1..c54b7b5 100644
@@ -18,8 +18,6 @@
   * High Level Configuration Options
   */
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #include <asm/arch/cpu.h>
  #include <asm/arch/omap.h>
 

include/configs/ti_omap4_common.h +0 -1

index 5fad3c1..e6e88c5 100644
@@ -26,7 +26,6 @@
  #define CONFIG_SYS_L2_PL310		1
  #define CONFIG_SYS_PL310_BASE	0x48242000
  #endif
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  /* Get CPU defs */
  #include <asm/arch/cpu.h>

include/configs/ti_omap5_common.h +0 -2

index 3589cdc..e42c88e 100644
@@ -23,8 +23,6 @@
  /* Common ARM Erratas */
  #define CONFIG_ARM_ERRATA_798870
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* Use General purpose timer 1 */
  #define CONFIG_SYS_TIMERBASE		GPT2_BASE
 

include/configs/tricorder.h +0 -2

index 127a968..ae0e89c 100644
@@ -16,8 +16,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  /* High Level Configuration Options */
  #define CONFIG_SYS_THUMB_BUILD
  #define CONFIG_OMAP			/* in a TI OMAP core */

include/configs/uniphier.h +0 -6

index 0f5b20f..f41a0b1 100644
@@ -30,12 +30,6 @@
  /* #define CONFIG_SYS_ICACHE_OFF */
  /* #define CONFIG_SYS_DCACHE_OFF */
 
-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE	128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-
  #define CONFIG_DISPLAY_CPUINFO
  #define CONFIG_DISPLAY_BOARDINFO
  #define CONFIG_MISC_INIT_F

include/configs/vexpress_aemv8a.h +0 -1

index 9aca393..a7c6fb7 100644
@@ -20,7 +20,6 @@
  #define CONFIG_SUPPORT_RAW_INITRD
 
  /* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
 

include/configs/vexpress_common.h +0 -2

index 51898e6..a8eba31 100644
@@ -118,8 +118,6 @@
  #define CONFIG_SYS_MEMTEST_START	V2M_BASE
  #define CONFIG_SYS_MEMTEST_END		0x20000000
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
  #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
  #define CONFIG_SETUP_MEMORY_TAGS	1
  #define CONFIG_SYS_L2CACHE_OFF		1

include/configs/vf610twr.h +0 -2

index c4a1fd0..33f966a 100644
@@ -9,8 +9,6 @@
  #ifndef __CONFIG_H
  #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
  #include <asm/arch/imx-regs.h>
 
  #define CONFIG_VF610

include/configs/woodburn_common.h +0 -1

index 153466a..de6b183 100644
@@ -19,7 +19,6 @@
  #define CONFIG_SYS_FSL_CLK
 
  #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  #define CONFIG_DISPLAY_CPUINFO
 

include/configs/xilinx_zynqmp.h +0 -1

index ca60e5d..104e63d 100644
@@ -35,7 +35,6 @@
  #define CPU_RELEASE_ADDR	0xFFFFFF0
 
  /* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
 
  #if !defined(CONFIG_IDENT_STRING)
  # define CONFIG_IDENT_STRING		" Xilinx ZynqMP"

include/configs/zynq-common.h +0 -1

index e59e412..20ca709 100644
@@ -16,7 +16,6 @@
  #endif
 
  /* Cache options */
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
  #define CONFIG_SYS_L2CACHE_OFF
  #ifndef CONFIG_SYS_L2CACHE_OFF

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes. Second, we say ARM64 uses 64 bytes not 80 (as found in the Linux Kernel) due to how we use it for forcing alignment from the compiler. Our other option here would be to move up to 128 bytes but as no processors yet use 80 bytes, we'll revisit this logic as needed later.

Finally, it is possible that Uniphier will need to adjust ARCH_DMA_MINALIGN in the case of CACHE_UNIPHIER being enabled as previously it moves ARCH_DMA_MINALIGN up to 128 bytes

Cc Albert Aribaud <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Nagendra T S <[email protected]>

Cc Vaibhav Hiremath <[email protected]>

Cc Lokesh Vutla <[email protected]>

Cc Steve Rae <[email protected]>

Cc Igor Grinberg <[email protected]>

Cc Nikita Kiryanov <[email protected]>

Cc Stefan Agner <[email protected]>

Cc Heiko Schocher <[email protected]>

Cc Mateusz Kulikowski <[email protected]>

Cc Peter Griffin <[email protected]>

Cc Paul Kocialkowski <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Cc "Pali Roh?r" <[email protected]>

Cc Adam Ford <[email protected]>

Cc Steve Sakoman <[email protected]>

Cc Grazvydas Ignotas <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Robert Baldyga <[email protected]>

Cc Minkyu Kang <[email protected]>

Cc Thomas Weber <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc David Feng <[email protected]>

Cc Alison Wang <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

Cc York Sun <[email protected]>

Cc Shengzhou Liu <[email protected]>

Cc Mingkai Hu <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Aneesh Bansal <[email protected]>

Cc Saksham Jain <[email protected]>

Cc Qianyu Gong <[email protected]>

Cc Wang Dongsheng <[email protected]>

Cc Alex Porosanu <[email protected]>

Cc Hongbo Zhang <[email protected]>

Cc tang yuantian <[email protected]>

Cc Rajesh Bhagat <[email protected]>

Cc Josh Wu <[email protected]>

Cc Bo Shen <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Hannes Schmelzer <[email protected]>

Cc Thomas Chou <[email protected]>

Cc Joe Hershberger <[email protected]>

Cc Sam Protsenko <[email protected]>

Cc Bin Meng <[email protected]>

Cc Christophe Ricard <[email protected]>

Cc Anand Moon <[email protected]>

Cc Beniamino Galvani <[email protected]>

Cc Carlo Caione <[email protected]>

Cc huang lin <[email protected]>

Cc Sjoerd Simons <[email protected]>

Cc Xu Ziyuan <[email protected]>

Cc "jk.kernel at gmail.com" <[email protected]>

Cc "Ariel D'Alessandro" <[email protected]>

Cc Kever Yang <[email protected]>

Cc Samuel Egli <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Hans de Goede <[email protected]>

Cc Ian Campbell <[email protected]>

Cc Siarhei Siamashka <[email protected]>

Cc Boris Brezillon <[email protected]>

Cc Andre Przywara <[email protected]>

Cc Bernhard Nortmann <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Ben Whitten <[email protected]>

Cc Tom Warren <[email protected]>

Cc Alexander Graf <[email protected]>

Cc Sekhar Nori <[email protected]>

Cc Vitaly Andrianov <[email protected]>

Cc "Andrew F. Davis" <[email protected]>

Cc Murali Karicheri <[email protected]>

Cc Carlos Hernandez <[email protected]>

Cc Ladislav Michl <[email protected]>

Cc Ash Charles <[email protected]>

Cc Mugunthan V N <[email protected]>

Cc Daniel Allred <[email protected]>

Cc Gong Qianyu <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/Kconfig                                  |  5 +++++
 arch/arm/cpu/arm11/cpu.c                          |  5 -----
 arch/arm/cpu/arm926ejs/cache.c                    |  5 -----
 arch/arm/cpu/pxa/cache.c                          |  5 -----
 arch/arm/include/asm/arch-armada100/config.h      |  2 --
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  2 --
 arch/arm/include/asm/arch-ls102xa/config.h        |  2 --
 arch/arm/include/asm/arch-mx5/imx-regs.h          |  2 --
 arch/arm/include/asm/arch-mx6/imx-regs.h          |  6 ------
 arch/arm/include/asm/arch-mx7/imx-regs.h          |  2 --
 arch/arm/include/asm/cache.h                      | 10 +++-------
 arch/arm/lib/cache.c                              |  4 ----
 arch/arm/mach-kirkwood/include/mach/config.h      |  2 --
 arch/arm/mach-mvebu/include/mach/config.h         |  2 --
 include/configs/am3517_crane.h                    |  2 --
 include/configs/am3517_evm.h                      |  2 --
 include/configs/am43xx_evm.h                      |  2 --
 include/configs/at91-sama5_common.h               |  2 --
 include/configs/bcm23550_w1d.h                    |  1 -
 include/configs/bcm28155_ap.h                     |  1 -
 include/configs/bcm_ep_board.h                    |  2 --
 include/configs/bur_am335x_common.h               |  1 -
 include/configs/cm_t3517.h                        |  3 ---
 include/configs/cm_t43.h                          |  1 -
 include/configs/colibri_vf.h                      |  4 ----
 include/configs/corvus.h                          |  1 -
 include/configs/dragonboard410c.h                 |  2 --
 include/configs/exynos4-common.h                  |  1 -
 include/configs/exynos5-common.h                  |  1 -
 include/configs/flea3.h                           |  1 -
 include/configs/hikey.h                           |  1 -
 include/configs/kc1.h                             |  1 -
 include/configs/kzm9g.h                           |  2 --
 include/configs/mcx.h                             |  2 --
 include/configs/meson-gxbb-common.h               |  1 -
 include/configs/nokia_rx51.h                      |  2 --
 include/configs/omap3_beagle.h                    |  2 --
 include/configs/omap3_cairo.h                     |  2 --
 include/configs/omap3_evm.h                       |  2 --
 include/configs/omap3_logic.h                     |  1 -
 include/configs/omap3_overo.h                     |  1 -
 include/configs/omap3_pandora.h                   |  2 --
 include/configs/omap3_zoom1.h                     |  2 --
 include/configs/pcm052.h                          |  2 --
 include/configs/rcar-gen2-common.h                |  2 --
 include/configs/rk3036_common.h                   |  2 --
 include/configs/rk3288_common.h                   |  2 --
 include/configs/rk3399_common.h                   |  2 --
 include/configs/rpi.h                             |  6 ------
 include/configs/s5p_goni.h                        |  4 ----
 include/configs/siemens-am33x-common.h            |  2 --
 include/configs/smartweb.h                        |  2 --
 include/configs/smdkc100.h                        |  2 --
 include/configs/sniper.h                          |  2 --
 include/configs/socfpga_common.h                  |  1 -
 include/configs/sunxi-common.h                    |  1 -
 include/configs/tam3517-common.h                  |  2 --
 include/configs/tao3530.h                         |  2 --
 include/configs/taurus.h                          |  2 --
 include/configs/tegra114-common.h                 |  1 -
 include/configs/tegra124-common.h                 |  1 -
 include/configs/tegra186-common.h                 |  1 -
 include/configs/tegra20-common.h                  |  1 -
 include/configs/tegra210-common.h                 |  1 -
 include/configs/tegra30-common.h                  |  1 -
 include/configs/ti814x_evm.h                      |  2 --
 include/configs/ti816x_evm.h                      |  2 --
 include/configs/ti_am335x_common.h                |  1 -
 include/configs/ti_armv7_keystone2.h              |  1 -
 include/configs/ti_omap3_common.h                 |  2 --
 include/configs/ti_omap4_common.h                 |  1 -
 include/configs/ti_omap5_common.h                 |  2 --
 include/configs/tricorder.h                       |  2 --
 include/configs/uniphier.h                        |  6 ------
 include/configs/vexpress_aemv8a.h                 |  1 -
 include/configs/vexpress_common.h                 |  2 --
 include/configs/vf610twr.h                        |  2 --
 include/configs/woodburn_common.h                 |  1 -
 include/configs/xilinx_zynqmp.h                   |  1 -
 include/configs/zynq-common.h                     |  1 -
 80 files changed, 8 insertions(+), 163 deletions(-)

arch/arm/Kconfig +5 -0

index aef901c..15cd66a 100644
@@ -79,6 +79,11 @@ config SYS_ARM_ARCH
        default 4 if CPU_SA1100
        default 8 if ARM64
 
+config SYS_CACHELINE_SIZE
+       int
+       default 64 if CPU_V7 || ARM64
+       default 32
+
 config SEMIHOSTING
        bool "support boot from semihosting"
        help

arch/arm/cpu/arm11/cpu.c +0 -5

index 7244c2e..ef32c3f 100644
@@ -53,11 +53,6 @@ static void cache_flush(void)
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

arch/arm/cpu/arm926ejs/cache.c +0 -5

index 2119382..02cb24c 100644
@@ -8,11 +8,6 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 void invalidate_dcache_all(void)
 {
        asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));

arch/arm/cpu/pxa/cache.c +0 -5

index 7aba112..d26354e 100644
@@ -8,11 +8,6 @@
 #include <common.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 void invalidate_dcache_all(void)
 {
        /* Flush/Invalidate I cache */

arch/arm/include/asm/arch-armada100/config.h +0 -2

index e062da1..6ebc759 100644
@@ -16,8 +16,6 @@
 #define _ARMD1_CONFIG_H
 
 #include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK                (14745600)      /* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK    (3250000)       /* Timer Freq. 3.25MHZ */

arch/arm/include/asm/arch-fsl-layerscape/config.h +0 -2

index b0ad4b4..5279981 100644
@@ -36,7 +36,6 @@
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_PAGE_SIZE           0x10000
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)

@@ -150,7 +149,6 @@
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE              64
 #define CONFIG_NUM_DDR_CONTROLLERS             1
 #define CONFIG_SYS_FSL_SEC_COMPAT              5
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */

arch/arm/include/asm/arch-ls102xa/config.h +0 -2

index d408fe4..56d8f32 100644
@@ -7,8 +7,6 @@
 #ifndef _ASM_ARMV7_LS102XA_CONFIG_
 #define _ASM_ARMV7_LS102XA_CONFIG_
 
-#define CONFIG_SYS_CACHELINE_SIZE              64
-
 #define OCRAM_BASE_ADDR                                0x10000000
 #define OCRAM_SIZE                             0x00010000
 #define OCRAM_BASE_S_ADDR                      0x10010000

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -2

index e73cc07..3e79fa3 100644
@@ -9,8 +9,6 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000

arch/arm/include/asm/arch-mx6/imx-regs.h +0 -6

index ac37e4f..53bf054 100644
@@ -9,12 +9,6 @@
 
 #define ARCH_MXC
 
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE      64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 

arch/arm/include/asm/arch-mx7/imx-regs.h +0 -2

index 74917f0..d33be31 100644
@@ -9,8 +9,6 @@
 
 #define ARCH_MXC
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define ROM_SW_INFO_ADDR                0x000001E8
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x00017FFF

arch/arm/include/asm/cache.h +3 -7

index 16e65c3..8ec81c6 100644
@@ -43,14 +43,10 @@ void dram_bank_mmu_setup(int bank);
 #endif
 
 /*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the L1 data cache shall be set for us in
+ * CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be higher than what the
+ * particular core uses, but this is OK to use in terms of alignment.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
 #define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN      64
-#endif
 
 #endif /* _ASM_CACHE_H */

arch/arm/lib/cache.c +0 -4

index d330b09..4f72f89 100644
@@ -10,10 +10,6 @@
 #include <common.h>
 #include <malloc.h>
 
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
 /*
  * Flush range from all levels of d-cache/unified-cache.
  * Affects the range [start, start + size - 1].

arch/arm/mach-kirkwood/include/mach/config.h +0 -2

index 60b60aa..446457f 100644
@@ -24,8 +24,6 @@
 #endif /* CONFIG_KW88F6281 */
 
 #include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE      32
-                               /* default Dcache Line length for kirkwood */
 #define CONFIG_MD5     /* get_random_hex on krikwood needs MD5 support */
 #define CONFIG_KIRKWOOD_EGIGA_INIT     /* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8  /* Set RGMII Pad voltage to 1.8V */

arch/arm/mach-mvebu/include/mach/config.h +0 -2

index 4df70d7..1b35e08 100644
@@ -26,8 +26,6 @@
 #define MV88F78X60 /* for the DDR training bin_hdr code */
 #endif
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #define CONFIG_SYS_L2_PL310
 
 #ifdef CONFIG_SPL_BUILD

include/configs/am3517_crane.h +0 -2

index a65d1a8..30c4278 100644
@@ -13,8 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * High Level Configuration Options
  */

include/configs/am3517_evm.h +0 -2

index 4d88aac..ef4a8ba 100644
@@ -18,8 +18,6 @@
 #define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */

include/configs/am43xx_evm.h +0 -2

index 0467953..518b904 100644
@@ -11,7 +11,6 @@
 
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       32
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 21)    /* 2GB */
 #define CONFIG_SYS_TIMERBASE           0x48040000      /* Use Timer2 */
 

@@ -49,7 +48,6 @@
 /* Enabling L2 Cache */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE  0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * Since SPL did pll and ddr initialization for us,

include/configs/at91-sama5_common.h +0 -2

index 9257c5f..051186d 100644
@@ -12,8 +12,6 @@
 
 #include <asm/hardware.h>
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #define CONFIG_SYS_TEXT_BASE           0x26f00000
 
 /* ARM asynchronous clock */

include/configs/bcm23550_w1d.h +0 -1

index 770dd87..b968801 100644
@@ -127,7 +127,6 @@
 /* Commands */
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #undef CONFIG_USB_GADGET_VBUS_DRAW
 #define CONFIG_USB_GADGET_VBUS_DRAW    0
 #define CONFIG_USBID_ADDR              0x34052c46

include/configs/bcm28155_ap.h +0 -1

index df0b2ba..f38f081 100644
@@ -126,7 +126,6 @@
 /* Commands */
 #define CONFIG_FAT_WRITE
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #define CONFIG_USBID_ADDR              0x34052c46
 
 #endif /* __BCM28155_AP_H */

include/configs/bcm_ep_board.h +0 -2

index 50cd743..b5e5029 100644
@@ -11,8 +11,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * Memory configuration
  * (these must be defined elsewhere)

include/configs/bur_am335x_common.h +0 -1

index a94b1e2..04da877 100644
@@ -15,7 +15,6 @@
 #define CONFIG_AM33XX
 #define CONFIG_OMAP
 #define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
 
 /* Timer information */

include/configs/cm_t3517.h +0 -3

index ea9983b..a89ccb7 100644
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * High Level Configuration Options
  */

@@ -30,7 +28,6 @@
  * Although the default iss 64, we still define it
  * to be on the safe side once the default is changed.
  */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 

include/configs/cm_t43.h +0 -1

index 5d94f13..b896d4d 100644
@@ -79,7 +79,6 @@
 /* Enabling L2 Cache */
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * Since SPL did pll and ddr initialization for us,

include/configs/colibri_vf.h +0 -4

index 5892595..fb68e59 100644
@@ -12,8 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610

@@ -207,8 +205,6 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
 /* USB Host Support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_VF

include/configs/corvus.h +0 -1

index 28ea15b..746475d 100644
@@ -118,7 +118,6 @@
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   (SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT      25000
 
-#define CONFIG_SYS_CACHELINE_SIZE      SZ_8K
 #define CONFIG_SYS_LOAD_ADDR   ATMEL_BASE_CS6
 
 /* bootstrap + u-boot + env in nandflash */

include/configs/dragonboard410c.h +0 -2

index 1dbe219..cc7ab83 100644
@@ -27,8 +27,6 @@
 #define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x80000)
 #define CONFIG_SYS_BOOTM_LEN           0x1000000 /* 16MB max kernel size */
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* UART */
 #define CONFIG_BAUDRATE                        115200
 

include/configs/exynos4-common.h +0 -1

index fbe0fa9..fdbaf02 100644
@@ -15,7 +15,6 @@
 
 #define CONFIG_BOARD_COMMON
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
 #define CONFIG_REVISION_TAG
 
 /* SD/MMC configuration */

include/configs/exynos5-common.h +0 -1

index f2ed798..1538787 100644
@@ -13,7 +13,6 @@
 
 #include "exynos-common.h"
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #define CONFIG_EXYNOS_SPL
 
 #ifdef FTRACE

include/configs/flea3.h +0 -1

index 824aca4..e84803d 100644
@@ -19,7 +19,6 @@
 #define CONFIG_MX35
 
 #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define CONFIG_DISPLAY_CPUINFO
 

include/configs/hikey.h +0 -1

index ffcc4d2..142326c 100644
@@ -22,7 +22,6 @@
 #define CONFIG_SUPPORT_RAW_INITRD
 
 /* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #define CONFIG_IDENT_STRING            "hikey"
 

include/configs/kc1.h +0 -1

index b08cf21..8b95799 100644
@@ -24,7 +24,6 @@
 
 #define CONFIG_SYS_L2_PL310            1
 #define CONFIG_SYS_PL310_BASE          0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * Platform

include/configs/kzm9g.h +0 -2

index 94f3516..a4b296a 100644
@@ -10,8 +10,6 @@
 
 #undef DEBUG
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #define CONFIG_SH73A0
 #define CONFIG_KZM_A9_GT
 #define CONFIG_ARCH_RMOBILE_BOARD_STRING       "KMC KZM-A9-GT"

include/configs/mcx.h +0 -2

index 0c6e111..8387f19 100644
@@ -25,8 +25,6 @@
 #define CONFIG_MACH_TYPE       MACH_TYPE_MCX
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */

include/configs/meson-gxbb-common.h +0 -1

index eaf6a9c..3bba2e6 100644
@@ -10,7 +10,6 @@
 
 #define CONFIG_CPU_ARMV8
 #define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_ENV_IS_NOWHERE          1

include/configs/nokia_rx51.h +0 -2

index cd154a4..cdae544 100644
@@ -19,8 +19,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 /*
  * High Level Configuration Options
  */

include/configs/omap3_beagle.h +0 -2

index 4dbe2b6..fc5de03 100644
@@ -275,8 +275,6 @@
 
 #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* Defines for SPL */
 #define CONFIG_SPL_OMAP3_ID_NAND
 

include/configs/omap3_cairo.h +0 -2

index 82e0d50..4310bad 100644
@@ -192,8 +192,6 @@
 
 #define CONFIG_OMAP3_SPI
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* Defines for SPL */
 #define CONFIG_SPL_OMAP3_ID_NAND
 

include/configs/omap3_evm.h +0 -2

index 52a24d3..e87b4c0 100644
@@ -340,8 +340,6 @@
 /* Uncomment to define the board revision statically */
 /* #define CONFIG_STATIC_BOARD_REV     OMAP3EVM_BOARD_GEN_2 */
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* Defines for SPL */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE           0x40200800

include/configs/omap3_logic.h +0 -1

index 49a8b3f..05a4361 100644
@@ -82,7 +82,6 @@
 #define CONFIG_ANDROID_BOOT_IMAGE
 #define CONFIG_FASTBOOT_BUF_ADDR       CONFIG_SYS_LOAD_ADDR
 #define CONFIG_FASTBOOT_BUF_SIZE       0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /* TWL4030 */
 #define CONFIG_TWL4030_PWM

include/configs/omap3_overo.h +0 -1

index fbd0c2a..618a546 100644
@@ -215,7 +215,6 @@
 /* Initial RAM setup */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE       0x800
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /* NAND boot config */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT

include/configs/omap3_pandora.h +0 -2

index 380ec12..9e7bd88 100644
@@ -119,6 +119,4 @@
 #define CONFIG_ENV_OFFSET              SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #endif                         /* __CONFIG_H */

include/configs/omap3_zoom1.h +0 -2

index 99d9fc3..6397051 100644
@@ -176,8 +176,6 @@
 #define CONFIG_ENV_OFFSET              SMNAND_ENV_OFFSET
 #define CONFIG_ENV_ADDR                        SMNAND_ENV_OFFSET
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #ifdef CONFIG_CMD_NET
 /* Ethernet (LAN9211 from SMSC9118 family) */
 #define CONFIG_SMC911X

include/configs/pcm052.h +0 -2

index 74e22db..57a7630 100644
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610

include/configs/rcar-gen2-common.h +0 -2

index 80313fc..8f91e8e 100644
@@ -9,8 +9,6 @@
 #ifndef __RCAR_GEN2_COMMON_H
 #define __RCAR_GEN2_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
 #include <asm/arch/rmobile.h>
 
 #define CONFIG_CMD_DFL

include/configs/rk3036_common.h +0 -2

index 21d4683..101a3ed 100644
@@ -6,8 +6,6 @@
 #ifndef __CONFIG_RK3036_COMMON_H
 #define __CONFIG_RK3036_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH

include/configs/rk3288_common.h +0 -2

index d3d4c68..601186c 100644
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_RK3288_COMMON_H
 #define __CONFIG_RK3288_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH

include/configs/rk3399_common.h +0 -2

index 6875308..e9626a5 100644
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_RK3399_COMMON_H
 #define __CONFIG_RK3399_COMMON_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_ENV_SIZE                        0x2000

include/configs/rpi.h +0 -6

index dbbb81e..752cc31 100644
@@ -14,12 +14,6 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #endif
 
-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE              32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE              64
-#endif
-
 /* Architecture, CPU, etc.*/
 #define CONFIG_ARCH_CPU_INIT
 

include/configs/s5p_goni.h +0 -4

index 87e51d0..61c5663 100644
@@ -17,8 +17,6 @@
 #define CONFIG_S5PC110         1       /* which is in a S5PC110 */
 #define CONFIG_MACH_GONI       1       /* working with Goni */
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #include <linux/sizes.h>
 #include <asm/arch/cpu.h>              /* get chip and board defs */
 

@@ -236,8 +234,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_LOAD_ADDR - 0x1000000)
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX8998

include/configs/siemens-am33x-common.h +0 -2

index eab665c..3d25e3d 100644
@@ -36,8 +36,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 
-#define CONFIG_SYS_CACHELINE_SIZE       64
-
 /* commands to include */
 
 #define CONFIG_ENV_VARS_UBOOT_CONFIG

include/configs/smartweb.h +0 -2

index 076a5ce..8ad8f24 100644
@@ -170,8 +170,6 @@
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   SZ_1M
 #define DFU_MANIFEST_POLL_TIMEOUT      25000
-
-#define CONFIG_SYS_CACHELINE_SIZE      0x2000
 #endif
 
 /* General Boot Parameter */

include/configs/smdkc100.h +0 -2

index 84a188a..9d52689 100644
@@ -12,8 +12,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * High Level Configuration Options
  * (easy to change)

include/configs/sniper.h +0 -2

index fb348a5..e2f5e60 100644
@@ -16,8 +16,6 @@
  * CPU
  */
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_ARM_ARCH_CP15_ERRATA
 #define CONFIG_ARM_ERRATA_454179
 #define CONFIG_ARM_ERRATA_430973

include/configs/socfpga_common.h +0 -1

index f654f94..ce5781b 100644
@@ -75,7 +75,6 @@
 /*
  * Cache
  */
-#define CONFIG_SYS_CACHELINE_SIZE 32
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 

include/configs/sunxi-common.h +0 -1

index b9aa62b..f64edd4 100644
@@ -55,7 +55,6 @@
 
 /* CPU */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE      64
 #define CONFIG_TIMER_CLK_FREQ          24000000
 
 /*

include/configs/tam3517-common.h +0 -2

index 73ff416..5213065 100644
@@ -23,8 +23,6 @@
 
 #define CONFIG_SYS_TEXT_BASE 0x80008000
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_EMIF4   /* The chip has EMIF4 controller */
 
 #include <asm/arch/cpu.h>              /* get chip and board defs */

include/configs/tao3530.h +0 -2

index 6616d73..52bd837 100644
@@ -13,8 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * High Level Configuration Options
  */

include/configs/taurus.h +0 -2

index 2d091db..513e655 100644
@@ -133,8 +133,6 @@
 #define CONFIG_DFU_NAND
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE   (SZ_1M)
 #define DFU_MANIFEST_POLL_TIMEOUT      25000
-
-#define CONFIG_SYS_CACHELINE_SIZE      SZ_8K
 #endif
 
 /* SPI EEPROM */

include/configs/tegra114-common.h +0 -1

index 21454d4..f07c198 100644
@@ -9,7 +9,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /*
  * NS16550 Configuration

include/configs/tegra124-common.h +0 -1

index 39e74f0..a6055ad 100644
@@ -11,7 +11,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /*
  * NS16550 Configuration

include/configs/tegra186-common.h +0 -1

index aa7b9d0..b7bb1bc 100644
@@ -10,7 +10,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /*
  * NS16550 Configuration

include/configs/tegra20-common.h +0 -1

index 00e85c4..1b24db3 100644
@@ -10,7 +10,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * Errata configuration

include/configs/tegra210-common.h +0 -1

index 8f35a7b..03aa5b6 100644
@@ -11,7 +11,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 /*
  * NS16550 Configuration

include/configs/tegra30-common.h +0 -1

index 9afd864..4a74505 100644
@@ -10,7 +10,6 @@
 #include "tegra-common.h"
 
 /* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * Errata configuration

include/configs/ti814x_evm.h +0 -2

index 3c05883..732854e 100644
@@ -16,8 +16,6 @@
 #ifndef __CONFIG_TI814X_EVM_H
 #define __CONFIG_TI814X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_TI81XX
 #define CONFIG_TI814X
 #define CONFIG_SYS_NO_FLASH

include/configs/ti816x_evm.h +0 -2

index 05fd00f..17f12a8 100644
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_TI816X_EVM_H
 #define __CONFIG_TI816X_EVM_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_TI81XX
 #define CONFIG_TI816X
 #define CONFIG_SYS_NO_FLASH

include/configs/ti_am335x_common.h +0 -1

index bcd56fc..a9b10d0 100644
@@ -14,7 +14,6 @@
 
 #define CONFIG_AM33XX
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
 #define CONFIG_SYS_TIMERBASE           0x48040000      /* Use Timer2 */
 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC

include/configs/ti_armv7_keystone2.h +0 -1

index 4aa262e..c830c0c 100644
@@ -200,7 +200,6 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_EFI_PARTITION
 #define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE              64
 #define CONFIG_USB_SS_BASE                     KS2_USB_SS_BASE
 #define CONFIG_USB_HOST_XHCI_BASE              KS2_USB_HOST_XHCI_BASE
 #define CONFIG_DEV_USB_PHY_BASE                        KS2_DEV_USB_PHY_BASE

include/configs/ti_omap3_common.h +0 -2

index 32877d1..c54b7b5 100644
@@ -18,8 +18,6 @@
  * High Level Configuration Options
  */
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #include <asm/arch/cpu.h>
 #include <asm/arch/omap.h>
 

include/configs/ti_omap4_common.h +0 -1

index 5fad3c1..e6e88c5 100644
@@ -26,7 +26,6 @@
 #define CONFIG_SYS_L2_PL310            1
 #define CONFIG_SYS_PL310_BASE  0x48242000
 #endif
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /* Get CPU defs */
 #include <asm/arch/cpu.h>

include/configs/ti_omap5_common.h +0 -2

index 3589cdc..e42c88e 100644
@@ -23,8 +23,6 @@
 /* Common ARM Erratas */
 #define CONFIG_ARM_ERRATA_798870
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* Use General purpose timer 1 */
 #define CONFIG_SYS_TIMERBASE           GPT2_BASE
 

include/configs/tricorder.h +0 -2

index 127a968..ae0e89c 100644
@@ -16,8 +16,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /* High Level Configuration Options */
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_OMAP                    /* in a TI OMAP core */

include/configs/uniphier.h +0 -6

index 0f5b20f..f41a0b1 100644
@@ -30,12 +30,6 @@
 /* #define CONFIG_SYS_ICACHE_OFF */
 /* #define CONFIG_SYS_DCACHE_OFF */
 
-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE      128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE      32
-#endif
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_F

include/configs/vexpress_aemv8a.h +0 -1

index 9aca393..a7c6fb7 100644
@@ -20,7 +20,6 @@
 #define CONFIG_SUPPORT_RAW_INITRD
 
 /* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #define CONFIG_IDENT_STRING            " vexpress_aemv8a"
 

include/configs/vexpress_common.h +0 -2

index 51898e6..a8eba31 100644
@@ -118,8 +118,6 @@
 #define CONFIG_SYS_MEMTEST_START       V2M_BASE
 #define CONFIG_SYS_MEMTEST_END         0x20000000
 
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 #define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS       1
 #define CONFIG_SYS_L2CACHE_OFF         1

include/configs/vf610twr.h +0 -2

index c4a1fd0..33f966a 100644
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610

include/configs/woodburn_common.h +0 -1

index 153466a..de6b183 100644
@@ -19,7 +19,6 @@
 #define CONFIG_SYS_FSL_CLK
 
 #define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define CONFIG_DISPLAY_CPUINFO
 

include/configs/xilinx_zynqmp.h +0 -1

index ca60e5d..104e63d 100644
@@ -35,7 +35,6 @@
 #define CPU_RELEASE_ADDR       0xFFFFFF0
 
 /* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #if !defined(CONFIG_IDENT_STRING)
 # define CONFIG_IDENT_STRING           " Xilinx ZynqMP"

include/configs/zynq-common.h +0 -2

index e59e412..20ca709 100644
@@ -16,7 +16,6 @@
 #endif
 
 /* Cache options */
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define CONFIG_SYS_L2CACHE_OFF
 #ifndef CONFIG_SYS_L2CACHE_OFF
--

2.8.1