OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Subsystems (5)
Paul Walmsley
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Hello,
This series adds the ability to late-initialize individual hwmods. The goal here is for clockevent (and eventually clocksource) hwmods to be late-initialized individually, and right before they are needed, in the timer init code. Then omap_hwmod_late_init(), which late-inits the rest of the hwmods, is intended to run as an initcall -- much later in the boot process.
This series includes the OMAP2/3 hwmod data for the GPTIMERs that Tarun posted earlier. This data is necessary for this new code to avoid warnings during boot.
Boot-tested on N800, OMAP34xx Beagleboard and OMAP4430ES2 Panda. Applies on Tony's 04aa67dec63b61c1a8b9b6d001262250f1a92130 ("Merge branch 'for-tony' of git://gitorious.org/usb/usb into omap-for-linus")
- Paul
---
hwmod_clockevent_2.6.39
text data bss dec hex filename
5774609 497512 5596888 11869009 b51b51 vmlinux.omap2plus_defconfig.orig
5778597 504584 5596856 11880037 b54665 vmlinux.omap2plus_defconfig
Paul Walmsley (5):
OMAP2+: hwmod: find MPU initiator hwmod during in _register() OMAP2+: hwmod: allow multiple calls to omap_hwmod_init()
OMAP2+: hwmod: ignore attempts to re-late-init a hwmod
OMAP2+: hwmod: add ability to late-init individual hwmods OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
Thara Gopinath (3):
OMAP2420: hwmod data: add dmtimer
OMAP2430: hwmod data: add dmtimer
OMAP3: hwmod data: add dmtimer
arch/arm/mach-omap2/omap_hwmod.c | 124 +++-- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634 +++++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_2430_data.c | 633 +++++++++++++++++++++++++ arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 649 ++++++++++++++++++++++++++ arch/arm/mach-omap2/timer-gp.c | 8 arch/arm/plat-omap/include/plat/dmtimer.h | 11 arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 7 files changed, 2024 insertions(+), 38 deletions(-)
Paul Walmsley
maintainerPATCH 1/8 OMAP2420: hwmod data: add dmtimer
From: Thara Gopinath <[email protected]>
Add dmtimer data.
--- arch/arm/mach-omap2/omap_hwmod_2420_data.c | 634 ++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/dmtimer.h | 11 2 files changed, 645 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_2420_data.c +634 -0
@@ -19,6 +19,7 @@#include <plat/i2c.h> #include <plat/gpio.h> #include <plat/mcspi.h> +#include <plat/dmtimer.h> #include "omap_hwmod_common_data.h"
@@ -318,6 +319,625 @@ static struct omap_hwmod omap2420_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 , + .syss_offs =0x0014 , + .sysc_flags = (SYSC_HAS_SIDLEMODE |SYSC_HAS_CLOCKACTIVITY | +SYSC_HAS_ENAWAKEUP |SYSC_HAS_SOFTRESET | +SYSC_HAS_AUTOIDLE ), + .idlemodes = (SIDLE_FORCE |SIDLE_NO |SIDLE_SMART ), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2420_timer_hwmod_class = { + .name ="timer" , + .sysc = &omap2420_timer_sysc, + .rev =OMAP_TIMER_IP_VERSION_1 , +}; + +/* timer1 */ +static struct omap_hwmod omap2420_timer1_hwmod; +static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { + { .irq =37 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { + { + .pa_start =0x48028000 , + .pa_end =0x48028000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { + .master = &omap2420_l4_wkup_hwmod, + .slave = &omap2420_timer1_hwmod, + .clk ="gpt1_ick" , + .addr = omap2420_timer1_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer1_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { + &omap2420_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2420_timer1_hwmod = { + .name ="timer1" , + .mpu_irqs = omap2420_timer1_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer1_mpu_irqs), + .main_clk ="gpt1_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT1_SHIFT , + .module_offs =WKUP_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT1_SHIFT , + }, + }, + .slaves = omap2420_timer1_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer1_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer2 */ +static struct omap_hwmod omap2420_timer2_hwmod; +static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { + { .irq =38 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { + { + .pa_start =0x4802a000 , + .pa_end =0x4802a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer2_hwmod, + .clk ="gpt2_ick" , + .addr = omap2420_timer2_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer2_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { + &omap2420_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2420_timer2_hwmod = { + .name ="timer2" , + .mpu_irqs = omap2420_timer2_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer2_mpu_irqs), + .main_clk ="gpt2_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT2_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT2_SHIFT , + }, + }, + .slaves = omap2420_timer2_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer2_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer3 */ +static struct omap_hwmod omap2420_timer3_hwmod; +static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { + { .irq =39 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer3_hwmod, + .clk ="gpt3_ick" , + .addr = omap2420_timer3_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer3_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { + &omap2420_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2420_timer3_hwmod = { + .name ="timer3" , + .mpu_irqs = omap2420_timer3_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer3_mpu_irqs), + .main_clk ="gpt3_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT3_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT3_SHIFT , + }, + }, + .slaves = omap2420_timer3_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer3_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer4 */ +static struct omap_hwmod omap2420_timer4_hwmod; +static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { + { .irq =40 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { + { + .pa_start =0x4807a000 , + .pa_end =0x4807a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer4_hwmod, + .clk ="gpt4_ick" , + .addr = omap2420_timer4_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer4_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { + &omap2420_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2420_timer4_hwmod = { + .name ="timer4" , + .mpu_irqs = omap2420_timer4_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer4_mpu_irqs), + .main_clk ="gpt4_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT4_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT4_SHIFT , + }, + }, + .slaves = omap2420_timer4_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer4_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer5 */ +static struct omap_hwmod omap2420_timer5_hwmod; +static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { + { .irq =41 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { + { + .pa_start =0x4807c000 , + .pa_end =0x4807c000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer5_hwmod, + .clk ="gpt5_ick" , + .addr = omap2420_timer5_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer5_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { + &omap2420_l4_core__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap2420_timer5_hwmod = { + .name ="timer5" , + .mpu_irqs = omap2420_timer5_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer5_mpu_irqs), + .main_clk ="gpt5_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT5_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT5_SHIFT , + }, + }, + .slaves = omap2420_timer5_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer5_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + + +/* timer6 */ +static struct omap_hwmod omap2420_timer6_hwmod; +static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { + { .irq =42 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { + { + .pa_start =0x4807e000 , + .pa_end =0x4807e000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer6_hwmod, + .clk ="gpt6_ick" , + .addr = omap2420_timer6_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer6_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { + &omap2420_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2420_timer6_hwmod = { + .name ="timer6" , + .mpu_irqs = omap2420_timer6_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer6_mpu_irqs), + .main_clk ="gpt6_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT6_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT6_SHIFT , + }, + }, + .slaves = omap2420_timer6_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer6_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer7 */ +static struct omap_hwmod omap2420_timer7_hwmod; +static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { + { .irq =43 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { + { + .pa_start =0x48080000 , + .pa_end =0x48080000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer7_hwmod, + .clk ="gpt7_ick" , + .addr = omap2420_timer7_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer7_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { + &omap2420_l4_core__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap2420_timer7_hwmod = { + .name ="timer7" , + .mpu_irqs = omap2420_timer7_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer7_mpu_irqs), + .main_clk ="gpt7_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT7_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT7_SHIFT , + }, + }, + .slaves = omap2420_timer7_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer7_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer8 */ +static struct omap_hwmod omap2420_timer8_hwmod; +static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { + { .irq =44 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { + { + .pa_start =0x48082000 , + .pa_end =0x48082000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer8_hwmod, + .clk ="gpt8_ick" , + .addr = omap2420_timer8_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer8_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { + &omap2420_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2420_timer8_hwmod = { + .name ="timer8" , + .mpu_irqs = omap2420_timer8_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer8_mpu_irqs), + .main_clk ="gpt8_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT8_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT8_SHIFT , + }, + }, + .slaves = omap2420_timer8_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer8_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer9 */ +static struct omap_hwmod omap2420_timer9_hwmod; +static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { + { .irq =45 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { + { + .pa_start =0x48084000 , + .pa_end =0x48084000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer9_hwmod, + .clk ="gpt9_ick" , + .addr = omap2420_timer9_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer9_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { + &omap2420_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2420_timer9_hwmod = { + .name ="timer9" , + .mpu_irqs = omap2420_timer9_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer9_mpu_irqs), + .main_clk ="gpt9_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT9_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT9_SHIFT , + }, + }, + .slaves = omap2420_timer9_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer9_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer10 */ +static struct omap_hwmod omap2420_timer10_hwmod; +static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { + { .irq =46 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { + { + .pa_start =0x48086000 , + .pa_end =0x48086000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer10_hwmod, + .clk ="gpt10_ick" , + .addr = omap2420_timer10_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer10_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { + &omap2420_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2420_timer10_hwmod = { + .name ="timer10" , + .mpu_irqs = omap2420_timer10_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer10_mpu_irqs), + .main_clk ="gpt10_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT10_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT10_SHIFT , + }, + }, + .slaves = omap2420_timer10_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer10_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer11 */ +static struct omap_hwmod omap2420_timer11_hwmod; +static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { + { .irq =47 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { + { + .pa_start =0x48088000 , + .pa_end =0x48088000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer11_hwmod, + .clk ="gpt11_ick" , + .addr = omap2420_timer11_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer11_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { + &omap2420_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2420_timer11_hwmod = { + .name ="timer11" , + .mpu_irqs = omap2420_timer11_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer11_mpu_irqs), + .main_clk ="gpt11_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT11_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT11_SHIFT , + }, + }, + .slaves = omap2420_timer11_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer11_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; + +/* timer12 */ +static struct omap_hwmod omap2420_timer12_hwmod; +static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { + { .irq =48 , }, +}; + +static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { + { + .pa_start =0x4808a000 , + .pa_end =0x4808a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_timer12_hwmod, + .clk ="gpt12_ick" , + .addr = omap2420_timer12_addrs, + .addr_cnt =ARRAY_SIZE (omap2420_timer12_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { + &omap2420_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2420_timer12_hwmod = { + .name ="timer12" , + .mpu_irqs = omap2420_timer12_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2420_timer12_mpu_irqs), + .main_clk ="gpt12_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT12_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT12_SHIFT , + }, + }, + .slaves = omap2420_timer12_slaves, + .slaves_cnt =ARRAY_SIZE (omap2420_timer12_slaves), + .class = &omap2420_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2420 ) +}; +/* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { {
@@ -1022,6 +1642,20 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l4_wkup_hwmod, &omap2420_mpu_hwmod, &omap2420_iva_hwmod, + + &omap2420_timer1_hwmod, + &omap2420_timer2_hwmod, + &omap2420_timer3_hwmod, + &omap2420_timer4_hwmod, + &omap2420_timer5_hwmod, + &omap2420_timer6_hwmod, + &omap2420_timer7_hwmod, + &omap2420_timer8_hwmod, + &omap2420_timer9_hwmod, + &omap2420_timer10_hwmod, + &omap2420_timer11_hwmod, + &omap2420_timer12_hwmod, + &omap2420_wd_timer2_hwmod, &omap2420_uart1_hwmod, &omap2420_uart2_hwmod,
arch/arm/plat-omap/include/plat/dmtimer.h +11 -0
@@ -3,6 +3,12 @@* * OMAP Dual-Mode Timers * +* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ +* Tarun Kanti DebBarma <[email protected]> +* Thara Gopinath <[email protected]> +* +* Platform device conversion and hwmod support. +* * Copyright (C) 2005 Nokia Corporation * Author: Lauri Leukkunen <[email protected]> * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 +/* +* IP revision identifier so that Highlander IP +* in OMAP4 can be distinguished. +*/ +#define OMAP_TIMER_IP_VERSION_1 0x1struct omap_dm_timer ;extern struct omap_dm_timer *gptimer_wakeup;extern struct sys_timer omap_timer;
Paul Walmsley
maintainerPATCH 2/8 OMAP2430: hwmod data: add dmtimer
In reply to Paul WalmsleyFrom: Thara Gopinath <[email protected]>
Add dmtimer data.
--- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 633 ++++++++++++++++++++++++++++ 1 files changed, 633 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_2430_data.c +633 -0
@@ -19,6 +19,7 @@#include <plat/i2c.h> #include <plat/gpio.h> #include <plat/mcspi.h> +#include <plat/dmtimer.h> #include "omap_hwmod_common_data.h"
@@ -375,6 +376,624 @@ static struct omap_hwmod omap2430_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) }; +/* Timer Common */ +static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 , + .syss_offs =0x0014 , + .sysc_flags = (SYSC_HAS_SIDLEMODE |SYSC_HAS_CLOCKACTIVITY | +SYSC_HAS_ENAWAKEUP |SYSC_HAS_SOFTRESET | +SYSC_HAS_AUTOIDLE ), + .idlemodes = (SIDLE_FORCE |SIDLE_NO |SIDLE_SMART ), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap2430_timer_hwmod_class = { + .name ="timer" , + .sysc = &omap2430_timer_sysc, + .rev =OMAP_TIMER_IP_VERSION_1 , +}; + +/* timer1 */ +static struct omap_hwmod omap2430_timer1_hwmod; +static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = { + { .irq =37 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { + { + .pa_start =0x49018000 , + .pa_end =0x49018000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { + .master = &omap2430_l4_wkup_hwmod, + .slave = &omap2430_timer1_hwmod, + .clk ="gpt1_ick" , + .addr = omap2430_timer1_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer1_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { + &omap2430_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap2430_timer1_hwmod = { + .name ="timer1" , + .mpu_irqs = omap2430_timer1_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer1_mpu_irqs), + .main_clk ="gpt1_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT1_SHIFT , + .module_offs =WKUP_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT1_SHIFT , + }, + }, + .slaves = omap2430_timer1_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer1_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer2 */ +static struct omap_hwmod omap2430_timer2_hwmod; +static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = { + { .irq =38 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = { + { + .pa_start =0x4802a000 , + .pa_end =0x4802a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer2 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer2_hwmod, + .clk ="gpt2_ick" , + .addr = omap2430_timer2_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer2_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { + &omap2430_l4_core__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap2430_timer2_hwmod = { + .name ="timer2" , + .mpu_irqs = omap2430_timer2_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer2_mpu_irqs), + .main_clk ="gpt2_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT2_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT2_SHIFT , + }, + }, + .slaves = omap2430_timer2_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer2_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer3 */ +static struct omap_hwmod omap2430_timer3_hwmod; +static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = { + { .irq =39 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = { + { + .pa_start =0x48078000 , + .pa_end =0x48078000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer3 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer3_hwmod, + .clk ="gpt3_ick" , + .addr = omap2430_timer3_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer3_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { + &omap2430_l4_core__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap2430_timer3_hwmod = { + .name ="timer3" , + .mpu_irqs = omap2430_timer3_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer3_mpu_irqs), + .main_clk ="gpt3_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT3_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT3_SHIFT , + }, + }, + .slaves = omap2430_timer3_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer3_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer4 */ +static struct omap_hwmod omap2430_timer4_hwmod; +static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = { + { .irq =40 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = { + { + .pa_start =0x4807a000 , + .pa_end =0x4807a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer4 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer4_hwmod, + .clk ="gpt4_ick" , + .addr = omap2430_timer4_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer4_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { + &omap2430_l4_core__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap2430_timer4_hwmod = { + .name ="timer4" , + .mpu_irqs = omap2430_timer4_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer4_mpu_irqs), + .main_clk ="gpt4_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT4_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT4_SHIFT , + }, + }, + .slaves = omap2430_timer4_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer4_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer5 */ +static struct omap_hwmod omap2430_timer5_hwmod; +static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = { + { .irq =41 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = { + { + .pa_start =0x4807c000 , + .pa_end =0x4807c000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer5 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer5_hwmod, + .clk ="gpt5_ick" , + .addr = omap2430_timer5_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer5_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { + &omap2430_l4_core__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap2430_timer5_hwmod = { + .name ="timer5" , + .mpu_irqs = omap2430_timer5_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer5_mpu_irqs), + .main_clk ="gpt5_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT5_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT5_SHIFT , + }, + }, + .slaves = omap2430_timer5_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer5_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer6 */ +static struct omap_hwmod omap2430_timer6_hwmod; +static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = { + { .irq =42 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = { + { + .pa_start =0x4807e000 , + .pa_end =0x4807e000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer6 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer6_hwmod, + .clk ="gpt6_ick" , + .addr = omap2430_timer6_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer6_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { + &omap2430_l4_core__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap2430_timer6_hwmod = { + .name ="timer6" , + .mpu_irqs = omap2430_timer6_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer6_mpu_irqs), + .main_clk ="gpt6_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT6_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT6_SHIFT , + }, + }, + .slaves = omap2430_timer6_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer6_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer7 */ +static struct omap_hwmod omap2430_timer7_hwmod; +static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = { + { .irq =43 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = { + { + .pa_start =0x48080000 , + .pa_end =0x48080000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer7 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer7_hwmod, + .clk ="gpt7_ick" , + .addr = omap2430_timer7_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer7_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { + &omap2430_l4_core__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap2430_timer7_hwmod = { + .name ="timer7" , + .mpu_irqs = omap2430_timer7_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer7_mpu_irqs), + .main_clk ="gpt7_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT7_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT7_SHIFT , + }, + }, + .slaves = omap2430_timer7_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer7_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer8 */ +static struct omap_hwmod omap2430_timer8_hwmod; +static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = { + { .irq =44 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = { + { + .pa_start =0x48082000 , + .pa_end =0x48082000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer8 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer8_hwmod, + .clk ="gpt8_ick" , + .addr = omap2430_timer8_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer8_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { + &omap2430_l4_core__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap2430_timer8_hwmod = { + .name ="timer8" , + .mpu_irqs = omap2430_timer8_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer8_mpu_irqs), + .main_clk ="gpt8_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT8_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT8_SHIFT , + }, + }, + .slaves = omap2430_timer8_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer8_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer9 */ +static struct omap_hwmod omap2430_timer9_hwmod; +static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = { + { .irq =45 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = { + { + .pa_start =0x48084000 , + .pa_end =0x48084000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer9 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer9_hwmod, + .clk ="gpt9_ick" , + .addr = omap2430_timer9_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer9_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { + &omap2430_l4_core__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap2430_timer9_hwmod = { + .name ="timer9" , + .mpu_irqs = omap2430_timer9_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer9_mpu_irqs), + .main_clk ="gpt9_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT9_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT9_SHIFT , + }, + }, + .slaves = omap2430_timer9_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer9_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer10 */ +static struct omap_hwmod omap2430_timer10_hwmod; +static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = { + { .irq =46 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = { + { + .pa_start =0x48086000 , + .pa_end =0x48086000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer10_hwmod, + .clk ="gpt10_ick" , + .addr = omap2430_timer10_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer10_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { + &omap2430_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap2430_timer10_hwmod = { + .name ="timer10" , + .mpu_irqs = omap2430_timer10_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer10_mpu_irqs), + .main_clk ="gpt10_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT10_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT10_SHIFT , + }, + }, + .slaves = omap2430_timer10_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer10_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer11 */ +static struct omap_hwmod omap2430_timer11_hwmod; +static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = { + { .irq =47 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = { + { + .pa_start =0x48088000 , + .pa_end =0x48088000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer11_hwmod, + .clk ="gpt11_ick" , + .addr = omap2430_timer11_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer11_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { + &omap2430_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap2430_timer11_hwmod = { + .name ="timer11" , + .mpu_irqs = omap2430_timer11_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer11_mpu_irqs), + .main_clk ="gpt11_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT11_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT11_SHIFT , + }, + }, + .slaves = omap2430_timer11_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer11_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; + +/* timer12 */ +static struct omap_hwmod omap2430_timer12_hwmod; +static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = { + { .irq =48 , }, +}; + +static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = { + { + .pa_start =0x4808a000 , + .pa_end =0x4808a000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_timer12_hwmod, + .clk ="gpt12_ick" , + .addr = omap2430_timer12_addrs, + .addr_cnt =ARRAY_SIZE (omap2430_timer12_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { + &omap2430_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap2430_timer12_hwmod = { + .name ="timer12" , + .mpu_irqs = omap2430_timer12_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap2430_timer12_mpu_irqs), + .main_clk ="gpt12_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP24XX_EN_GPT12_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP24XX_ST_GPT12_SHIFT , + }, + }, + .slaves = omap2430_timer12_slaves, + .slaves_cnt =ARRAY_SIZE (omap2430_timer12_slaves), + .class = &omap2430_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP2430 ) +}; +/* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { {
@@ -1236,6 +1855,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l4_wkup_hwmod, &omap2430_mpu_hwmod, &omap2430_iva_hwmod, + + &omap2430_timer1_hwmod, + &omap2430_timer2_hwmod, + &omap2430_timer3_hwmod, + &omap2430_timer4_hwmod, + &omap2430_timer5_hwmod, + &omap2430_timer6_hwmod, + &omap2430_timer7_hwmod, + &omap2430_timer8_hwmod, + &omap2430_timer9_hwmod, + &omap2430_timer10_hwmod, + &omap2430_timer11_hwmod, + &omap2430_timer12_hwmod, + &omap2430_wd_timer2_hwmod, &omap2430_uart1_hwmod, &omap2430_uart2_hwmod,
Paul Walmsley
maintainerPATCH 3/8 OMAP3: hwmod data: add dmtimer
In reply to Paul WalmsleyFrom: Thara Gopinath <[email protected]>
Add dmtimer data.
--- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 649 ++++++++++++++++++++++++++++ 1 files changed, 649 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +649 -0
@@ -23,6 +23,7 @@#include <plat/gpio.h> #include <plat/smartreflex.h> #include <plat/mcspi.h> +#include <plat/dmtimer.h> #include "omap_hwmod_common_data.h"
@@ -495,6 +496,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) }; +/* timer class */ +static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 , + .syss_offs =0x0014 , + .sysc_flags = (SYSC_HAS_SIDLEMODE |SYSC_HAS_CLOCKACTIVITY | +SYSC_HAS_ENAWAKEUP |SYSC_HAS_SOFTRESET | +SYSC_HAS_EMUFREE |SYSC_HAS_AUTOIDLE ), + .idlemodes = (SIDLE_FORCE |SIDLE_NO |SIDLE_SMART ), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { + .name ="timer" , + .sysc = &omap3xxx_timer_1ms_sysc, + .rev =OMAP_TIMER_IP_VERSION_1 , +}; + +static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { + .rev_offs =0x0000 , + .sysc_offs =0x0010 , + .syss_offs =0x0014 , + .sysc_flags = (SYSC_HAS_SIDLEMODE |SYSC_HAS_ENAWAKEUP | +SYSC_HAS_SOFTRESET |SYSC_HAS_AUTOIDLE ), + .idlemodes = (SIDLE_FORCE |SIDLE_NO |SIDLE_SMART ), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { + .name ="timer" , + .sysc = &omap3xxx_timer_sysc, + .rev =OMAP_TIMER_IP_VERSION_1 , +}; + +/* timer1 */ +static struct omap_hwmod omap3xxx_timer1_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = { + { .irq =37 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { + { + .pa_start =0x48318000 , + .pa_end =0x48318000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { + .master = &omap3xxx_l4_wkup_hwmod, + .slave = &omap3xxx_timer1_hwmod, + .clk ="gpt1_ick" , + .addr = omap3xxx_timer1_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer1_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer1 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { + &omap3xxx_l4_wkup__timer1, +}; + +/* timer1 hwmod */ +static struct omap_hwmod omap3xxx_timer1_hwmod = { + .name ="timer1" , + .mpu_irqs = omap3xxx_timer1_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer1_mpu_irqs), + .main_clk ="gpt1_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT1_SHIFT , + .module_offs =WKUP_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT1_SHIFT , + }, + }, + .slaves = omap3xxx_timer1_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer1_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer2 */ +static struct omap_hwmod omap3xxx_timer2_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = { + { .irq =38 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { + { + .pa_start =0x49032000 , + .pa_end =0x49032000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer2 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer2_hwmod, + .clk ="gpt2_ick" , + .addr = omap3xxx_timer2_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer2_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer2 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { + &omap3xxx_l4_per__timer2, +}; + +/* timer2 hwmod */ +static struct omap_hwmod omap3xxx_timer2_hwmod = { + .name ="timer2" , + .mpu_irqs = omap3xxx_timer2_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer2_mpu_irqs), + .main_clk ="gpt2_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT2_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT2_SHIFT , + }, + }, + .slaves = omap3xxx_timer2_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer2_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer3 */ +static struct omap_hwmod omap3xxx_timer3_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = { + { .irq =39 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { + { + .pa_start =0x49034000 , + .pa_end =0x49034000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer3 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer3_hwmod, + .clk ="gpt3_ick" , + .addr = omap3xxx_timer3_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer3_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer3 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { + &omap3xxx_l4_per__timer3, +}; + +/* timer3 hwmod */ +static struct omap_hwmod omap3xxx_timer3_hwmod = { + .name ="timer3" , + .mpu_irqs = omap3xxx_timer3_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer3_mpu_irqs), + .main_clk ="gpt3_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT3_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT3_SHIFT , + }, + }, + .slaves = omap3xxx_timer3_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer3_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer4 */ +static struct omap_hwmod omap3xxx_timer4_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = { + { .irq =40 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { + { + .pa_start =0x49036000 , + .pa_end =0x49036000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer4 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer4_hwmod, + .clk ="gpt4_ick" , + .addr = omap3xxx_timer4_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer4_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer4 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { + &omap3xxx_l4_per__timer4, +}; + +/* timer4 hwmod */ +static struct omap_hwmod omap3xxx_timer4_hwmod = { + .name ="timer4" , + .mpu_irqs = omap3xxx_timer4_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer4_mpu_irqs), + .main_clk ="gpt4_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT4_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT4_SHIFT , + }, + }, + .slaves = omap3xxx_timer4_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer4_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer5 */ +static struct omap_hwmod omap3xxx_timer5_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = { + { .irq =41 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { + { + .pa_start =0x49038000 , + .pa_end =0x49038000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer5 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer5_hwmod, + .clk ="gpt5_ick" , + .addr = omap3xxx_timer5_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer5_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer5 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { + &omap3xxx_l4_per__timer5, +}; + +/* timer5 hwmod */ +static struct omap_hwmod omap3xxx_timer5_hwmod = { + .name ="timer5" , + .mpu_irqs = omap3xxx_timer5_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer5_mpu_irqs), + .main_clk ="gpt5_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT5_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT5_SHIFT , + }, + }, + .slaves = omap3xxx_timer5_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer5_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer6 */ +static struct omap_hwmod omap3xxx_timer6_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = { + { .irq =42 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { + { + .pa_start =0x4903A000 , + .pa_end =0x4903A000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer6 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer6_hwmod, + .clk ="gpt6_ick" , + .addr = omap3xxx_timer6_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer6_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer6 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { + &omap3xxx_l4_per__timer6, +}; + +/* timer6 hwmod */ +static struct omap_hwmod omap3xxx_timer6_hwmod = { + .name ="timer6" , + .mpu_irqs = omap3xxx_timer6_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer6_mpu_irqs), + .main_clk ="gpt6_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT6_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT6_SHIFT , + }, + }, + .slaves = omap3xxx_timer6_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer6_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer7 */ +static struct omap_hwmod omap3xxx_timer7_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = { + { .irq =43 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { + { + .pa_start =0x4903C000 , + .pa_end =0x4903C000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer7 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer7_hwmod, + .clk ="gpt7_ick" , + .addr = omap3xxx_timer7_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer7_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer7 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { + &omap3xxx_l4_per__timer7, +}; + +/* timer7 hwmod */ +static struct omap_hwmod omap3xxx_timer7_hwmod = { + .name ="timer7" , + .mpu_irqs = omap3xxx_timer7_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer7_mpu_irqs), + .main_clk ="gpt7_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT7_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT7_SHIFT , + }, + }, + .slaves = omap3xxx_timer7_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer7_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer8 */ +static struct omap_hwmod omap3xxx_timer8_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = { + { .irq =44 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { + { + .pa_start =0x4903E000 , + .pa_end =0x4903E000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer8 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer8_hwmod, + .clk ="gpt8_ick" , + .addr = omap3xxx_timer8_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer8_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer8 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { + &omap3xxx_l4_per__timer8, +}; + +/* timer8 hwmod */ +static struct omap_hwmod omap3xxx_timer8_hwmod = { + .name ="timer8" , + .mpu_irqs = omap3xxx_timer8_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer8_mpu_irqs), + .main_clk ="gpt8_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT8_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT8_SHIFT , + }, + }, + .slaves = omap3xxx_timer8_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer8_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer9 */ +static struct omap_hwmod omap3xxx_timer9_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = { + { .irq =45 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { + { + .pa_start =0x49040000 , + .pa_end =0x49040000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_per -> timer9 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { + .master = &omap3xxx_l4_per_hwmod, + .slave = &omap3xxx_timer9_hwmod, + .clk ="gpt9_ick" , + .addr = omap3xxx_timer9_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer9_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer9 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { + &omap3xxx_l4_per__timer9, +}; + +/* timer9 hwmod */ +static struct omap_hwmod omap3xxx_timer9_hwmod = { + .name ="timer9" , + .mpu_irqs = omap3xxx_timer9_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer9_mpu_irqs), + .main_clk ="gpt9_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT9_SHIFT , + .module_offs =OMAP3430_PER_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT9_SHIFT , + }, + }, + .slaves = omap3xxx_timer9_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer9_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer10 */ +static struct omap_hwmod omap3xxx_timer10_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = { + { .irq =46 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = { + { + .pa_start =0x48086000 , + .pa_end =0x48086000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer10 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer10_hwmod, + .clk ="gpt10_ick" , + .addr = omap3xxx_timer10_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer10_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer10 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { + &omap3xxx_l4_core__timer10, +}; + +/* timer10 hwmod */ +static struct omap_hwmod omap3xxx_timer10_hwmod = { + .name ="timer10" , + .mpu_irqs = omap3xxx_timer10_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer10_mpu_irqs), + .main_clk ="gpt10_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT10_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT10_SHIFT , + }, + }, + .slaves = omap3xxx_timer10_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer10_slaves), + .class = &omap3xxx_timer_1ms_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer11 */ +static struct omap_hwmod omap3xxx_timer11_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = { + { .irq =47 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = { + { + .pa_start =0x48088000 , + .pa_end =0x48088000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer11 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer11_hwmod, + .clk ="gpt11_ick" , + .addr = omap3xxx_timer11_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer11_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer11 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { + &omap3xxx_l4_core__timer11, +}; + +/* timer11 hwmod */ +static struct omap_hwmod omap3xxx_timer11_hwmod = { + .name ="timer11" , + .mpu_irqs = omap3xxx_timer11_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer11_mpu_irqs), + .main_clk ="gpt11_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT11_SHIFT , + .module_offs =CORE_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT11_SHIFT , + }, + }, + .slaves = omap3xxx_timer11_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer11_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; + +/* timer12*/ +static struct omap_hwmod omap3xxx_timer12_hwmod; +static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { + { .irq =95 , }, +}; + +static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { + { + .pa_start =0x48304000 , + .pa_end =0x48304000 +SZ_1K -1 , + .flags =ADDR_TYPE_RT + }, +}; + +/* l4_core -> timer12 */ +static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_timer12_hwmod, + .clk ="gpt12_ick" , + .addr = omap3xxx_timer12_addrs, + .addr_cnt =ARRAY_SIZE (omap3xxx_timer12_addrs), + .user =OCP_USER_MPU |OCP_USER_SDMA , +}; + +/* timer12 slave port */ +static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { + &omap3xxx_l4_core__timer12, +}; + +/* timer12 hwmod */ +static struct omap_hwmod omap3xxx_timer12_hwmod = { + .name ="timer12" , + .mpu_irqs = omap3xxx_timer12_mpu_irqs, + .mpu_irqs_cnt =ARRAY_SIZE (omap3xxx_timer12_mpu_irqs), + .main_clk ="gpt12_fck" , + .prcm = { + .omap2 = { + .prcm_reg_id =1 , + .module_bit =OMAP3430_EN_GPT12_SHIFT , + .module_offs =WKUP_MOD , + .idlest_reg_id =1 , + .idlest_idle_bit =OMAP3430_ST_GPT12_SHIFT , + }, + }, + .slaves = omap3xxx_timer12_slaves, + .slaves_cnt =ARRAY_SIZE (omap3xxx_timer12_slaves), + .class = &omap3xxx_timer_hwmod_class, + .omap_chip =OMAP_CHIP_INIT (CHIP_IS_OMAP3430 ) +}; +/* l4_wkup -> wd_timer2 */ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { {
@@ -1795,6 +2430,20 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l4_wkup_hwmod, &omap3xxx_mpu_hwmod, &omap3xxx_iva_hwmod, + + &omap3xxx_timer1_hwmod, + &omap3xxx_timer2_hwmod, + &omap3xxx_timer3_hwmod, + &omap3xxx_timer4_hwmod, + &omap3xxx_timer5_hwmod, + &omap3xxx_timer6_hwmod, + &omap3xxx_timer7_hwmod, + &omap3xxx_timer8_hwmod, + &omap3xxx_timer9_hwmod, + &omap3xxx_timer10_hwmod, + &omap3xxx_timer11_hwmod, + &omap3xxx_timer12_hwmod, + &omap3xxx_wd_timer2_hwmod, &omap3xxx_uart1_hwmod, &omap3xxx_uart2_hwmod,
Paul Walmsley
maintainerPATCH 4/8 OMAP2+: hwmod: find MPU initiator hwmod during in _register()
In reply to Paul WalmsleyMove the code that looks for the MPU initiator hwmod to run during the individual hwmod _register() function. (Previously, it ran after all hwmods were registered in the omap_hwmod_late_init() function.)
This is done so code can late-initialize a few individual hwmods -- for example, for the system timer -- before the entire set of hwmods is initialized later in boot via omap_hwmod_late_init().
--- arch/arm/mach-omap2/omap_hwmod.c | 23 +++++++++++++++-------- 1 files changed, 15 insertions(+), 8 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +15 -8
@@ -1455,7 +1455,7 @@ static int _setup(struct omap_hwmod *oh, void *data)*/ static int __init _register (struct omap_hwmod *oh) { -int ret, ms_id; +int ms_id;if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -1478,9 +1478,14 @@ static int __init _register(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_REGISTERED; - ret =0 ; +/* +* XXX Rather than doing a strcmp(), this should test a flag +* set in the hwmod data, inserted by the autogenerator code. +*/ +if (!strcmp (oh->name,MPU_INITIATOR_NAME )) + mpu_oh = oh; -return ret; +return 0 ; }
@@ -1644,22 +1649,24 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)* * Must be called after omap2_clk_init(). Resolves the struct clk names * to struct clk pointers for each registered omap_hwmod. Also calls -* _setup() on each hwmod. Returns 0. +* _setup() on each hwmod. Returns 0 upon success or -EINVAL upon error. */ static int __init omap_hwmod_late_init (void ) {int r; +if (!mpu_oh) { +pr_err ("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n" , + __func__,MPU_INITIATOR_NAME ); +return -EINVAL ; + } + r =omap_hwmod_for_each (_populate_mpu_rt_base,NULL );/* XXX check return value */ r =omap_hwmod_for_each (_init_clocks,NULL );WARN (r,"omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n" ); - mpu_oh =omap_hwmod_lookup (MPU_INITIATOR_NAME ); -WARN (!mpu_oh,"omap_hwmod: could not find MPU initiator hwmod %s\n" , -MPU_INITIATOR_NAME ); -omap_hwmod_for_each (_setup,NULL );return 0 ;
PATCH 4/8 OMAP2+: hwmod: find MPU initiator hwmod during in _register()
Quoted 29 lines · Paul Walmsley
Move the code that looks for the MPU initiator hwmod to run during the individual hwmod
_register()function. (Previously, it ran after all hwmods were registered in theomap_hwmod_late_init()function.)This is done so code can late-initialize a few individual hwmods -- for example, for the system timer -- before the entire set of hwmods is initialized later in boot via
omap_hwmod_late_init().Signed-off-by Paul Walmsley<[email protected]>Cc Beno?t Cousson<[email protected]>Cc Kevin Hilman<[email protected]>--- arch/arm/mach-omap2/omap_hwmod.c | 23 +++++++++++++++-------- 1 files changed, 15 insertions(+), 8 deletions(-)arch/arm/mach-omap2/omap_hwmod.c +1
-1@@ -1455,7 +1455,7 @@ static int _setup(struct omap_hwmod *oh, void *data)*/ static int __init _register (struct omap_hwmod *oh) { -int ret, ms_id; +int ms_id;if (!oh || !oh->name || !oh->class || !oh->class->name || (oh->_state != _HWMOD_STATE_UNKNOWN))
arch/arm/mach-omap2/omap_hwmod.c static int __init _register(struct omap_hwmod *oh) · line 1483
Quoted 7 lines
arch/arm/mach-omap2/omap_hwmod.c +3
-1@@ -1478,9 +1478,14 @@ static int __init _register(struct omap_hwmod *oh) oh->_state = _HWMOD_STATE_REGISTERED; - ret =0 ; +/* +* XXX Rather than doing a strcmp(), this should test a flag +* set in the hwmod data, inserted by the autogenerator code.
What do you mean exactly? Something like a "is_mpu" field set to true for the mpu?
Since we are enforcing a consistent naming for every hwmods, that looks like a duplication of the name.
We will always named this hwmod "mpu", so the strcmp() should be enough.
But, maybe I'm missing your point.
Benoit
Quoted 8 lines
arch/arm/mach-omap2/omap_hwmod.c +4
-1+*/ +if (!strcmp (oh->name,MPU_INITIATOR_NAME )) + mpu_oh = oh; -return ret; +return 0 ; }
Paul Walmsley
maintainerPATCH 4/8 OMAP2+: hwmod: find MPU initiator hwmod during in _register()
Hello Beno?t,
Quoted 11 lines · Benoit
arch/arm/mach-omap2/omap_hwmod.c static int __init _register(struct omap_hwmod *oh) · line 1483
Quoted 3 lines · Paul Walmsley
arch/arm/mach-omap2/omap_hwmod.c +3
-0+/* +* XXX Rather than doing a strcmp(), this should test a flag +* set in the hwmod data, inserted by the autogenerator code. What do you mean exactly? Something like a "
is_mpu" field set to true for the mpu? Since we are enforcing a consistent naming for every hwmods, that looks like a duplication of the name. We will always named this hwmod "mpu", so thestrcmp()should be enough.But, maybe I'm missing your point.
I had in mind adding a new flag bit for struct omap_hwmod.flags for this purpose, mostly for these reasons:
1. Russell indicated a preference to avoid strcmp() for this type of situation during the clock code merge a few years ago
2. Testing a single bit is much more efficient than calling strcmp(), which will hopefully make life a little easier when running on an FPGA emulator
A separate field would of course work as well, but seems more heavyweight if there's only one special case.
Quoted 7 lines
arch/arm/mach-omap2/omap_hwmod.c static int __init _register(struct omap_hwmod *oh) · line 1489
Quoted 7 lines
arch/arm/mach-omap2/omap_hwmod.c +4
-1+*/ +if (!strcmp (oh->name,MPU_INITIATOR_NAME )) + mpu_oh = oh; -return ret; +return 0 ; }
- Paul
Paul Walmsley
maintainerPATCH 5/8 OMAP2+: hwmod: allow multiple calls to omap_hwmod_init()
In reply to Paul WalmsleyThere's no longer any reason why we should prevent multiple calls to omap_hwmod_init(). It is now simply used to register an array of hwmods.
This should allow a subset of hwmods (e.g., hwmods handling the system clocksource and clockevents) to be registered earlier than the remaining mass of hwmods.
--- arch/arm/mach-omap2/omap_hwmod.c | 29 ++++++++++------------------- 1 files changed, 10 insertions(+), 19 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +10 -19
@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; -/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ -static u8 inited; -/* Private functions */
@@ -1600,26 +1597,20 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),*/ int __init omap_hwmod_init (struct omap_hwmod **ohs) { -struct omap_hwmod *oh; -int r; - -if (inited) -return -EINVAL ; - - inited =1 ; +int r, i;if (!ohs)return 0 ; - oh = *ohs; -while (oh) { -if (omap_chip_is (oh->omap_chip)) { - r =_register (oh); -WARN (r,"omap_hwmod: %s: _register returned " -"%d\n" , oh->name, r); - } - oh = *++ohs; - } + i =0 ; +do { +if (!omap_chip_is (ohs[i]->omap_chip)) +continue ; + + r =_register (ohs[i]); +WARN (r,"omap_hwmod: %s: _register returned %d\n" , ohs[i]->name, + r); + }while (ohs[++i]);return 0 ; }
PATCH 5/8 OMAP2+: hwmod: allow multiple calls to omap_hwmod_init()
Quoted 7 lines · Paul Walmsley
There's no longer any reason why we should prevent multiple calls to
omap_hwmod_init(). It is now simply used to register an array of hwmods.This should allow a subset of hwmods (e.g., hwmods handling the system clocksource and clockevents) to be registered earlier than the remaining mass of hwmods.
Cool... that one was needed anyway.
It will allow potentially to split the original omapxxx_hwmod list in severals parts and thus handle the features or the infrastructure hwmods we need to init early od based on the chip capabilities.
I was considering that during the discussion with Sanjeev
(http://www.spinics.net/lists/linux-omap/msg46716.html).
Benoit
Quoted 61 lines
Signed-off-by Paul Walmsley<[email protected]>Cc Beno?t Cousson<[email protected]>Cc Kevin Hilman<[email protected]>--- arch/arm/mach-omap2/omap_hwmod.c | 29 ++++++++++------------------- 1 files changed, 10 insertions(+), 19 deletions(-)arch/arm/mach-omap2/omap_hwmod.c +10
-19@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);/* mpu_oh: used to add/remove MPU initiator from sleepdep list */ static struct omap_hwmod *mpu_oh; -/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ -static u8 inited; -/* Private functions */ @@ -1600,26 +1597,20 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),*/ int __init omap_hwmod_init (struct omap_hwmod **ohs) { -struct omap_hwmod *oh; -int r; - -if (inited) -return -EINVAL ; - - inited =1 ; +int r, i;if (!ohs)return 0 ; - oh = *ohs; -while (oh) { -if (omap_chip_is (oh->omap_chip)) { - r =_register (oh); -WARN (r,"omap_hwmod: %s: _register returned " -"%d\n" , oh->name, r); - } - oh = *++ohs; - } + i =0 ; +do { +if (!omap_chip_is (ohs[i]->omap_chip)) +continue ; + + r =_register (ohs[i]); +WARN (r,"omap_hwmod: %s: _register returned %d\n" , ohs[i]->name, + r); + }while (ohs[++i]);return 0 ; }
Paul Walmsley
maintainerPATCH 6/8 OMAP2+: hwmod: ignore attempts to re-late-init a hwmod
In reply to Paul WalmsleyPreviously, if a hwmod had already been late-initialized, and the code attempted to late-initialize the hwmod again, an error would be returned. This is not really useful behavior if we wish to allow the OMAP core code to late-init the hwmods needed for the Linux clocksources and clockevents _before_ the rest of the hwmods are late-inited. So, instead of generating errors, just ignore the attempt to re-late-initialize the hwmod.
--- arch/arm/mach-omap2/omap_hwmod.c | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +11 -8
@@ -902,17 +902,15 @@ static struct omap_hwmod *_lookup(const char *name)* @data: not used; pass NULL * * Called by omap_hwmod_late_init() (after omap2_clk_init()). -* Resolves all clock names embedded in the hwmod. Returns -EINVAL if -* the omap_hwmod has not yet been registered or if the clocks have -* already been initialized, 0 on success, or a non-zero error on -* failure. +* Resolves all clock names embedded in the hwmod. Returns 0 on +* success, or a negative error code on failure. */ static int _init_clocks (struct omap_hwmod *oh,void *data) {int ret =0 ; -if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) -return -EINVAL ; +if (oh->_state != _HWMOD_STATE_REGISTERED) +return 0 ;pr_debug ("omap_hwmod: %s: looking up clocks\n" , oh->name);
@@ -1351,14 +1349,16 @@ static int _shutdown(struct omap_hwmod *oh)* @oh: struct omap_hwmod * * * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh -* OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the -* wrong state or returns 0. +* OCP_SYSCONFIG register. Returns 0. */ static int _setup (struct omap_hwmod *oh,void *data) {int i, r;u8 postsetup_state; +if (oh->_state != _HWMOD_STATE_CLKS_INITED) +return 0 ; +/* Set iclk autoidle mode */ if (oh->slaves_cnt >0 ) {for (i =0 ; i < oh->slaves_cnt; i++) {
@@ -1624,6 +1624,9 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)*/ static int __init _populate_mpu_rt_base (struct omap_hwmod *oh,void *data) { +if (oh->_state != _HWMOD_STATE_REGISTERED) +return 0 ; +if (oh->_int_flags & _HWMOD_NO_MPU_PORT)return 0 ;
Paul Walmsley
maintainerPATCH 7/8 OMAP2+: hwmod: add ability to late-init individual hwmods
In reply to Paul WalmsleyAdd omap_hwmod_late_init_one(), which is intended for use early in boot to selectively init the hwmods needed for system clocksources and clockevents, and any other hwmod that is needed in early boot. omap_hwmod_late_init() can then be called later in the boot process. The point is to minimize the amount of code that needs to be run early in the boot process.
--- arch/arm/mach-omap2/omap_hwmod.c | 53 +++++++++++++++++++++++++- arch/arm/plat-omap/include/plat/omap_hwmod.h | 3 + 2 files changed, 54 insertions(+), 2 deletions(-)
arch/arm/mach-omap2/omap_hwmod.c +51 -2
@@ -1639,6 +1639,55 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) }/** +* omap_hwmod_late_init_one - XXX +* +* XXX Fix this documentation +* +* Must be called after omap2_clk_init(). Resolves the struct clk +* names to struct clk pointers for each registered omap_hwmod. Also +* calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon +* success. +*/ +int __init omap_hwmod_late_init_one (const char *oh_name) +{ +struct omap_hwmod *oh; +int r; + +pr_debug ("omap_hwmod: %s: %s\n" , oh_name, __func__); + +if (!mpu_oh) { +pr_err ("omap_hwmod: %s: cannot late_init_one: MPU initiator hwmod %s not yet registered\n" , + oh_name,MPU_INITIATOR_NAME ); +return -EINVAL ; + } + + oh =_lookup (oh_name); +if (!oh) { +WARN (1 ,"omap_hwmod: %s: hwmod not yet registered\n" , oh_name); +return -EINVAL ; + } + +if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) +omap_hwmod_late_init_one (MPU_INITIATOR_NAME ); + + r =_populate_mpu_rt_base (oh,NULL ); +if (IS_ERR_VALUE (r)) { +WARN (1 ,"omap_hwmod: %s: couldn't set mpu_rt_base\n" , oh_name); +return -EINVAL ; + } + + r =_init_clocks (oh,NULL ); +if (IS_ERR_VALUE (r)) { +WARN (1 ,"omap_hwmod: %s: couldn't init clocks\n" , oh_name); +return -EINVAL ; + } + +_setup (oh,NULL ); + +return 0 ; +} + +/** * omap_hwmod_late_init - do some post-clock framework initialization * * Must be called after omap2_clk_init(). Resolves the struct clk names
@@ -1657,9 +1706,9 @@ static int __init omap_hwmod_late_init(void) r =omap_hwmod_for_each (_populate_mpu_rt_base,NULL ); -/* XXX check return value */ r =omap_hwmod_for_each (_init_clocks,NULL ); -WARN (r,"omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n" ); +WARN (IS_ERR_VALUE (r), +"omap_hwmod: %s: _init_clocks failed\n" , __func__);omap_hwmod_for_each (_setup,NULL );
arch/arm/plat-omap/include/plat/omap_hwmod.h +3 -0
@@ -30,6 +30,7 @@#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H#include <linux/kernel.h> +#include <linux/init.h> #include <linux/list.h> #include <linux/ioport.h> #include <linux/spinlock.h>
@@ -540,6 +541,8 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name);int omap_hwmod_for_each (int (*fn)(struct omap_hwmod *oh,void *data),void *data); +int __init omap_hwmod_late_init_one (const char *name); +int omap_hwmod_enable (struct omap_hwmod *oh);int _omap_hwmod_enable (struct omap_hwmod *oh);int omap_hwmod_idle (struct omap_hwmod *oh);
Tony Lindgren
maintainerPATCH 7/8 OMAP2+: hwmod: add ability to late-init individual hwmods
Hi,
arch/arm/mach-omap2/omap_hwmod.c static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) · line 1651
Quoted 3 lines · Paul Walmsley
arch/arm/mach-omap2/omap_hwmod.c +1
-0+int __init omap_hwmod_late_init_one (const char *oh_name)
How about the following naming changes to avoid confusion:
omap_hwmod_init -> omap_hwmod_registeromap_hwmod_late_init -> omap_hwmod_initomap_hwmod_late_init_one -> omap_hwmod_init_one
This is because "late_init" gets actually called very early during the boot.
Regards,
Tony
Paul Walmsley
maintainerPATCH 7/8 OMAP2+: hwmod: add ability to late-init individual hwmods
Quoted 7 lines · Tony Lindgren
arch/arm/mach-omap2/omap_hwmod.c static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) · line 1651
Quoted 3 lines · Paul Walmsley
arch/arm/mach-omap2/omap_hwmod.c +1
-0+int __init omap_hwmod_late_init_one (const char *oh_name)How about the following naming changes to avoid confusion:
Quoted 6 lines
omap_hwmod_init->omap_hwmod_registeromap_hwmod_late_init->omap_hwmod_initomap_hwmod_late_init_one->omap_hwmod_init_oneThis is because "
late_init" gets actually called very early during the boot.
Sounds good to me. Will write a patch to make this change,
- Paul
Paul Walmsley
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
In reply to Paul WalmsleyLate-initialize the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to late-initialize all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)
--- arch/arm/mach-omap2/timer-gp.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/timer-gp.c +7 -1
@@ -40,10 +40,11 @@#include <plat/dmtimer.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <plat/common.h> #include "timer-gp.h" +#include <plat/omap_hwmod.h> -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12
@@ -133,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +const char *clockevent_hwmod_name; inited =1 ; + clockevent_hwmod_name = (gptimer_id ==12 ) ?"timer12" :"timer1" ; +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;
@@ -250,6 +255,7 @@ static void __init omap2_gp_timer_init(void) BUG_ON(!twd_base); }#endif +omap_dm_timer_init ();omap2_gp_clockevent_init ();
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Paul,
Quoted 46 lines
-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Wednesday, February 23, 2011 12:42 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Cc: Tony Lindgren; Kevin Hilman; Santosh Shilimkar; Beno?t Cousson
Subject: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initLate-initialize the GPTIMER hwmod used for the clockevent source immediately
before it is used. This avoids the need to late-initialize all of the hwmods
until the boot process is further along. (In general, we want to defer
as much as possible until late in the boot process.)Signed-off-by Paul Walmsley <[email protected]>Cc Beno?t Cousson <[email protected]>Cc Tony Lindgren <[email protected]>Cc Kevin Hilman <[email protected]>Cc Santosh Shilimkar <[email protected]>--- arch/arm/mach-omap2/timer-gp.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)arch/arm/mach- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
omap2/timer-gp.c
index 0fc550e..a4e51a2 100644arch/arm/mach-omap2/timer-gp.c +2
-1@@ -40,10 +40,11 @@#include <plat/dmtimer.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <plat/common.h> #include "timer-gp.h" +#include <plat/omap_hwmod.h> -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -133,9 +134,13 @@ static void __initomap2_gp_clockevent_init (void) {
arch/arm/mach-omap2/timer-gp.c static void __init · line 145
Quoted 10 lines
arch/arm/mach-omap2/timer-gp.c +4
-0u32 tick_rate;int src; +const char *clockevent_hwmod_name; inited =1 ; + clockevent_hwmod_name = (gptimer_id ==12 ) ?"timer12" :"timer1" ; +omap_hwmod_late_init_one (clockevent_hwmod_name); +
Do we need above hard-coding ? This takes away flexibility of choosing system timer from board files, right ?
Am I missing something here?
Quoted 12 lines
arch/arm/mach-omap2/timer-gp.c +0
-0gptimer =omap_dm_timer_request_specific (gptimer_id);arch/arm/mach-omap2/timer-gp.c +1
-0BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;@@ -250,6 +255,7 @@ static void __init omap2_gp_timer_init(void) BUG_ON(!twd_base); }#endif +omap_dm_timer_init ();omap2_gp_clockevent_init ();
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Quoted 71 lines
-----Original Message-----
From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh
Sent: Wednesday, February 23, 2011 2:23 PM
To: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm- kernel at lists.infradead.org
Cc: Tony Lindgren; Hilman, Kevin; Cousson, Benoit
Subject: RE: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initPaul,
Quoted 46 lines
-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Wednesday, February 23, 2011 12:42 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Cc: Tony Lindgren; Kevin Hilman; Santosh Shilimkar; Beno?t Cousson
Subject: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initLate-initialize the GPTIMER hwmod used for the clockevent source immediately
before it is used. This avoids the need to late-initialize all of the hwmods
until the boot process is further along. (In general, we want to defer
as much as possible until late in the boot process.)Signed-off-by Paul Walmsley <[email protected]>Cc Beno?t Cousson <[email protected]>Cc Tony Lindgren <[email protected]>Cc Kevin Hilman <[email protected]>Cc Santosh Shilimkar <[email protected]>--- arch/arm/mach-omap2/timer-gp.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)arch/arm/mach- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
omap2/timer-gp.c
index 0fc550e..a4e51a2 100644arch/arm/mach-omap2/timer-gp.c +2
-1@@ -40,10 +40,11 @@#include <plat/dmtimer.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <plat/common.h> #include "timer-gp.h" +#include <plat/omap_hwmod.h> -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -133,9 +134,13 @@ static void __initomap2_gp_clockevent_init (void) {arch/arm/mach-omap2/timer-gp.c static void __init · line 145
Quoted 10 lines
arch/arm/mach-omap2/timer-gp.c +4
-0u32 tick_rate;int src; +const char *clockevent_hwmod_name; inited =1 ; + clockevent_hwmod_name = (gptimer_id ==12 ) ?"timer12" :"timer1" ; +omap_hwmod_late_init_one (clockevent_hwmod_name); +Do we need above hard-coding ? This takes away flexibility of choosing system timer from board files, right ?
Quoted 1 line
Am I missing something here?
Currently, omap_4430sdp_init_early() and omap3_beagle_init_irq() calls omap2_gp_clockevent_set_gptimer(id) to set it to 1 and 12 respectively. For OMAP24xx, the default settings of gptimer_id=1 is taken. In summary, we are losing the flexibility.
Instead we could have something like:sscanf(clockevent_hwmod_name, "timer%2d", &gptimer_id);
--
Tarun
Quoted 19 lines
Quoted 8 lines
arch/arm/mach-omap2/timer-gp.c +0
-0gptimer =omap_dm_timer_request_specific (gptimer_id);arch/arm/mach-omap2/timer-gp.c +0
-0BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;arch/arm/mach-omap2/timer-gp.c static void __init omap2_gp_timer_init(void) · line 261
Quoted 7 lines
arch/arm/mach-omap2/timer-gp.c +1
-0@@ -250,6 +255,7 @@ static void __init omap2_gp_timer_init(void) BUG_ON(!twd_base); }#endif +omap_dm_timer_init ();omap2_gp_clockevent_init ();--
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Paul Walmsley
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
In reply to Santosh ShilimkarHello Santosh,
Quoted 39 lines · Santosh Shilimkar
Quoted 25 lines
-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Wednesday, February 23, 2011 12:42 PMarch/arm/mach- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
omap2/timer-gp.c
index 0fc550e..a4e51a2 100644arch/arm/mach-omap2/timer-gp.c +2
-1@@ -40,10 +40,11 @@#include <plat/dmtimer.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <plat/common.h> #include "timer-gp.h" +#include <plat/omap_hwmod.h> -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -133,9 +134,13 @@ static void __initomap2_gp_clockevent_init (void) {arch/arm/mach-omap2/timer-gp.c static void __init · line 145
Quoted 10 lines
arch/arm/mach-omap2/timer-gp.c +4
-0u32 tick_rate;int src; +const char *clockevent_hwmod_name; inited =1 ; + clockevent_hwmod_name = (gptimer_id ==12 ) ?"timer12" :"timer1" ; +omap_hwmod_late_init_one (clockevent_hwmod_name); +Do we need above hard-coding ? This takes away flexibility of choosing system timer from board files, right ?
Quoted 1 line
Am I missing something here?
You are absolutely right. That was an error on my part. I propose the following change instead - please let me know what you think.
- Paul
From: Paul Walmsley <[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
Late-initialize the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to late-initialize all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)
This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma <[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
--- arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/timer-gp.c +6 -1
@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12
@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +char *clockevent_hwmod_name; inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;
Signature · 1 line
1.7.2.3
Paul Walmsley
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Hello Santosh,
Quoted 2 lines · Paul Walmsley
I propose the following change instead - please let me know what you think.
Oops - the patch I sent you was not completely refreshed in the local tree. Here is the correct one.
- Paul
From: Paul Walmsley <[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
Late-initialize the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to late-initialize all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)
This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma <[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
--- arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/timer-gp.c +6 -1
@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12
@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +char clockevent_hwmod_name[8 ];/* 8 = sizeof("timerXX0") */ inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;
Signature · 1 line
1.7.2.3
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Quoted 12 lines
-----Original Message-----
From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
owner at vger.kernel.org] On Behalf Of Paul Walmsley
Sent: Thursday, February 24, 2011 1:45 PM
To: Shilimkar, Santosh
Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Tony Lindgren; Hilman, Kevin; Cousson, Benoit
Subject: RE: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initHello Santosh,
Quoted 7 lines
Quoted 2 lines · Paul Walmsley
I propose the following change instead - please let me know what you think.
Oops - the patch I sent you was not completely refreshed in the local tree. Here is the correct one.
I have tested on OMAP3 and works fine.
On OMAP2, I guess there is different issue for which it does not work. --
Tarun
Quoted 64 lines
From: Paul Walmsley <[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer initLate-initialize the GPTIMER hwmod used for the clockevent source immediately
before it is used. This avoids the need to late-initialize all of the hwmods
until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma <[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
Signed-off-by Paul Walmsley <[email protected]>Cc Beno?t Cousson <[email protected]>Cc Tony Lindgren <[email protected]>Cc Kevin Hilman <[email protected]>Cc Santosh Shilimkar <[email protected]>Cc Tarun Kanti DebBarma <[email protected]>--- arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)arch/arm/mach-omap2/timer- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
gp.c
index 7b7c268..b289d53 100644arch/arm/mach-omap2/timer-gp.c +6
-2@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +char clockevent_hwmod_name[8 ];/* 8 = sizeof("timerXX0") */ inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer; --1.7.2.3
Paul Walmsley
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Quoted 2 lines · Tarun Kanti
I have tested on OMAP3 and works fine.
On OMAP2, I guess there is different issue for which it does not work.
Works fine for me on N800. Boot log below.
- Paul
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Linux version 2.6.38-rc5-00065-g8a2f1db (paul at twilight) (gcc version 4.3.2 (Sourcery G++ Lite 2008q3-72) ) #180 Thu Feb 24 01:56:43 MST1 [ 0.000000] CPU: ARMv6-compatible processor [4107b362] revision 2 (ARMv6TEJ), cr=00c5387f [ 0.000000] CPU: VIPT aliasing data cache, unknown instruction cache [ 0.000000] Machine: Nokia N800 [ 0.000000] Ignoring unrecognised tag 0x414f4d50 [ 0.000000] bootconsole [earlycon0] enabled [ 0.000000] Memory policy: ECC disabled, Data cache writeback [ 0.000000] OMAP2420 [ 0.000000] [ 0.000000] SRAM: Mapped pa 0x40200000 to va 0xfe400000 size: 0xa0000 [ 0.000000] On node 0 totalpages: 32768 [ 0.000000] free_area_init_node: node 0, pgdat c03c9850, node_mem_map c08ee000 [ 0.000000] Normal zone: 256 pages used for memmap [ 0.000000] Normal zone: 0 pages reserved [ 0.000000] Normal zone: 32512 pages, LIFO batch:7 [ 0.000000] Clocking rate (Crystal/DPLL/MPU): 19.2/658/329 MHz [ 0.000000] GPMC revision 2.0 [ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 [ 0.000000] pcpu-alloc: [0] 0 [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 [ 0.000000] Kernel command line: root=/dev/mmcblk0p1 rootwait console=ttyO2,115200 earlyprintk debug init=/bin/bash [ 0.000000] PID hash table entries: 512 (order: -1, 2048 bytes) [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) [ 0.000000] Memory: 128MB = 128MB total [ 0.000000] Memory: 120756k/120756k available, 10316k reserved, 0K highmem [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB) [ 0.000000] DMA : 0xffc00000 - 0xffe00000 ( 2 MB) [ 0.000000] vmalloc : 0xc8800000 - 0xf8000000 ( 760 MB) [ 0.000000] lowmem : 0xc0000000 - 0xc8000000 ( 128 MB) [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB) [ 0.000000] .init : 0xc0008000 - 0xc002c000 ( 144 kB) [ 0.000000] .text : 0xc002c000 - 0xc0390bfc (3475 kB) [ 0.000000] .data : 0xc0392000 - 0xc03c9f20 ( 224 kB) [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: at arch/arm/kernel/hw_breakpoint.c:142 get_debug_arch+0x3c/0x68() [ 0.000000] CPUID feature registers not supported. Assuming v6 debug is present. [ 0.000000] Modules linked in: [ 0.000000] [<c003cbd8>] (unwind_backtrace+0x0/0xec) from [<c005bce4>] (warn_slowpath_common+0x4c/0x64) [ 0.000000] [<c005bce4>] (warn_slowpath_common+0x4c/0x64) from [<c005bd7c>] (warn_slowpath_fmt+0x2c/0x3c) [ 0.000000] [<c005bd7c>] (warn_slowpath_fmt+0x2c/0x3c) from [<c003d4c4>] (get_debug_arch+0x3c/0x68) [ 0.000000] [<c003d4c4>] (get_debug_arch+0x3c/0x68) from [<c003d4f8>] (debug_arch_supported+0x8/0x20) [ 0.000000] [<c003d4f8>] (debug_arch_supported+0x8/0x20) from [<c003d5b4>] (hw_breakpoint_slots+0xc/0x50) [ 0.000000] [<c003d5b4>] (hw_breakpoint_slots+0xc/0x50) from [<c0013f50>] (init_hw_breakpoint+0xc/0x98) [ 0.000000] [<c0013f50>] (init_hw_breakpoint+0xc/0x98) from [<c0013ee8>] (perf_event_init+0xa8/0x104) [ 0.000000] [<c0013ee8>] (perf_event_init+0xa8/0x104) from [<c0008ad0>] (start_kernel+0x150/0x2d4) [ 0.000000] [<c0008ad0>] (start_kernel+0x150/0x2d4) from [<80008034>] (0x80008034) [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]--- [ 0.000000] NR_IRQS:402 [ 0.000000] IRQ: Found an INTC at 0xfa0fe000 (revision 2.0) with 96 interrupts [ 0.000000] Total of 96 interrupts on 1 active controller [ 0.000000] OMAP clockevent source: GPTIMER1 at 32000 Hz [ 0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms [ 0.000000] Console: colour dummy device 80x30 [ 0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar [ 0.000000] ... MAX_LOCKDEP_SUBCLASSES: 8 [ 0.000000] ... MAX_LOCK_DEPTH: 48 [ 0.000000] ... MAX_LOCKDEP_KEYS: 8191 [ 0.000000] ... CLASSHASH_SIZE: 4096 [ 0.000000] ... MAX_LOCKDEP_ENTRIES: 16384 [ 0.000000] ... MAX_LOCKDEP_CHAINS: 32768 [ 0.000000] ... CHAINHASH_SIZE: 16384 [ 0.000000] memory used by lock dependency info: 3695 kB [ 0.000000] per task-struct memory footprint: 1152 bytes [ 0.057922] Calibrating delay loop... 319.32 BogoMIPS (lpj=1249280) [ 0.246368] pid_max: default: 32768 minimum: 301 [ 0.252197] Security Framework initialized [ 0.257080] Mount-cache hash table entries: 512 [ 0.269104] CPU: Testing write buffer coherency: ok [ 0.276367] hw perfevents: enabled with v6 PMU driver, 3 counters available [ 0.302276] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l3_main [ 0.309844] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_core [ 0.317352] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_wkup [ 0.326904] omap_voltage_early_init: voltage driver support not added [ 0.345275] print_constraints: dummy: [ 0.362274] omap_device: omap_gpio.0: new worst case activate latency 0: 274658 [ 0.371246] OMAP GPIO hardware version 1.8 [ 0.376678] OMAP GPIO hardware version 1.8 [ 0.381958] OMAP GPIO hardware version 1.8 [ 0.387115] OMAP GPIO hardware version 1.8 [ 0.415069] omap_mux_init: Add partition: #1: core, flags: 3 [ 0.430908] omap_device: omap_uart.0: new worst case activate latency 0: 30517 [ 0.431518] omap_device: omap_uart.0: new worst case deactivate latency 0: 30517 [ 0.456970] hw-breakpoint: found 6 breakpoint and 1 watchpoint registers. [ 0.464233] hw-breakpoint: maximum watchpoint size is 4 bytes. [ 0.487426] pm_dbg_init: only OMAP3 supported [ 0.495056] OMAP DMA hardware revision 2.0 [ 0.588745] bio: create slab <bio-0> at 0 [ 0.610168] SCSI subsystem initialized [ 0.615234] omap_device: omap2_mcspi.1: new worst case activate latency 0: 30517 [ 0.626403] omap_device: omap2_mcspi.1: new worst case deactivate latency 0: 30517 [ 0.644897] usbcore: registered new interface driver usbfs [ 0.653442] usbcore: registered new interface driver hub [ 0.661193] usbcore: registered new device driver usb [ 0.670562] omap_device: omap_i2c.1: new worst case activate latency 0: 30517 [ 0.678344] omap_i2c omap_i2c.1: bus 1 rev3.4 at 400 kHz [ 0.690063] omap_device: omap_i2c.1: new worst case deactivate latency 0: 30517 [ 0.698272] omap_i2c omap_i2c.2: bus 2 rev3.4 at 400 kHz [ 0.714233] Switching to clocksource 32k_counter [ 0.724639] Switched to NOHz mode on CPU #0 [ 0.873931] NetWinder Floating Point Emulator V0.97 (double precision) [ 0.886077] PMU: registered new PMU device of type 0 [ 0.910186] VFS: Disk quotas dquot_6.5.2 [ 0.914581] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) [ 0.924377] JFFS2 version 2.2. (NAND) (SUMMARY) [ 0.933959] msgmni has been set to 235 [ 0.946075] io scheduler noop registered [ 0.950256] io scheduler deadline registered [ 0.955078] io scheduler cfq registered (default) [ 0.970458] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.992492] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 72) is a OMAP UART0 [ 1.003753] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 73) is a OMAP UART1 [ 1.014373] omap_uart.2: ttyO2 at MMIO 0x4806e000 (irq = 74) is a OMAP UART2 [ 1.022521] console [ttyO2] enabled, bootconsole disabled [ 1.022521] console [ttyO2] enabled, bootconsole disabled [ 1.043029] omap_rng omap_rng: OMAP Random Number Generator ver. 40 [ 1.126007] brd: module loaded [ 1.167938] loop: module loaded [ 1.174621] Menelaus rev 2.2 [ 1.178771] omap_device: omap_i2c.1: new worst case activate latency 0: 152587 [ 1.210601] mtdoops: mtd device (mtddev=name/number) must be supplied [ 1.218261] omap2-nand driver initializing [ 1.224273] OneNAND driver initializing [ 1.230163] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base c8880000 [ 1.240386] OneNAND Manufacturer: Samsung (0xec) [ 1.245330] Muxed OneNAND(DDP) 256MB 1.8V 16-bit (0x48) [ 1.250885] OneNAND version = 0x0011 [ 1.254638] Chip support all block unlock [ 1.259124] onenand_wait: controller error! state 15 ctrl 0x0440 intr 0x8000 [ 1.268249] Scanning device for bad blocks [ 1.489715] Creating 5 MTD partitions on "omap2-onenand": [ 1.495574] 0x000000000000-0x000000020000 : "bootloader" [ 1.516876] 0x000000020000-0x000000080000 : "config" [ 1.532928] 0x000000080000-0x000000280000 : "kernel" [ 1.549377] 0x000000280000-0x000000680000 : "initfs" [ 1.565887] 0x000000680000-0x000010000000 : "rootfs" [ 1.614929] usbcore: registered new interface driver cdc_wdm [ 1.621063] Initializing USB Mass Storage driver... [ 1.627868] usbcore: registered new interface driver usb-storage [ 1.634338] USB Mass Storage support registered. [ 1.642150] usbcore: registered new interface driver libusual [ 1.649902] usbcore: registered new interface driver usbtest [ 1.655883] udc: OMAP UDC driver, version: 4 October 2004 (iso) (dma) [ 1.670349] mousedev: PS/2 mouse device common for all mice [ 1.689666] i2c /dev entries driver [ 1.701751] Driver for 1-wire Dallas network protocol. [ 1.711456] omap_device: omap_wdt.-1: new worst case activate latency 0: 30517 [ 1.722717] OMAP Watchdog Timer Rev 0x11: initial timeout 60 sec [ 1.729309] omap_device: omap_wdt.-1: new worst case deactivate latency 0: 30517 [ 1.836456] usbcore: registered new interface driver usbhid [ 1.842498] usbhid: USB HID core driver [ 1.846618] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 2 [ 1.870056] omap_voltage_late_init: Voltage driver support not added [ 1.876892] Power Management for OMAP2 initializing [ 1.882019] PRCM revision 1.0 [ 1.922149] clock: disabling unused clocks to save power [ 1.930511] mmci-omap mmci-omap.0: command timeout (CMD52) [ 1.937744] mmci-omap mmci-omap.0: command timeout (CMD52) [ 1.951721] mmci-omap mmci-omap.0: command timeout (CMD5) [ 1.958282] mmci-omap mmci-omap.0: command timeout (CMD5) [ 1.964660] mmci-omap mmci-omap.0: command timeout (CMD5) [ 1.970367] mmci-omap mmci-omap.0: command timeout (CMD5) [ 1.976776] mmci-omap mmci-omap.0: command timeout (CMD5) [ 1.983428] drivers/rtc/hctosys.c: unable to open rtc device (rtc0) [ 1.997192] Waiting for root device /dev/mmcblk0p1... [ 2.112396] mmc0: host does not support reading read-only switch. assuming write-enable. [ 2.121459] mmc0: new SD card at address e624 [ 2.131561] mmcblk0: mmc0:e624 SD01G 968 MiB [ 2.148162] mmcblk0: p1 [ 2.225433] mmci-omap mmci-omap.0: command timeout (CMD52) [ 2.232391] mmci-omap mmci-omap.0: command timeout (CMD52) [ 2.245483] mmci-omap mmci-omap.0: command timeout (CMD8) [ 2.252319] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.260284] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.266082] EXT3-fs: barriers not enabled [ 2.270416] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.277099] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.285156] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.293060] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.304626] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.312713] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.320800] mmci-omap mmci-omap.0: command timeout (CMD1) [ 2.415588] mmci-omap mmci-omap.0: command timeout (CMD52) [ 2.422454] mmci-omap mmci-omap.0: command timeout (CMD52) [ 2.433319] mmci-omap mmci-omap.0: command timeout (CMD8) [ 2.440856] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.447601] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.455078] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.461761] mmci-omap mmci-omap.0: command timeout (CMD5) [ 2.468475] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.476287] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.483978] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.489959] kjournald starting. Commit interval 5 seconds [ 2.496856] mmci-omap mmci-omap.0: command timeout (CMD55) [ 2.504852] mmci-omap mmci-omap.0: command timeout (CMD1) [ 2.511108] EXT3-fs (mmcblk0p1): using internal journal [ 2.516754] EXT3-fs (mmcblk0p1): recovery complete [ 2.540832] EXT3-fs (mmcblk0p1): mounted filesystem with ordered data mode [ 2.549194] VFS: Mounted root (ext3 filesystem) on device 179:1. [ 2.556030] Freeing init memory: 144K
root@(none):/#
Tony Lindgren
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
In reply to DebBarma, Tarun KantiQuoted 2 lines · DebBarma, Tarun Kanti
I have tested on OMAP3 and works fine.
On OMAP2, I guess there is different issue for which it does not work.
That's because commit 15490ef8ff8fd22d677cb5d4f6a98e5a79118dba changed things to include CONFIG_CPU_32v6K. And this means that omap-for-linus won't boot on omap2 currently using omap2plus_defconfig. The master branch boots because of the patches in omap-testing.
To boot test omap-for-linus, you can temporarily merge in the omap-testing branch that has the pending patches from Russell to make non-6K ARMv6 processors work with CONFIG_CPU_32v6K.
Regards,
Tony
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
Quoted 13 lines
-----Original Message-----
From: Tony Lindgren [mailto:tony at atomide.com]
Sent: Thursday, February 24, 2011 9:11 PM
To: DebBarma, Tarun Kanti
Cc: Paul Walmsley; Shilimkar, Santosh; linux-omap at vger.kernel.org; linux- arm-kernel at lists.infradead.org; Hilman, Kevin; Cousson, Benoit
Subject: Re: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initQuoted 2 lines · DebBarma, Tarun Kanti
I have tested on OMAP3 and works fine.
On OMAP2, I guess there is different issue for which it does not work.
Quoted 8 lines
That's because commit
15490ef8ff8fd22d677cb5d4f6a98e5a79118dbachanged things to includeCONFIG_CPU_32v6K. And this means that omap-for-linus won't boot on omap2 currently usingomap2plus_defconfig. The master branch boots because of the patches in omap-testing.To boot test omap-for-linus, you can temporarily merge in the omap-testing branch that has the pending patches from Russell to make non-6K ARMv6 processors work with
CONFIG_CPU_32v6K.
I have re-based the changes on omap-testing branch and tested on OMAP2420 and OMAP2430.
--
Tarun
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer init
In reply to Paul WalmsleyQuoted 45 lines
-----Original Message-----
From: Paul Walmsley [mailto:paul at pwsan.com]
Sent: Thursday, February 24, 2011 1:45 PM
To: Santosh Shilimkar
Cc: linux-omap at vger.kernel.org; linux-arm-
kernel at lists.infradead.org; Tony Lindgren; Kevin Hilman; Benoit Cousson
Subject: RE: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmodright before timer initHello Santosh,
Quoted 1 line · Paul Walmsley
I propose the following change instead - please let me know what
you
Quoted 1 line
think.
Oops - the patch I sent you was not completely refreshed in the local
tree. Here is the correct one.- Paul
From: Paul Walmsley <[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer initLate-initialize the GPTIMER hwmod used for the clockevent source immediately
before it is used. This avoids the need to late-initialize all of the hwmods
until the boot process is further along. (In general, we want to defer
as much as possible until late in the boot process.)This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma <[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
Quoted 7 lines
Signed-off-by Paul Walmsley <[email protected]>Cc Beno?t Cousson <[email protected]>Cc Tony Lindgren <[email protected]>Cc Kevin Hilman <[email protected]>Cc Santosh Shilimkar <[email protected]>Cc Tarun Kanti DebBarma <[email protected]>---
Looks good and thanks for fixing this one.
Quoted 38 lines
arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)arch/arm/mach- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
omap2/timer-gp.c
index 7b7c268..b289d53 100644arch/arm/mach-omap2/timer-gp.c +6
-1@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -132,9 +133,13 @@ static void __initomap2_gp_clockevent_init (void) {u32 tick_rate;int src; +char clockevent_hwmod_name[8 ];/* 8 = sizeof("timerXX0") */ inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL );
gptimer_wakeup= gptimer;
--
1.7.2.3
PATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
In reply to Paul WalmsleyQuoted 8 lines
-----Original Message-----
From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- owner at vger.kernel.org] On Behalf Of Paul Walmsley
Sent: Wednesday, February 23, 2011 12:42 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Cc: Tony Lindgren; Hilman, Kevin; Shilimkar, Santosh; Cousson, Benoit
Subject: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
I am not able to apply this patch.
Patch 1-7 applied successfully on top of:
04aa67d Merge branch 'for-tony' of git://gitorious.org/usb/usb into omap-for-linus
--
Tarun
Quoted 63 lines
Late-initialize the GPTIMER hwmod used for the clockevent source immediately
before it is used. This avoids the need to late-initialize all of the hwmods
until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)Signed-off-by Paul Walmsley <[email protected]>Cc Beno?t Cousson <[email protected]>Cc Tony Lindgren <[email protected]>Cc Kevin Hilman <[email protected]>Cc Santosh Shilimkar <[email protected]>--- arch/arm/mach-omap2/timer-gp.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-)arch/arm/mach-omap2/timer- renamed from arch/arm/mach-omap2/timer-gp.c +0
-0
gp.c
index 0fc550e..a4e51a2 100644arch/arm/mach-omap2/timer-gp.c +7
-2@@ -40,10 +40,11 @@#include <plat/dmtimer.h> #include <asm/localtimer.h> #include <asm/sched_clock.h> +#include <plat/common.h> #include "timer-gp.h" +#include <plat/omap_hwmod.h> -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -133,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +const char *clockevent_hwmod_name; inited =1 ; + clockevent_hwmod_name = (gptimer_id ==12 ) ?"timer12" :"timer1" ; +omap_hwmod_late_init_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;@@ -250,6 +255,7 @@ static void __init omap2_gp_timer_init(void) BUG_ON(!twd_base); }#endif +omap_dm_timer_init ();omap2_gp_clockevent_init (); --To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo at vger.kernel.org
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Paul Walmsley
maintainerPATCH 8/8 OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer init
Hello Tarun
Quoted 11 lines · Tarun Kanti
Quoted 8 lines
-----Original Message-----
From: linux-omap-owner at vger.kernel.org [mailto:linux-omap- owner at vger.kernel.org] On Behalf Of Paul Walmsley
Sent: Wednesday, February 23, 2011 12:42 PM
To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Cc: Tony Lindgren; Hilman, Kevin; Shilimkar, Santosh; Cousson, Benoit
Subject: [PATCH 8/8] OMAP2+: clockevent: late-init GPTIMER clockevent hwmod right before timer initI am not able to apply this patch.
Patch 1-7 applied successfully on top of:
04aa67d Merge branch 'for-tony' ofgit://gitorious.org/usb/usbinto omap-for-linus
Thanks, it seems that there was a stray header change left in my original tree. The updated version is here:
http://marc.info/?l=linux-omap&m=129853532211359&w=2
- Paul
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
In reply to Paul WalmsleyHi Paul,
Quoted 10 lines · Paul Walmsley
Hello,
This series adds the ability to late-initialize individual hwmods. The goal here is for clockevent (and eventually clocksource) hwmods to be late-initialized individually, and right before they are needed, in the timer init code. Then
omap_hwmod_late_init(), which late-inits the rest of the hwmods, is intended to run as an initcall -- much later in the boot process.
Quoted 5 lines
This series includes the OMAP2/3 hwmod data for the GPTIMERs that Tarun posted earlier. This data is necessary for this new code to avoid warnings during boot.
Boot-tested on N800, OMAP34xx Beagleboard and OMAP4430ES2 Panda.
I'm testing it on 4430sdp, and I have the following warning:
[ 0.000000] omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck. [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: at arch/arm/mach-omap2/timer-gp.c:157 omap2_gp_timer_init+0x80/0x190() [ 0.000000] timer-gp: omap_dm_timer_set_source() failed [ 0.000000] Modules linked in: [ 0.000000] [<c0062a6c>] (unwind_backtrace+0x0/0xec) from [<c009422c>] (warn_slowpath_common+0x4c/0x64) [ 0.000000] [<c009422c>] (warn_slowpath_common+0x4c/0x64) from [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) [ 0.000000] [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) [ 0.000000] [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) from [<c000c0dc>] (time_init+0x20/0x30) [ 0.000000] [<c000c0dc>] (time_init+0x20/0x30) from [<c0008cbc>] (start_kernel+0x1a4/0x30c) [ 0.000000] [<c0008cbc>] (start_kernel+0x1a4/0x30c) from [<80008038>] (0x80008038) [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]--- [ 0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
Regards,
Benoit
Paul Walmsley
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Salut Beno?t,
Quoted 17 lines · Benoit
Quoted 8 lines · Paul Walmsley
This series adds the ability to late-initialize individual hwmods. The goal here is for clockevent (and eventually clocksource) hwmods to be late-initialized individually, and right before they are needed, in the timer init code. Then
omap_hwmod_late_init(), which late-inits the rest of the hwmods, is intended to run as an initcall -- much later in the boot process.Quoted 5 lines
This series includes the OMAP2/3 hwmod data for the GPTIMERs that Tarun posted earlier. This data is necessary for this new code to avoid warnings during boot.
Boot-tested on N800, OMAP34xx Beagleboard and OMAP4430ES2 Panda.
I'm testing it on 4430sdp, and I have the following warning:
Quoted 13 lines
[ 0.000000] omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck. [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: at arch/arm/mach-omap2/timer-gp.c:157 omap2_gp_timer_init+0x80/0x190() [ 0.000000] timer-gp: omap_dm_timer_set_source() failed [ 0.000000] Modules linked in: [ 0.000000] [<c0062a6c>] (unwind_backtrace+0x0/0xec) from [<c009422c>] (warn_slowpath_common+0x4c/0x64) [ 0.000000] [<c009422c>] (warn_slowpath_common+0x4c/0x64) from [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) [ 0.000000] [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) [ 0.000000] [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) from [<c000c0dc>] (time_init+0x20/0x30) [ 0.000000] [<c000c0dc>] (time_init+0x20/0x30) from [<c0008cbc>] (start_kernel+0x1a4/0x30c) [ 0.000000] [<c0008cbc>] (start_kernel+0x1a4/0x30c) from [<80008038>] (0x80008038) [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]--- [ 0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
This is due to commit 3b03b58dab847883e6b9a431558c7d8e43fa94c6 ("OMAP4:
hwmod data: Prevent timer1 to be reset and idle during init"). Could you please try reverting this and see if the warning disappears?
Tony, I guess the omap-for-linus branch will probably need to get rebuilt to drop that patch, once this series is merged...
- Paul
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Salut Paul,
Quoted 35 lines · Paul Walmsley
Salut Beno?t,
Quoted 17 lines · Benoit
Quoted 8 lines · Paul Walmsley
This series adds the ability to late-initialize individual hwmods. The goal here is for clockevent (and eventually clocksource) hwmods to be late-initialized individually, and right before they are needed, in the timer init code. Then
omap_hwmod_late_init(), which late-inits the rest of the hwmods, is intended to run as an initcall -- much later in the boot process.Quoted 5 lines
This series includes the OMAP2/3 hwmod data for the GPTIMERs that Tarun posted earlier. This data is necessary for this new code to avoid warnings during boot.
Boot-tested on N800, OMAP34xx Beagleboard and OMAP4430ES2 Panda.
I'm testing it on 4430sdp, and I have the following warning:
Quoted 13 lines
[ 0.000000] omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck. [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: at arch/arm/mach-omap2/timer-gp.c:157 omap2_gp_timer_init+0x80/0x190() [ 0.000000] timer-gp: omap_dm_timer_set_source() failed [ 0.000000] Modules linked in: [ 0.000000] [<c0062a6c>] (unwind_backtrace+0x0/0xec) from [<c009422c>] (warn_slowpath_common+0x4c/0x64) [ 0.000000] [<c009422c>] (warn_slowpath_common+0x4c/0x64) from [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) [ 0.000000] [<c00942c4>] (warn_slowpath_fmt+0x2c/0x3c) from [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) [ 0.000000] [<c0010e30>] (omap2_gp_timer_init+0x80/0x190) from [<c000c0dc>] (time_init+0x20/0x30) [ 0.000000] [<c000c0dc>] (time_init+0x20/0x30) from [<c0008cbc>] (start_kernel+0x1a4/0x30c) [ 0.000000] [<c0008cbc>] (start_kernel+0x1a4/0x30c) from [<80008038>] (0x80008038) [ 0.000000] ---[ end trace 1b75b31a2719ed1c ]--- [ 0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
Quoted 3 lines
This is due to commit
3b03b58dab847883e6b9a431558c7d8e43fa94c6("OMAP4:
hwmod data: Prevent timer1 to be reset and idle during init"). Could you please try reverting this and see if the warning disappears?
Thanks, this is indeed fixing this warning. I didn't see these two patches were exclusive.
Thanks,
Benoit
Quoted 5 lines
Tony, I guess the omap-for-linus branch will probably need to get rebuilt to drop that patch, once this series is merged...
- Paul
Tony Lindgren
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Quoted 3 lines · Paul Walmsley
Quoted 2 lines
Tony, I guess the omap-for-linus branch will probably need to get rebuilt to drop that patch, once this series is merged...
Let's rather apply a fix or revert instead than start messing with omap-for-linus. That branch is supposed to be a stable base for others to base their branches on.
Tony
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Quoted 7 lines · Tony Lindgren
Quoted 3 lines · Paul Walmsley
Quoted 2 lines
Tony, I guess the omap-for-linus branch will probably need to get rebuilt to drop that patch, once this series is merged...
Let's rather apply a fix or revert instead than start messing with omap-for-linus. That branch is supposed to be a stable base for others to base their branches on.
Paul,
It is probably better to add the fix in that series at the same time you setup the timer hwmod in the following commit 38698bef5454. It will avoid breaking bisect.
Regards,
Benoit
---
From 35e0aff709a7ea27c65e08c7bd5d904d3193ec75 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Set up the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to set up all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)
This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma <[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
Revert as well commit 3b03b58dab847883e6b9a431558c7d8e43fa94c6:
"OMAP4: hwmod data: Prevent timer1 to be reset and idle during init", that is not longer needed since hwmod is setup before timer used it.
--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 - arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 2 files changed, 6 insertions(+), 2 deletions(-)
(quoted diff) +0 -0
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 2c58827..b4d3b3c 100644
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0 -0
@@ -3989,7 +3989,6 @@ static struct omap_hwmod_ocp_if
*omap44xx_timer1_slaves[] = {
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_timer1_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
.main_clk = "timer1_fck",
arch/arm/mach-omap2/timer-gp.c +6 -1
@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12
@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +char clockevent_hwmod_name[8 ];/* 8 = sizeof("timerXX0") */ inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_setup_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;
Signature · 1 line
1.7.0.4
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Paul,
Quoted 9 lines · Benoit
Quoted 7 lines · Tony Lindgren
Quoted 3 lines · Paul Walmsley
Quoted 2 lines
Tony, I guess the omap-for-linus branch will probably need to get rebuilt to drop that patch, once this series is merged...
Let's rather apply a fix or revert instead than start messing with omap-for-linus. That branch is supposed to be a stable base for others to base their branches on.
Quoted 5 lines
Paul,
It is probably better to add the fix in that series at the same time you setup the timer hwmod in the following commit
38698bef5454. It will avoid breaking bisect.
It looks like your branch is now merged without the revert or the fix proposed below, so the warning is still there :-(
Tony,
Do you plan to re-merge this branch or should I just send a revert on top of it?
Thanks,
Benoit
Quoted 86 lines
Regards,
Benoit---
From35e0aff709a7ea27c65e08c7bd5d904d3193ec75Mon Sep 17 00:00:00 2001
From: Paul Walmsley<[email protected]>
Date: Wed, 23 Feb 2011 00:14:08 -0700
Subject: [PATCH] OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bitSet up the GPTIMER hwmod used for the clockevent source immediately before it is used. This avoids the need to set up all of the hwmods until the boot process is further along. (In general, we want to defer as much as possible until late in the boot process.)
This second version fixes a bug pointed out by Santosh Shilimkar <[email protected]>, that would cause the kernel to use an incorrect timer hwmod name if the selected GPTIMER was not 1 or 12 - thanks Santosh. Also, Tarun Kanti DebBarma<[email protected]> pointed out that the original patch did not apply cleanly; this has now been fixed.
Revert as well commit
3b03b58dab847883e6b9a431558c7d8e43fa94c6:
"OMAP4: hwmod data: Prevent timer1 to be reset and idle during init", that is not longer needed since hwmod is setup before timer used it.Signed-off-by Paul Walmsley<[email protected]>Cc Beno??t Cousson<[email protected]>Cc Tony Lindgren<[email protected]>Cc Kevin Hilman<[email protected]>Cc Santosh Shilimkar<[email protected]>Acked-by Santosh Shilimkar<[email protected]>Cc Tarun Kanti DebBarma<[email protected]>--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 - arch/arm/mach-omap2/timer-gp.c | 7 ++++++- 2 files changed, 6 insertions(+), 2 deletions(-)arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0
-1@@ -3989,7 +3989,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {static struct omap_hwmod omap44xx_timer1_hwmod = { .name ="timer1" , .class =&omap44xx_timer_1ms_hwmod_class, - .flags =HWMOD_INIT_NO_IDLE |HWMOD_INIT_NO_RESET , .mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs_cnt =ARRAY_SIZE (omap44xx_timer1_irqs),.main_clk = "timer1_fck",arch/arm/mach-omap2/timer-gp.c +6
-1@@ -39,10 +39,11 @@#include <asm/mach/time.h> #include <plat/dmtimer.h> #include <asm/localtimer.h> +#include <plat/common.h> +#include <plat/omap_hwmod.h> #include "timer-gp.h" -#include <plat/common.h> /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ #define MAX_GPTIMER_ID 12@@ -132,9 +133,13 @@ static void __init omap2_gp_clockevent_init(void) {u32 tick_rate;int src; +char clockevent_hwmod_name[8 ];/* 8 = sizeof("timerXX0") */ inited =1 ; +sprintf (clockevent_hwmod_name,"timer%d" , gptimer_id); +omap_hwmod_setup_one (clockevent_hwmod_name); + gptimer =omap_dm_timer_request_specific (gptimer_id);BUG_ON (gptimer ==NULL ); gptimer_wakeup = gptimer;
Tony Lindgren
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Quoted 4 lines · Cousson, Benoit
Tony,
Do you plan to re-merge this branch or should I just send a revert on top of it?
Please just provide a patch.
Regards,
Tony
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Quoted 11 lines · Tony Lindgren
Quoted 4 lines · Cousson, Benoit
Tony,
Do you plan to re-merge this branch or should I just send a revert on top of it?Please just provide a patch.
Regards,
Tony
I posted it with the one from Rajendra to fix the regression with Santosh's series, but I do need Santosh to rebase and re-test the second one.
Meanwhile, here is the revert.
Benoit
---
Paul Walmsley
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
Quoted 8 lines · Benoit
Quoted 1 line
From
aa22c44486c12c388eb96e9fe9b1476267856006Mon Sep 17 00:00:00 2001From: Benoit Cousson <[email protected]>
Date: Fri, 4 Mar 2011 16:01:43 +0100
Subject: [PATCH 1/2] Revert "OMAP4: hwmod data: Prevent timer1 to be reset and idle during init"The following commit: 38698be:
OMAP2+: clockevent: set up GPTIMER clockevent hwmod right before timer init
Quoted 7 lines
Fixed properly the issue with early init for the timer1
So reverts commit
3b03b58dab847883e6b9a431558c7d8e43fa94c6that is now generated a warning at boot time.Signed-off-by Benoit Cousson <[email protected]>Cc Paul Walmsley <[email protected]>
Quoted 19 lines
--- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-)arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0
-1@@ -4005,7 +4005,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {static struct omap_hwmod omap44xx_timer1_hwmod = { .name ="timer1" , .class = &omap44xx_timer_1ms_hwmod_class, - .flags =HWMOD_INIT_NO_IDLE |HWMOD_INIT_NO_RESET , .mpu_irqs = omap44xx_timer1_irqs, .mpu_irqs_cnt =ARRAY_SIZE (omap44xx_timer1_irqs), .main_clk ="timer1_fck" ,Signature · 1 line
1.7.0.4
- Paul
cover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
In reply to Cousson, BenoitQuoted 20 lines
-----Original Message-----
From: Cousson, Benoit [mailto:b-cousson at ti.com]
Sent: Friday, March 04, 2011 10:09 PM
To: Tony Lindgren
Cc: Paul Walmsley; linux-omap at vger.kernel.org; linux-arm- kernel at lists.infradead.org; Hilman, Kevin; Shilimkar, Santosh; Gopinath, Thara; DebBarma, Tarun Kanti; Nayak, Rajendra
Subject: Re: [PATCH 0/8] OMAP2+: hwmod/clockevent: allow late-init of individual hwmodsQuoted 4 lines · Tony Lindgren
Quoted 3 lines · Cousson, Benoit
Tony,
Do you plan to re-merge this branch or should I just send arevert
Quoted 4 lines
Quoted 1 line
on top of it?
Please just provide a patch.
Quoted 8 lines
Quoted 3 lines
Regards,
Tony
I posted it with the one from Rajendra to fix the regression with Santosh's series, but I do need Santosh to rebase and re-test the second one.
I just replied on another thread Benoit. I still see an issue with MPU OFF.
Regards,
Santosh
Tony Lindgren
maintainercover OMAP2+: hwmod/clockevent: allow late-init of individual hwmods
In reply to Paul WalmsleyQuoted 9 lines · Paul Walmsley
Hello,
This series adds the ability to late-initialize individual hwmods. The goal here is for clockevent (and eventually clocksource) hwmods to be late-initialized individually, and right before they are needed, in the timer init code. Then
omap_hwmod_late_init(), which late-inits the rest of the hwmods, is intended to run as an initcall -- much later in the boot process.
Sounds good to me!
Tony