arm64: arch_timer: Add workaround for hisilicon-161601 erratum

Erratum Hisilicon-161601 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected.

The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.

The workaround is enabled if the hisilicon,erratum-161601 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.hisilicon-161601 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information.

Fix some description for fsl erratum a008585.

v2: Significant rework based on feedback, including seperate the fsl erratum a008585
to another patch, update the erratum name and remove unwanted code.

v3: Significant rework based on feedback, including fix some alignment problem, make the
#define __hisi_161601_read_reg to be private to the .c file instead of being globally visible, add more accurate annotation and modify a bit of logical format to enable arch_timer_read_ool_enabled, remove the kernel commandline parameter clocksource.arm_arch_timer.hisilicon-161601.

v5: Theoretically the erratum should not occur more than twice in succession when reading
the system counter, but it is possible that some interrupts may lead to more than twice read errors, triggering the warning, so setting the number of retries to 50 which is far beyond the number of iterations the loop has been observed to take.

Signed-off-by Ding Tianhong <[email protected]>

---
 Documentation/arm64/silicon-errata.txt |  1 +
 arch/arm64/include/asm/arch_timer.h    |  2 +-
 drivers/clocksource/Kconfig            |  9 +++++
 drivers/clocksource/arm_arch_timer.c   | 70 +++++++++++++++++++++++++++++++---
 4 files changed, 76 insertions(+), 6 deletions(-)

Documentation/arm64/silicon-errata.txt +1 -0

index 405da11..1c1a95f 100644
@@ -63,3 +63,4 @@ stable kernels.
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
 |                |                 |                 |                         |
 | Freescale/NXP  | LS2080A/LS1043A | A-008585        | FSL_ERRATUM_A008585     |
+| Hisilicon      | Hip0{5,6,7}     | #161601         | HISILICON_ERRATUM_161601|

arch/arm64/include/asm/arch_timer.h +1 -1

index f882c7c..ebf4cde 100644
@@ -29,7 +29,7 @@
 
 #include <clocksource/arm_arch_timer.h>
 
-#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
 extern struct static_key_false arch_timer_read_ool_enabled;
 #define needs_unstable_timer_counter_workaround() \
 	static_branch_unlikely(&arch_timer_read_ool_enabled)

drivers/clocksource/Kconfig +9 -0

index 4866f7a..162d820 100644
@@ -335,6 +335,15 @@ config FSL_ERRATUM_A008585
 	  value").  The workaround will only be active if the
 	  fsl,erratum-a008585 property is found in the timer node.
 
+config HISILICON_ERRATUM_161601
+	bool "Workaround for Hisilicon Erratum 161601"
+	default y
+	depends on ARM_ARCH_TIMER && ARM64
+	help
+	  This option enables a workaround for Hisilicon Erratum
+	  161601. The workaround will be active if the hisilicon,erratum-161601
+	  property is found in the timer node.
+
 config ARM_GLOBAL_TIMER
 	bool "Support for the ARM global timer" if COMPILE_TEST
 	select CLKSRC_OF if OF

drivers/clocksource/arm_arch_timer.c +0 -0

index e7406ad..9a82496 100644
@@ -95,15 +95,18 @@ static int __init early_evtstrm_cfg(char *buf)
  * Architected system timer support.
  */

drivers/clocksource/arm_arch_timer.c +5 -0

+	.read_cntp_tval_el0 = hisi_161601_read_cntp_tval_el0,
+	.read_cntv_tval_el0 = hisi_161601_read_cntv_tval_el0,
+	.read_cntvct_el0 = hisi_161601_read_cntvct_el0,
+};
+#endif /* CONFIG_HISILICON_ERRATUM_161601 */

drivers/clocksource/arm_arch_timer.c +5 -1

-#ifdef CONFIG_FSL_ERRATUM_A008585
+#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
 		/*
 		 * Don't use the vdso fastpath if errata require using
 		 * the out-of-line counter accessor.

@@ -909,10 +960,19 @@ static int __init arch_timer_of_init(struct device_node *np)
 #ifdef CONFIG_FSL_ERRATUM_A008585
 	if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
 		timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
+#endif
+
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+	if (!timer_unstable_counter_workaround && of_property_read_bool(np, "hisilicon,erratum-161601"))

drivers/clocksource/arm_arch_timer.c +0 -0

 	}
 #endif
 

From: Hanjun Guo <[email protected]>

Add hisi timer specific erratum fixes.

v3: add hisilicon erratum 161601 for ACPI mode.

v4: update some data structures.

Signed-off-by Hanjun Guo <[email protected]>

Signed-off-by Ding Tianhong <[email protected]>

---
 drivers/clocksource/arm_arch_timer.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

drivers/clocksource/arm_arch_timer.c +0 -0

index 212bfa5..7b15d2a 100644
@@ -1089,10 +1089,28 @@ struct gtdt_arch_timer_fixup {
 	void *context;
 };
 

drivers/clocksource/arm_arch_timer.c +8 -0

+}
+#endif
+
 /* note: this needs to be updated according to the doc of OEM ID
  * and TABLE ID for different board.
  */
 struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = {
+#ifdef CONFIG_HISILICON_ERRATUM_161601
+	{"HISI", "hip05", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
+	{"HISI", "hip06", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
+	{"HISI", "hip07", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
+#endif
 
 
 

};

void __init arch_timer_acpi_quirks_handler(char *oem_id,

Erratum Hisilicon-161601 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected.

The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.

v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
Significant rework based on feedback, including seperate the fsl erratum a008585 to another patch, update the erratum name and remove unwanted code.

v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of being globally visible. After discussion with Marc and Will, a consensus decision was made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum, and make some generic name more specific, export timer_unstable_counter_workaround for module access.

Significant rework based on feedback, including fix some alignment problem, make the #define __hisi_161601_read_reg to be private to the .c file instead of being globally visible, add more accurate annotation and modify a bit of logical format to enable arch_timer_read_ool_enabled, remove the kernel commandline parameter clocksource.arm_arch_timer.hisilicon-161601.

Introduce a generic aquick framework for erratum in ACPI mode.

v4: rename the quirk handler parameter to make it more generic, and
avoid break loop when handling the quirk becasue it need to support multi quirks handler.

update some data structures for acpi mode.

v5: Adapt the new kernel-parameters.txt for latest kernel version.
Set the retries of reread system counter to 50, because it is possible that some interrupts may lead to more than twice read errors and break the loop, it will trigger the warning, so we set the number of retries far beyond the number of iterations the loop has been observed to take.

Ding Tianhong (4):
arm64: arch_timer: Add device tree binding for hisilicon-161601
erratum
arm64: arch_timer: Introduce a generic erratum handing mechanism for

    fsl-a008585
  arm64: arch_timer: Work around Erratum Hisilicon-161601
  arm64: arch timer: Add timer erratum property for Hip05-d02 and
    Hip06-d03

Hanjun Guo (2):
arm64: arch_timer: apci: Introduce a generic aquirk framework for
erratum
arm64: arch_timer: acpi: add hisi timer errata data

Hi Ding,

Quoted 50 lines · Ding Tianhong

Erratum Hisilicon-161601 says that the ARM generic timer counter "has the potential to contain an erroneous value when the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected.

The workaround is to reread the system count registers until the value of the second read is larger than the first one by less than 32, the system counter can be guaranteed not to return wrong value twice by back-to-back read and the error value is always larger than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.

v2: Introducing a new generic erratum handling mechanism for fsl,a008585 and hisilicon,161601.
Significant rework based on feedback, including seperate the fsl erratum a008585 to another patch, update the erratum name and remove unwanted code.

v3: Introducing the erratum_workaround_set_sne generic function for fsl erratum a008585
and make the #define __fsl_a008585_read_reg to be private to the .c file instead of being globally visible. After discussion with Marc and Will, a consensus decision was made to remove the commandline parameter for enabling fsl,erratum-a008585 erratum, and make some generic name more specific, export timer_unstable_counter_workaround for module access.

Significant rework based on feedback, including fix some alignment problem, make the #define __hisi_161601_read_reg to be private to the .c file instead of being globally visible, add more accurate annotation and modify a bit of logical format to enable arch_timer_read_ool_enabled, remove the kernel commandline parameter clocksource.arm_arch_timer.hisilicon-161601.

Introduce a generic aquick framework for erratum in ACPI mode.

v4: rename the quirk handler parameter to make it more generic, and
avoid break loop when handling the quirk becasue it need to support multi quirks handler.

update some data structures for acpi mode.

v5: Adapt the new kernel-parameters.txt for latest kernel version.
Set the retries of reread system counter to 50, because it is possible that some interrupts may lead to more than twice read errors and break the loop, it will trigger the warning, so we set the number of retries far beyond the number of iterations the loop has been observed to take.

Ding Tianhong (4):
arm64: arch_timer: Add device tree binding for hisilicon-161601
erratum
arm64: arch_timer: Introduce a generic erratum handing mechanism for

    fsl-a008585
  arm64: arch_timer: Work around Erratum Hisilicon-161601
  arm64: arch timer: Add timer erratum property for Hip05-d02 and
    Hip06-d03

Quoted 4 lines

Hanjun Guo (2):
arm64: arch_timer: apci: Introduce a generic aquirk framework for
erratum
arm64: arch_timer: acpi: add hisi timer errata data

Since the ACPI code is conflict with Fuwei's GTDT patch set, let's split this patch set into two parts, one is the DT based code, and the other is the ACPI part, I will rebase ACPI code on top of Fuwei's patch set so please go upstream first.

Thanks
Hanjun

.