arm64: rk3399: enable SPL with ATF support

Add spl support for rk3399.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/Kconfig                                |   1 +
 arch/arm/dts/rk3399.dtsi                        |  24 ++++
 arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 118 ++++++++++++++++++
 arch/arm/mach-rockchip/Kconfig                  |   2 +
 arch/arm/mach-rockchip/Makefile                 |   1 +
 arch/arm/mach-rockchip/rk3399-board-spl.c       | 157 ++++++++++++++++++++++++
 configs/evb-rk3399_defconfig                    |  17 +++
 drivers/clk/rockchip/clk_rk3399.c               |  42 ++++++-
 drivers/pinctrl/rockchip/pinctrl_rk3399.c       | 106 ----------------
 include/configs/rk3399_common.h                 |  11 ++
 include/dt-bindings/clock/rk3399-cru.h          |  16 ++-
 11 files changed, 382 insertions(+), 113 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/rk3399-board-spl.c

RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from coreboot, support 4GB lpddr3 in this version.

Signed-off-by Kever Yang <[email protected]>

---

 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h  |  188 +++
 arch/arm/mach-rockchip/rk3399/Makefile             |    1 +
 arch/arm/mach-rockchip/rk3399/sdram-lpddr3-4GB.inc | 1565 ++++++++++++++++++++
 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c       | 1121 ++++++++++++++
 4 files changed, 2875 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
 create mode 100644 arch/arm/mach-rockchip/rk3399/sdram-lpddr3-4GB.inc
 create mode 100644 arch/arm/mach-rockchip/rk3399/sdram_rk3399.c

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file +0 -0

new file mode 100644
index 0000000..fab0faf

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file +14 -0

+};
+
+struct rk3399_ddr_pctl_regs {
+       u32 denali_ctl[332];
+};
+
+struct rk3399_ddr_publ_regs {
+       u32 denali_phy[959];
+};
+
+struct rk3399_ddr_pi_regs {
+       u32 denali_pi[200];
+};
+union noc_ddrtiminga0 {

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file +55 -0

+};
+
+union noc_ddrtimingb0 {
+       u32 d32;
+       struct {
+               unsigned rdtowr : 5;
+               unsigned reserved0 : 3;
+               unsigned wrtord : 5;
+               unsigned reserved1 : 3;
+               unsigned rrd : 4;
+               unsigned reserved2 : 4;
+               unsigned faw : 6;
+               unsigned reserved3 : 2;
+       } b;
+};
+
+union noc_ddrtimingc0 {
+       u32 d32;
+       struct {
+               unsigned burstpenalty : 4;
+               unsigned reserved0 : 4;
+               unsigned wrtomwr : 6;
+               unsigned reserved1 : 18;
+       } b;
+};
+
+union noc_devtodev0 {
+       u32 d32;
+       struct {
+               unsigned busrdtord : 3;
+               unsigned reserved0 : 1;
+               unsigned busrdtowr : 3;
+               unsigned reserved1 : 1;
+               unsigned buswrtord : 3;
+               unsigned reserved2 : 1;
+               unsigned buswrtowr : 3;
+               unsigned reserved3 : 17;
+       } b;
+};
+
+union noc_ddrmode {
+       u32 d32;
+       struct {
+               unsigned autoprecharge : 1;
+               unsigned bypassfiltering : 1;
+               unsigned fawbank : 1;
+               unsigned burstsize : 2;
+               unsigned mwrsize : 2;
+               unsigned reserved2 : 1;
+               unsigned forceorder : 8;
+               unsigned forceorderstate : 8;
+               unsigned reserved3 : 8;
+       } b;
+};
+

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file +12 -0

+       union noc_ddrtiminga0 ddrtiminga0;
+       union noc_ddrtimingb0 ddrtimingb0;
+       union noc_ddrtimingc0 ddrtimingc0;
+       union noc_devtodev0 devtodev0;
+       union noc_ddrmode ddrmode;
+       u32 agingx0;
+};
+
+struct rk3399_ddr_cic_regs {
+       u32 cic_ctrl0;
+       u32 cic_ctrl1;
+       u32 cic_idle_th;

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h new file +24 -0

+        * row_3_4 = 0: normal die, power of 2
+        */
+       unsigned char row_3_4;
+       unsigned char cs0_row;
+       unsigned char cs1_row;
+       unsigned int ddrconfig;
+       struct rk3399_msch_timings noc_timings;
+};
+
+struct rk3399_sdram_params {
+       struct rk3399_sdram_channel ch[2];
+       unsigned int ddr_freq;
+       unsigned char dramtype;
+       unsigned char num_channels;
+       unsigned char stride;
+       unsigned char odt;
+       /* align 8 byte */
+       struct rk3399_ddr_pctl_regs pctl_regs;
+       /* align 8 byte */
+       struct rk3399_ddr_pi_regs pi_regs;
+       /* align 8 byte */
+       struct rk3399_ddr_publ_regs phy_regs;
+       /* used for align 8byte for next struct */
+       unsigned int align_8;

arch/arm/mach-rockchip/rk3399/sdram-lpddr3-4GB.inc new file +14 -0

@@ -0,0 +1,1565 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +1 -0

new file mode 100644
index 0000000..67a92cc
@@ -0,0 +1,1121 @@
+/*

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +30 -0

+#include <asm/arch/sdram_rk3399.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/grf_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDRC0_BASE_ADDR         0xffa80000
+#define SERVER_MSCH0_BASE_ADDR  0xffa84000
+#define DDRC1_BASE_ADDR         0xffa88000
+#define SERVER_MSCH1_BASE_ADDR  0xffa8c000
+
+#define DDR_PI_OFFSET                  0x800
+#define DDR_PHY_OFFSET                 0x2000
+#define DDRC0_PI_BASE_ADDR             (DDRC0_BASE_ADDR + DDR_PI_OFFSET)
+#define DDRC0_PHY_BASE_ADDR            (DDRC0_BASE_ADDR + DDR_PHY_OFFSET)
+#define DDRC1_PI_BASE_ADDR             (DDRC1_BASE_ADDR + DDR_PI_OFFSET)
+#define DDRC1_PHY_BASE_ADDR            (DDRC1_BASE_ADDR + DDR_PHY_OFFSET)
+
+#define PMUCRU_BASE             0xff750000
+#define CRU_BASE                0xff760000
+#define PMUGRF_BASE             0xff320000
+#define PMUSGRF_BASE            0xff330000
+#define CIC_BASE_ADDR          0xff620000
+
+static struct rk3399_pmucru * const pmucru_ptr = (void *)PMUCRU_BASE;
+static struct rk3399_cru * const cru_ptr = (void *)CRU_BASE;
+static struct rk3399_pmugrf_regs * const rk3399_pmugrf = (void *)PMUGRF_BASE;
+static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE;

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +41 -0

+
+/*
+ * sys_reg bitfield struct
+ * [31]                row_3_4_ch1
+ * [30]                row_3_4_ch0
+ * [29:28]     chinfo
+ * [27]                rank_ch1
+ * [26:25]     col_ch1
+ * [24]                bk_ch1
+ * [23:22]     cs0_row_ch1
+ * [21:20]     cs1_row_ch1
+ * [19:18]     bw_ch1
+ * [17:16]     dbw_ch1;
+ * [15:13]     ddrtype
+ * [12]                channelnum
+ * [11]                rank_ch0
+ * [10:9]      col_ch0
+ * [8]         bk_ch0
+ * [7:6]       cs0_row_ch0
+ * [5:4]       cs1_row_ch0
+ * [3:2]       bw_ch0
+ * [1:0]       dbw_ch0
+*/
+#define SYS_REG_ENC_ROW_3_4(n, ch)     ((n) << (30 + (ch)))
+#define SYS_REG_DEC_ROW_3_4(n, ch)     ((n >> (30 + ch)) & 0x1)
+#define SYS_REG_ENC_CHINFO(ch)         (1 << (28 + (ch)))
+#define SYS_REG_ENC_DDRTYPE(n)         ((n) << 13)
+#define SYS_REG_ENC_NUM_CH(n)          (((n) - 1) << 12)
+#define SYS_REG_DEC_NUM_CH(n)          (1 + ((n >> 12) & 0x1))
+#define SYS_REG_ENC_RANK(n, ch)                (((n) - 1) << (11 + ((ch) * 16)))
+#define SYS_REG_DEC_RANK(n, ch)                (1 + ((n >> (11 + 16 * ch)) & 0x1))
+#define SYS_REG_ENC_COL(n, ch)         (((n) - 9) << (9 + ((ch) * 16)))
+#define SYS_REG_DEC_COL(n, ch)         (9 + ((n >> (9 + 16 * ch)) & 0x3))
+#define SYS_REG_ENC_BK(n, ch)          (((n) == 3 ? 0 : 1) \
+                                               << (8 + ((ch) * 16)))
+#define SYS_REG_DEC_BK(n, ch)          (3 - ((n >> (8 + 16 * ch)) & 0x1))
+#define SYS_REG_ENC_CS0_ROW(n, ch)     (((n) - 13) << (6 + ((ch) * 16)))
+#define SYS_REG_DEC_CS0_ROW(n, ch)     (13 + ((n >> (6 + 16 * ch)) & 0x3))
+#define SYS_REG_ENC_CS1_ROW(n, ch)     (((n) - 13) << (4 + ((ch) * 16)))
+#define SYS_REG_DEC_CS1_ROW(n, ch)     (13 + ((n >> (4 + 16 * ch)) & 0x3))
+#define SYS_REG_ENC_BW(n, ch)          ((2 >> (n)) << (2 + ((ch) * 16)))

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +5 -0

+
+#ifdef CONFIG_SPL_BUILD
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+       int i;

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +21 -0

+
+               /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
+               setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
+               setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
+               setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
+       } else {
+               /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
+               clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
+               clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
+               clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
+               clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
+
+               /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
+               clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
+               clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
+               clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
+       }
+}
+
+static void set_memory_map(u32 channel,
+                          const struct rk3399_sdram_params *sdram_params)

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +156 -0

+               row = 16;
+       else if (sdram_ch->ddrconfig == 3)
+               row = 14;
+       else
+               row = 15;
+
+       cs_map = (sdram_ch->rank > 1) ? 3 : 1;
+       reduc = (sdram_ch->bw == 2) ? 0 : 1;
+
+       clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+       clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
+                       ((3 - sdram_ch->bk) << 16) |
+                       ((16 - row) << 24));
+
+       clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
+                       cs_map | (reduc << 16));
+
+       /* PI_199 PI_COL_DIFF:RW:0:4 */
+       clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+
+       /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
+       clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
+                       ((3 - sdram_ch->bk) << 16) |
+                       ((16 - row) << 24));
+       /* PI_41 PI_CS_MAP:RW:24:4 */
+       clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
+       if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3))
+               writel(0x2EC7FFFF, &denali_pi[34]);
+}
+
+static void set_ds_odt(u32 channel,
+                      const struct rk3399_sdram_params *sdram_params)
+{
+       u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+
+       u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
+       u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+       u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
+       u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
+       u32 reg_value;
+
+       if (sdram_params->dramtype == LPDDR4) {
+               tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
+               tsel_wr_select_p = PHY_DRV_ODT_40;
+               ca_tsel_wr_select_p = PHY_DRV_ODT_40;
+               tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
+
+               tsel_rd_select_n = PHY_DRV_ODT_240;
+               tsel_wr_select_n = PHY_DRV_ODT_40;
+               ca_tsel_wr_select_n = PHY_DRV_ODT_40;
+               tsel_idle_select_n = PHY_DRV_ODT_240;
+       } else if (sdram_params->dramtype == LPDDR3) {
+               tsel_rd_select_p = PHY_DRV_ODT_240;
+               tsel_wr_select_p = PHY_DRV_ODT_34_3;
+               ca_tsel_wr_select_p = PHY_DRV_ODT_48;
+               tsel_idle_select_p = PHY_DRV_ODT_240;
+
+               tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
+               tsel_wr_select_n = PHY_DRV_ODT_34_3;
+               ca_tsel_wr_select_n = PHY_DRV_ODT_48;
+               tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
+       } else {
+               tsel_rd_select_p = PHY_DRV_ODT_240;
+               tsel_wr_select_p = PHY_DRV_ODT_34_3;
+               ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
+               tsel_idle_select_p = PHY_DRV_ODT_240;
+
+               tsel_rd_select_n = PHY_DRV_ODT_240;
+               tsel_wr_select_n = PHY_DRV_ODT_34_3;
+               ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
+               tsel_idle_select_n = PHY_DRV_ODT_240;
+       }
+
+       if (sdram_params->odt == 1)
+               tsel_rd_en = 1;
+       else
+               tsel_rd_en = 0;
+
+       tsel_wr_en = 0;
+       tsel_idle_en = 0;
+
+       /*
+        * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
+        * sets termination values for read/idle cycles and drive strength
+        * for write cycles for DQ/DM
+        */
+       reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
+                   (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
+                   (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
+       clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
+
+       /*
+        * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
+        * sets termination values for read/idle cycles and drive strength
+        * for write cycles for DQS
+        */
+       clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
+       clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
+
+       /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
+       reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
+       clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+       clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+       clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+
+       /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
+       clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
+
+       /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
+       clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+
+       /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
+       clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
+
+       /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
+       clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
+
+       /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
+       clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
+
+       /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
+       clrsetbits_le32(&denali_phy[924], 0xff,
+                       tsel_wr_select_n | (tsel_wr_select_p << 4));
+       clrsetbits_le32(&denali_phy[925], 0xff,
+                       tsel_rd_select_n | (tsel_rd_select_p << 4));
+
+       /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
+       reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
+               << 16;
+       clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
+       clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
+       clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
+       clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
+
+       /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
+       reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
+               << 24;
+       clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
+       clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
+       clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
+       clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
+
+       /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
+       reg_value = tsel_wr_en << 8;
+       clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
+       clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
+       clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
+
+       /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
+       reg_value = tsel_wr_en << 17;
+       clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +19 -0

+       u32 reg_value;
+       u32 drv_value, odt_value;
+       u32 speed;
+
+       /* vref setting */
+       if (sdram_params->dramtype == LPDDR4) {
+               /* LPDDR4 */
+               vref_mode_dq = 0x6;
+               vref_value_dq = 0x1f;
+               vref_mode_ac = 0x6;
+               vref_value_ac = 0x1f;
+       } else if (sdram_params->dramtype == LPDDR3) {
+               if (sdram_params->odt == 1) {
+                       vref_mode_dq = 0x5;  /* LPDDR3 ODT */
+                       drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+                       odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+                       if (drv_value == PHY_DRV_ODT_48) {
+                               switch (odt_value) {
+                               case PHY_DRV_ODT_240:

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +115 -0

+                               }
+                       } else if (drv_value == PHY_DRV_ODT_40) {
+                               switch (odt_value) {
+                               case PHY_DRV_ODT_240:
+                                       vref_value_dq = 0x19;
+                                       break;
+                               case PHY_DRV_ODT_120:
+                                       vref_value_dq = 0x23;
+                                       break;
+                               case PHY_DRV_ODT_60:
+                                       vref_value_dq = 0x31;
+                                       break;
+                               default:
+                                       error("Halting: Invalid ODT value.\n");
+                               }
+                       } else if (drv_value == PHY_DRV_ODT_34_3) {
+                               switch (odt_value) {
+                               case PHY_DRV_ODT_240:
+                                       vref_value_dq = 0x17;
+                                       break;
+                               case PHY_DRV_ODT_120:
+                                       vref_value_dq = 0x20;
+                                       break;
+                               case PHY_DRV_ODT_60:
+                                       vref_value_dq = 0x2e;
+                                       break;
+                               default:
+                                       error("Halting: Invalid ODT value.\n");
+                               }
+                       } else {
+                               error("Halting: Invalid DRV value.\n");
+                       }
+               } else {
+                       vref_mode_dq = 0x2;  /* LPDDR3 */
+                       vref_value_dq = 0x1f;
+               }
+               vref_mode_ac = 0x2;
+               vref_value_ac = 0x1f;
+       } else if (sdram_params->dramtype == DDR3) {
+               /* DDR3L */
+               vref_mode_dq = 0x1;
+               vref_value_dq = 0x1f;
+               vref_mode_ac = 0x1;
+               vref_value_ac = 0x1f;
+       }
+       else
+               error("Halting: Unknown DRAM type.\n");
+
+       reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+       /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+       clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+       /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+       clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+       /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+       clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+       /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+       clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+       reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+       /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+       clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+       if (sdram_params->dramtype == LPDDR4)
+               mode_sel = 0x6;
+       else if (sdram_params->dramtype == LPDDR3)
+               mode_sel = 0x0;
+       else if (sdram_params->dramtype == DDR3)
+               mode_sel = 0x1;
+
+       /* PHY_924 PHY_PAD_FDBK_DRIVE */
+       clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+       /* PHY_926 PHY_PAD_DATA_DRIVE */
+       clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+       /* PHY_927 PHY_PAD_DQS_DRIVE */
+       clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+       /* PHY_928 PHY_PAD_ADDR_DRIVE */
+       clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+       /* PHY_929 PHY_PAD_CLK_DRIVE */
+       clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+       /* PHY_935 PHY_PAD_CKE_DRIVE */
+       clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+       /* PHY_937 PHY_PAD_RST_DRIVE */
+       clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+       /* PHY_939 PHY_PAD_CS_DRIVE */
+       clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+
+       /* speed setting */
+       if (sdram_params->ddr_freq < 400*MHz)
+               speed = 0x0;
+       else if (sdram_params->ddr_freq < 800*MHz)
+               speed = 0x1;
+       else if (sdram_params->ddr_freq < 1200*MHz)
+               speed = 0x2;
+       else
+               speed = 0x3;
+
+       /* PHY_924 PHY_PAD_FDBK_DRIVE */
+       clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+       /* PHY_926 PHY_PAD_DATA_DRIVE */
+       clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+       /* PHY_927 PHY_PAD_DQS_DRIVE */
+       clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+       /* PHY_928 PHY_PAD_ADDR_DRIVE */
+       clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+       /* PHY_929 PHY_PAD_CLK_DRIVE */
+       clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+       /* PHY_935 PHY_PAD_CKE_DRIVE */
+       clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+       /* PHY_937 PHY_PAD_RST_DRIVE */
+       clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+       /* PHY_939 PHY_PAD_CS_DRIVE */
+       clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +28 -0

+       u32 tmp, tmp1, tmp2;
+       u32 pwrup_srefresh_exit;
+
+       /*
+        * work around controller bug:
+        * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
+        */
+       copy_to_reg(&denali_ctl[1], &params_ctl[1],
+                   sizeof(struct rk3399_ddr_pctl_regs) - 4);
+       writel(params_ctl[0], &denali_ctl[0]);
+       copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
+                   sizeof(struct rk3399_ddr_pi_regs));
+       /* rank count need to set for init */
+       set_memory_map(channel, sdram_params);
+
+       writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);
+       writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
+       writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
+
+       pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
+       clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
+
+       /* PHY_DLL_RST_EN */
+       clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
+
+       setbits_le32(&denali_pi[0], START);
+       setbits_le32(&denali_ctl[0], START);
+

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +34 -0

+
+       copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
+       copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
+       copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
+       copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
+       copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
+       copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
+       copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
+       copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
+       set_ds_odt(channel, sdram_params);
+
+       /*
+        * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
+        * dqs_tsel_wr_end[7:4] add Half cycle
+        */
+       tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
+       clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
+       tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
+       clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
+       tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
+       clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
+       tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
+       clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
+
+       /*
+        * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
+        * dq_tsel_wr_end[7:4] add Half cycle
+        */
+       tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
+       clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
+       tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
+       clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
+       tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
+       clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +18 -0

+       }
+
+       clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
+                       pwrup_srefresh_exit);
+       return 0;
+}
+
+static void select_per_cs_training_index(u32 channel, u32 rank)
+{
+       u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+
+       /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
+       if ((readl(&denali_phy[84])>>16) & 1) {
+               /*
+                * PHY_8/136/264/392
+                * phy_per_cs_training_index_X 1bit offset_24
+                */
+               clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +55 -0

+       u32 byte;
+
+       /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
+       setbits_le32(&denali_phy[896], 1);
+
+       /*
+        * PHY_8/136/264/392
+        * phy_per_cs_training_multicast_en_X 1bit offset_16
+        */
+       clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
+       clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
+       clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
+       clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
+
+       for (byte = 0; byte < 4; byte++)
+               clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
+                       0x200 << 16);
+
+       /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
+       clrbits_le32(&denali_phy[896], 1);
+
+       /* CTL_200 ctrlupd_req 1bit offset_8 */
+       clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
+}
+
+static int data_training(u32 channel,
+                        const struct rk3399_sdram_params *sdram_params,
+                        u32 training_flag)
+{
+       u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi;
+       u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+       u32 i, tmp;
+       u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
+       u32 rank = sdram_params->ch[channel].rank;
+
+       /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
+       setbits_le32(&denali_phy[927], (1 << 22));
+
+       if (training_flag == PI_FULL_TRAINING) {
+               if (sdram_params->dramtype == LPDDR4) {
+                       training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+                                       PI_READ_GATE_TRAINING |
+                                       PI_READ_LEVELING | PI_WDQ_LEVELING;
+               } else if (sdram_params->dramtype == LPDDR3) {
+                       training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+                                       PI_READ_GATE_TRAINING;
+               } else if (sdram_params->dramtype == DDR3) {
+                       training_flag = PI_WRITE_LEVELING |
+                                       PI_READ_GATE_TRAINING |
+                                       PI_READ_LEVELING;
+               }
+       }
+
+       /* ca training(LPDDR4,LPDDR3 support) */
+       if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +66 -0

+                               /* PI_174 PI_INT_STATUS:RD:8:18 */
+                               tmp = readl(&denali_pi[174]) >> 8;
+                               /*
+                                * check status obs
+                                * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
+                                */
+                               obs_0 = readl(&denali_phy[532]);
+                               obs_1 = readl(&denali_phy[660]);
+                               obs_2 = readl(&denali_phy[788]);
+                               if (((obs_0 >> 30) & 0x3) ||
+                                   ((obs_1 >> 30) & 0x3) ||
+                                   ((obs_2 >> 30) & 0x3))
+                                       obs_err = 1;
+                               if ((((tmp >> 11) & 0x1) == 0x1) &&
+                                   (((tmp >> 13) & 0x1) == 0x1) &&
+                                   (((tmp >> 5) & 0x1) == 0x0) &&
+                                   (obs_err == 0))
+                                       break;
+                               else if ((((tmp >> 5) & 0x1) == 0x1) ||
+                                        (obs_err == 1))
+                                       return -1;
+                       }
+                       /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+                       writel(0x00003f7c, (&denali_pi[175]));
+               }
+               clrbits_le32(&denali_pi[100], 0x3 << 8);
+       }
+
+       /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
+       if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
+               for (i = 0; i < rank; i++) {
+                       select_per_cs_training_index(channel, i);
+                       /* PI_60 PI_WRLVL_EN:RW:8:2 */
+                       clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
+                       /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
+                       clrsetbits_le32(&denali_pi[59],
+                                       (0x1 << 8) | (0x3 << 16),
+                                       (0x1 << 8) | (i << 16));
+
+                       while (1) {
+                               /* PI_174 PI_INT_STATUS:RD:8:18 */
+                               tmp = readl(&denali_pi[174]) >> 8;
+
+                               /*
+                                * check status obs, if error maybe can not
+                                * get leveling done PHY_40/168/296/424
+                                * phy_wrlvl_status_obs_X:0:13
+                                */
+                               obs_0 = readl(&denali_phy[40]);
+                               obs_1 = readl(&denali_phy[168]);
+                               obs_2 = readl(&denali_phy[296]);
+                               obs_3 = readl(&denali_phy[424]);
+                               if (((obs_0 >> 12) & 0x1) ||
+                                   ((obs_1 >> 12) & 0x1) ||
+                                   ((obs_2 >> 12) & 0x1) ||
+                                   ((obs_3 >> 12) & 0x1))
+                                       obs_err = 1;
+                               if ((((tmp >> 10) & 0x1) == 0x1) &&
+                                   (((tmp >> 13) & 0x1) == 0x1) &&
+                                   (((tmp >> 4) & 0x1) == 0x0) &&
+                                   (obs_err == 0))
+                                       break;
+                               else if ((((tmp >> 4) & 0x1) == 0x1) ||
+                                        (obs_err == 1))
+                                       return -1;
+                       }

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +47 -0

+               for (i = 0; i < rank; i++) {
+                       select_per_cs_training_index(channel, i);
+                       /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
+                       clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
+                       /*
+                        * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
+                        * PI_RDLVL_CS:RW:24:2
+                        */
+                       clrsetbits_le32(&denali_pi[74],
+                                       (0x1 << 16) | (0x3 << 24),
+                                       (0x1 << 16) | (i << 24));
+
+                       while (1) {
+                               /* PI_174 PI_INT_STATUS:RD:8:18 */
+                               tmp = readl(&denali_pi[174]) >> 8;
+
+                               /*
+                                * check status obs
+                                * PHY_43/171/299/427
+                                *     PHY_GTLVL_STATUS_OBS_x:16:8
+                                */
+                               obs_0 = readl(&denali_phy[43]);
+                               obs_1 = readl(&denali_phy[171]);
+                               obs_2 = readl(&denali_phy[299]);
+                               obs_3 = readl(&denali_phy[427]);
+                               if (((obs_0 >> (16 + 6)) & 0x3) ||
+                                   ((obs_1 >> (16 + 6)) & 0x3) ||
+                                   ((obs_2 >> (16 + 6)) & 0x3) ||
+                                   ((obs_3 >> (16 + 6)) & 0x3))
+                                       obs_err = 1;
+                               if ((((tmp >> 9) & 0x1) == 0x1) &&
+                                   (((tmp >> 13) & 0x1) == 0x1) &&
+                                   (((tmp >> 3) & 0x1) == 0x0) &&
+                                   (obs_err == 0))
+                                       break;
+                               else if ((((tmp >> 3) & 0x1) == 0x1) ||
+                                        (obs_err == 1))
+                                       return -1;
+                       }
+                       /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+                       writel(0x00003f7c, (&denali_pi[175]));
+               }
+               clrbits_le32(&denali_pi[80], 0x3 << 24);
+       }
+
+       /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
+       if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +79 -0

+                               /* PI_174 PI_INT_STATUS:RD:8:18 */
+                               tmp = readl(&denali_pi[174]) >> 8;
+
+                               /*
+                                * make sure status obs not report error bit
+                                * PHY_46/174/302/430
+                                *     phy_rdlvl_status_obs_X:16:8
+                                */
+                               if ((((tmp >> 8) & 0x1) == 0x1) &&
+                                   (((tmp >> 13) & 0x1) == 0x1) &&
+                                   (((tmp >> 2) & 0x1) == 0x0))
+                                       break;
+                               else if (((tmp >> 2) & 0x1) == 0x1)
+                                       return -1;
+                       }
+                       /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+                       writel(0x00003f7c, (&denali_pi[175]));
+               }
+               clrbits_le32(&denali_pi[80], 0x3 << 16);
+       }
+
+       /* wdq leveling(LPDDR4 support) */
+       if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
+               for (i = 0; i < rank; i++) {
+                       select_per_cs_training_index(channel, i);
+                       /*
+                        * disable PI_WDQLVL_VREF_EN before wdq leveling?
+                        * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
+                        */
+                       clrbits_le32(&denali_pi[181], 0x1 << 8);
+                       /* PI_124 PI_WDQLVL_EN:RW:16:2 */
+                       clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
+                       /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
+                       clrsetbits_le32(&denali_pi[121],
+                                       (0x1 << 8) | (0x3 << 16),
+                                       (0x1 << 8) | (i << 16));
+
+                       while (1) {
+                               /* PI_174 PI_INT_STATUS:RD:8:18 */
+                               tmp = readl(&denali_pi[174]) >> 8;
+                               if ((((tmp >> 12) & 0x1) == 0x1) &&
+                                   (((tmp >> 13) & 0x1) == 0x1) &&
+                                   (((tmp >> 6) & 0x1) == 0x0))
+                                       break;
+                               else if (((tmp >> 6) & 0x1) == 0x1)
+                                       return -1;
+                       }
+                       /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
+                       writel(0x00003f7c, (&denali_pi[175]));
+               }
+               clrbits_le32(&denali_pi[124], 0x3 << 16);
+       }
+
+       /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
+       clrbits_le32(&denali_phy[927], (1 << 22));
+
+       return 0;
+}
+
+static void set_ddrconfig(const struct rk3399_sdram_params *sdram_params,
+                         unsigned char channel, u32 ddrconfig)
+{
+       /* only need to set ddrconfig */
+       struct rk3399_msch_regs *ddr_msch_regs = rk3399_msch[channel];
+       unsigned int cs0_cap = 0;
+       unsigned int cs1_cap = 0;
+
+       cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
+                       + sdram_params->ch[channel].col
+                       + sdram_params->ch[channel].bk
+                       + sdram_params->ch[channel].bw - 20));
+       if (sdram_params->ch[channel].rank > 1)
+               cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
+                               - sdram_params->ch[channel].cs1_row);
+       if (sdram_params->ch[channel].row_3_4) {
+               cs0_cap = cs0_cap * 3 / 4;
+               cs1_cap = cs1_cap * 3 / 4;
+       }
+

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +59 -0

+
+       sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
+       sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->num_channels);
+       for (channel = 0, use = 0;
+            (use < sdram_params->num_channels) && (channel < 2); channel++) {
+               const struct rk3399_sdram_channel *info =
+                       &sdram_params->ch[channel];
+               struct rk3399_msch_regs *ddr_msch_regs;
+               const struct rk3399_msch_timings *noc_timing;
+
+               if (sdram_params->ch[channel].col == 0)
+                       continue;
+               use++;
+               sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel);
+               sys_reg |= SYS_REG_ENC_CHINFO(channel);
+               sys_reg |= SYS_REG_ENC_RANK(info->rank, channel);
+               sys_reg |= SYS_REG_ENC_COL(info->col, channel);
+               sys_reg |= SYS_REG_ENC_BK(info->bk, channel);
+               sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel);
+               if (sdram_params->ch[channel].rank > 1)
+                       sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel);
+               sys_reg |= SYS_REG_ENC_BW(info->bw, channel);
+               sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel);
+
+               ddr_msch_regs = rk3399_msch[channel];
+               noc_timing = &sdram_params->ch[channel].noc_timings;
+               writel(noc_timing->ddrtiminga0.d32,
+                      &ddr_msch_regs->ddrtiminga0.d32);
+               writel(noc_timing->ddrtimingb0.d32,
+                       &ddr_msch_regs->ddrtimingb0.d32);
+               writel(noc_timing->ddrtimingc0.d32,
+                       &ddr_msch_regs->ddrtimingc0.d32);
+               writel(noc_timing->devtodev0.d32,
+                       &ddr_msch_regs->devtodev0.d32);
+               writel(noc_timing->ddrmode.d32,
+                       &ddr_msch_regs->ddrmode.d32);
+
+               /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
+               if (sdram_params->ch[channel].rank == 1)
+                       setbits_le32(&rk3399_ddr_pctl[channel]->denali_ctl[276],
+                                    1 << 17);
+       }
+
+       writel(sys_reg, &rk3399_pmugrf->os_reg2);
+       DDR_STRIDE(sdram_params->stride);
+
+       /* reboot hold register set */
+       writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
+               PRESET_GPIO1_HOLD(1),
+               &pmucru_ptr->pmucru_rstnhold_con[1]);
+       clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3);
+}
+
+static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
+{
+       u32 channel;
+       u32 *denali_phy;
+       u32 ch_count = sdram_params->num_channels;
+       int i = 0;

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +70 -0

+               }
+       }
+
+       i = 0;
+       writel(RK_CLRSETBITS(1 << 1, 1 << 1), &rk3399_ddr_cic->cic_ctrl0);
+       while (!(readl(&rk3399_ddr_cic->cic_status0) & (1 << 0))) {
+               mdelay(10);
+               if (i>10) {
+                       error("index1 frequency done overtime, reset\n");
+                       hang();
+               }
+       }
+
+       for (channel = 0; channel < ch_count; channel++) {
+               denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+               clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
+               if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
+                       error("index1 training failed, reset\n");
+                       hang();
+               }
+       }
+}
+static struct rk3399_sdram_params sdram_configs[] = {
+#include "sdram-lpddr3-4GB.inc"
+};
+
+void sdram_init(const struct rk3399_sdram_params *sdram_params)
+{
+       unsigned char dramtype = sdram_params->dramtype;
+       unsigned int ddr_freq = sdram_params->ddr_freq;
+       int channel;
+
+       debug("Starting SDRAM initialization...\n");
+
+       if ((dramtype == DDR3 && ddr_freq > 800*MHz) ||
+           (dramtype == LPDDR3 && ddr_freq > 933*MHz) ||
+           (dramtype == LPDDR4 && ddr_freq > 800*MHz))
+               error("SDRAM frequency is to high!");
+
+
+       for (channel = 0; channel < 2; channel++) {
+               phy_dll_bypass_set(channel, rk3399_ddr_publ[channel], ddr_freq);
+
+               if (channel >= sdram_params->num_channels)
+                       continue;
+
+               /*
+                * TODO: we need to find the root cause why this
+                * step may fail, before that, we just reset the
+                * system, and start again.
+                */
+               if (pctl_cfg(channel, sdram_params) != 0) {
+                       printf("pctl_cfg fail, reset\n");
+                       hang();
+               }
+
+               /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
+               if (dramtype == LPDDR3)
+                       udelay(10);
+
+               if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
+                       printf("SDRAM initialization failed, reset\n");
+                       hang();
+               }
+
+               set_ddrconfig(sdram_params, channel,
+                             sdram_params->ch[channel].ddrconfig);
+       }
+       dram_all_config(sdram_params);
+       switch_to_phy_index1(sdram_params);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +44 -0

+       u32 ch;
+
+       if (!size_mb) {
+               u32 sys_reg = readl(&rk3399_pmugrf->os_reg2);
+               u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);
+
+               for (ch = 0; ch < ch_num; ch++) {
+                       rank = SYS_REG_DEC_RANK(sys_reg, ch);
+                       col = SYS_REG_DEC_COL(sys_reg, ch);
+                       bk = SYS_REG_DEC_BK(sys_reg, ch);
+                       cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch);
+                       cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch);
+                       bw = SYS_REG_DEC_BW(sys_reg, ch);
+                       row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch);
+
+                       chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
+
+                       if (rank > 1)
+                               chipsize_mb += chipsize_mb >>
+                                       (cs0_row - cs1_row);
+                       if (row_3_4)
+                               chipsize_mb = chipsize_mb * 3 / 4;
+                       size_mb += chipsize_mb;
+               }
+
+               /*
+                * we use the 0x00000000~0xf7ffffff space
+                * since 0xf8000000~0xffffffff is soc register space
+                * so we reserve it
+                */
+               size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20));
+       }
+
+       return size_mb;
+}
+
+static int rk3399_dmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_SPL_BUILD
+       struct rk3399_sdram_params *plat = sdram_configs;
+       int ret;
+       struct clk ddr_clk;
+
+       ret = clk_get_by_index(dev, 0, &ddr_clk);

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +15 -1

+#endif
+       return 0;
+}
+
+static const struct udevice_id rk3399_dmc_ids[] = {
+       { .compatible = "rockchip,rk3399-dmc" },
+       { }
+};
+
+U_BOOT_DRIVER(dmc_rk3399) = {
+       .name = "rockchip_rk3399_dmc",
+       .id = UCLASS_RAM,
+       .of_match = rk3399_dmc_ids,
+       .probe = rk3399_dmc_probe,
+};
--

1.9.1

Quoted 8 lines

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c line 134

Quoted 8 lines

arch/arm/mach-rockchip/rk3399/sdram_rk3399.c new file +8 -0

+{
+       u32 *denali_phy = ddr_publ_regs->denali_phy;
+       if (freq <= 125*MHz) {
+               /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
+               setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
+               setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
+               setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
+               setbits_le32(&denali_phy[470], (0x3 << 2) << 8);

These should really be defined as SHIFT and MASK values.

ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more infomation about ATF at:

SPL is consider as BL2 in ATF, it needs to load other part of ATF binary

like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to prepare the parameter for BL31 which including entry and image information for all other images. Then the SPL handle PC to BL31 with the parameter, the BL31 will do the rest of work and at last get into U-Boot(BL33).

Signed-off-by Kever Yang <[email protected]>

---

 common/spl/Kconfig   |  14 +++
 common/spl/Makefile  |   1 +
 common/spl/spl.c     |   4 +
 common/spl/spl_atf.c |  91 ++++++++++++++++
 include/atf_common.h | 295 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/spl.h        |   1 +
 6 files changed, 406 insertions(+)
 create mode 100644 common/spl/spl_atf.c
 create mode 100644 include/atf_common.h

common/spl/Kconfig +14 -0

index cba51f5..1bb4360 100644
@@ -577,6 +577,20 @@ config SPL_YMODEM_SUPPORT
 	  means of transmitting U-Boot over a serial line for using in SPL,
 	  with a checksum to ensure correctness.
 
+config SPL_ATF_SUPPORT
+	bool "Support ARM trust firmware"
+	depends on SPL
+	help
+	  ATF(ARM Trust Firmware) is component for ARM arch64 which need to
+	  load by SPL(consider as BL2 in ATF).
+	  More detail at: https://github.com/ARM-software/arm-trusted-firmware
+
+config SPL_ATF_TEXT_BASE
+	depends on SPL_ATF_SUPPORT
+	hex "ATF TEXT BASE addr"
+	help
+	  This is the base address in memory for ATF text and entry point.
+
 config TPL_ENV_SUPPORT
 	bool "Support an environment"
 	depends on TPL

common/spl/Makefile +1 -0

index ed02635..620ae90 100644
@@ -20,6 +20,7 @@ endif
 obj-$(CONFIG_SPL_UBI) += spl_ubi.o
 obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
 obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
 obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
 obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
 obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o

common/spl/spl.c +4 -0

index 1729034..7daf7bd 100644
@@ -390,6 +390,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	      gd->malloc_ptr / 1024);
 #endif
 
+#ifdef CONFIG_SPL_ATF_SUPPORT
+	bl31_entry();
+#endif
+
 	debug("loaded - jumping to U-Boot...");
 	spl_board_prepare_for_boot();
 	jump_to_image_no_args(&spl_image);

common/spl/spl_atf.c new file +0 -0

new file mode 100644
index 0000000..cf23b7a

common/spl/spl_atf.c new file +36 -0

+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <atf_common.h>
+
+static struct bl2_to_bl31_params_mem_t bl31_params_mem;
+static struct bl31_params_t *bl2_to_bl31_params;
+
+/*******************************************************************************
+ * This function assigns a pointer to the memory that the platform has kept
+ * aside to pass platform specific and trusted firmware related information
+ * to BL31. This memory is allocated by allocating memory to
+ * bl2_to_bl31_params_mem_t structure which is a superset of all the
+ * structure whose information is passed to BL31
+ * NOTE: This function should be called only once and should be done
+ * before generating params to BL31
+ ******************************************************************************/
+struct bl31_params_t *bl2_plat_get_bl31_params(void)
+{
+	struct entry_point_info_t *bl33_ep_info;
+
+	/*
+	 * Initialise the memory for all the arguments that needs to
+	 * be passed to BL31
+	 */
+	memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem_t));
+
+	/* Assign memory for TF related information */
+	bl2_to_bl31_params = &bl31_params_mem.bl31_params;
+	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
+
+	/* Fill BL31 related information */
+	SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
+		       VERSION_1, 0);

common/spl/spl_atf.c new file +7 -0

+
+	/* Fill BL33 related information */
+	bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+	bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+	SET_PARAM_HEAD(bl33_ep_info, PARAM_EP, VERSION_1, EP_NON_SECURE);
+
+	/* BL33 expects to receive the primary CPU MPID (through x0) */

common/spl/spl_atf.c new file +21 -0

+	return bl2_to_bl31_params;
+}
+
+void raw_write_daif(uint32_t daif)
+{
+	__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
+}
+
+void bl31_entry(void)
+{
+	struct bl31_params_t *bl31_params;
+	void (*entry)(struct bl31_params_t *params, void *plat_params) = NULL;
+
+	bl31_params = bl2_plat_get_bl31_params();
+	entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
+
+	raw_write_daif(SPSR_EXCEPTION_MASK);
+	dcache_disable();
+
+	entry(bl31_params, NULL);
+}

include/atf_common.h new file +18 -0

new file mode 100644
index 0000000..8351302
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

include/atf_common.h new file +267 -0

+ */
+
+#ifndef __BL_COMMON_H__
+#define __BL_COMMON_H__
+
+#define SECURE		0x0
+#define NON_SECURE	0x1
+#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
+
+#define UP	1
+#define DOWN	0
+
+/*******************************************************************************
+ * Constants to identify the location of a memory region in a given memory
+ * layout.
+******************************************************************************/
+#define TOP	0x1
+#define BOTTOM	!TOP
+
+/*******************************************************************************
+ * Constants that allow assembler code to access members of and the
+ * 'entry_point_info' structure at their correct offsets.
+ ******************************************************************************/
+#define ENTRY_POINT_INFO_PC_OFFSET	0x08
+#define ENTRY_POINT_INFO_ARGS_OFFSET	0x18
+
+/* The following are used to set/get image attributes. */
+#define PARAM_EP_SECURITY_MASK		(0x1)
+
+#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
+#define SET_SECURITY_STATE(x, security) \
+			((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
+
+
+/*
+ * The following are used for image state attributes.
+ * Image can only be in one of the following state.
+ */
+#define IMAGE_STATE_RESET			0
+#define IMAGE_STATE_COPIED			1
+#define IMAGE_STATE_COPYING			2
+#define IMAGE_STATE_AUTHENTICATED		3
+#define IMAGE_STATE_EXECUTED			4
+#define IMAGE_STATE_INTERRUPTED			5
+
+#define EP_SECURE	0x0
+#define EP_NON_SECURE	0x1
+
+#define EP_EE_MASK	0x2
+#define EP_EE_LITTLE	0x0
+#define EP_EE_BIG	0x2
+#define EP_GET_EE(x) (x & EP_EE_MASK)
+#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
+
+#define EP_ST_MASK	0x4
+#define EP_ST_DISABLE	0x0
+#define EP_ST_ENABLE	0x4
+#define EP_GET_ST(x) (x & EP_ST_MASK)
+#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
+
+#define EP_EXE_MASK	0x8
+#define NON_EXECUTABLE	0x0
+#define EXECUTABLE	0x8
+#define EP_GET_EXE(x) (x & EP_EXE_MASK)
+#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
+
+#define PARAM_EP		0x01
+#define PARAM_IMAGE_BINARY	0x02
+#define PARAM_BL31		0x03
+
+#define VERSION_1	0x01
+
+#define INVALID_IMAGE_ID		(0xFFFFFFFF)
+
+#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
+	(_p)->h.type = (uint8_t)(_type); \
+	(_p)->h.version = (uint8_t)(_ver); \
+	(_p)->h.size = (uint16_t)sizeof(*_p); \
+	(_p)->h.attr = (uint32_t)(_attr) ; \
+	} while (0)
+
+/* Following is used for populating structure members statically. */
+#define SET_STATIC_PARAM_HEAD(_p, _type, _ver, _p_type, _attr)	\
+	._p.h.type = (uint8_t)(_type), \
+	._p.h.version = (uint8_t)(_ver), \
+	._p.h.size = (uint16_t)sizeof(_p_type), \
+	._p.h.attr = (uint32_t)(_attr)
+
+#define MODE_RW_SHIFT	0x4
+#define MODE_RW_MASK	0x1
+#define MODE_RW_64	0x0
+#define MODE_RW_32	0x1
+
+#define MODE_EL_SHIFT	0x2
+#define MODE_EL_MASK	0x3
+#define MODE_EL3	0x3
+#define MODE_EL2	0x2
+#define MODE_EL1	0x1
+#define MODE_EL0	0x0
+
+#define MODE_SP_SHIFT	0x0
+#define MODE_SP_MASK	0x1
+#define MODE_SP_EL0	0x0
+#define MODE_SP_ELX	0x1
+
+#define SPSR_DAIF_SHIFT	6
+#define SPSR_DAIF_MASK	0x0f
+
+#define DAIF_FIQ_BIT (1<<0)
+#define DAIF_IRQ_BIT (1<<0)
+#define DAIF_ABT_BIT (1<<0)
+#define DAIF_DBG_BIT (1<<0)
+#define DISABLE_ALL_EXECPTIONS	\
+	(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+#define SPSR_64(el, sp, daif)		\
+	(MODE_RW_64 << MODE_RW_SHIFT |	\
+	 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT |	\
+	 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT |	\
+	 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+/*******************************************************************************
+ * Constants to indicate type of exception to the common exception handler.
+ ******************************************************************************/
+#define SYNC_EXCEPTION_SP_EL0		0x0
+#define IRQ_SP_EL0			0x1
+#define FIQ_SP_EL0			0x2
+#define SERROR_SP_EL0			0x3
+#define SYNC_EXCEPTION_SP_ELX		0x4
+#define IRQ_SP_ELX			0x5
+#define FIQ_SP_ELX			0x6
+#define SERROR_SP_ELX			0x7
+#define SYNC_EXCEPTION_AARCH64		0x8
+#define IRQ_AARCH64			0x9
+#define FIQ_AARCH64			0xa
+#define SERROR_AARCH64			0xb
+#define SYNC_EXCEPTION_AARCH32		0xc
+#define IRQ_AARCH32			0xd
+#define FIQ_AARCH32			0xe
+#define SERROR_AARCH32			0xf
+
+#define SPSR_USE_L           0
+#define SPSR_USE_H           1
+#define SPSR_L_H_MASK        1
+#define SPSR_M_SHIFT         4
+#define SPSR_ERET_32         (1 << SPSR_M_SHIFT)
+#define SPSR_ERET_64         (0 << SPSR_M_SHIFT)
+#define SPSR_FIQ             (1 << 6)
+#define SPSR_IRQ             (1 << 7)
+#define SPSR_SERROR          (1 << 8)
+#define SPSR_DEBUG           (1 << 9)
+#define SPSR_EXCEPTION_MASK  (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Structure used for telling the next BL how much of a particular type of
+ * memory is available for its use and how much is already used.
+ ******************************************************************************/
+struct aapcs64_params_t {
+	unsigned long arg0;
+	unsigned long arg1;
+	unsigned long arg2;
+	unsigned long arg3;
+	unsigned long arg4;
+	unsigned long arg5;
+	unsigned long arg6;
+	unsigned long arg7;
+};
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+struct param_header_t {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;    /* version of this structure */
+	uint16_t size;      /* size of this structure in bytes */
+	uint32_t attr;      /* attributes: unused bits SBZ */
+};
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+struct entry_point_info_t {
+	struct param_header_t h;
+	uintptr_t pc;
+	uint32_t spsr;
+	struct aapcs64_params_t args;
+};
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+struct atf_image_info_t {
+	struct param_header_t h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+};
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+struct image_desc_t {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	struct atf_image_info_t atf_image_info;
+	struct entry_point_info_t ep_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+struct bl31_params_t {
+	struct param_header_t h;
+	struct atf_image_info_t *bl31_image_info;
+	struct entry_point_info_t *bl32_ep_info;
+	struct atf_image_info_t *bl32_image_info;
+	struct entry_point_info_t *bl33_ep_info;
+	struct atf_image_info_t *bl33_image_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that is passed to
+ * BL31, e.g. while passing control to it from BL2, bl31_params
+ * and other platform specific params
+ ******************************************************************************/
+struct bl2_to_bl31_params_mem_t {
+	struct bl31_params_t bl31_params;
+	struct atf_image_info_t bl31_image_info;
+	struct atf_image_info_t bl32_image_info;
+	struct atf_image_info_t bl33_image_info;
+	struct entry_point_info_t bl33_ep_info;
+	struct entry_point_info_t bl32_ep_info;
+	struct entry_point_info_t bl31_ep_info;
+};
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __BL_COMMON_H__ */

include/spl.h +0 -0

index 918c464..ab5eaca 100644

Quoted 4 lines · Kever Yang

ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more infomation about ATF at:

SPL is consider as BL2 in ATF, it needs to load other part of ATF binary

SPL replaces BL2 in ATF

Quoted 5 lines

like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to prepare the parameter for BL31 which including entry and image information for all other images. Then the SPL handle PC to BL31 with the parameter, the BL31 will do the rest of work and at last get into U-Boot(BL33).

But the main question for this is how do load that images and in which format. It means I would think that you will introduce fit format which contain BL33(U-Boot), BL32(secure os) and BL31(ATF) and SPL will be able to load all of them.

If you look at zynqmp I did a small trick where I consider case that with ATF it is OS boot where kernel is ATF and dtb is full u-boot to get it boot.

If you adopt fit format then I expect SPL will be able to remember which part is where and based on that fill structure for ATF.
Then SPL_ATF_TEXT_BASE address is not needed because it will be read from fit format.

Quoted 74 lines

Signed-off-by Kever Yang <[email protected]>

---

  common/spl/Kconfig   |  14 +++
  common/spl/Makefile  |   1 +
  common/spl/spl.c     |   4 +
  common/spl/spl_atf.c |  91 ++++++++++++++++
  include/atf_common.h | 295 +++++++++++++++++++++++++++++++++++++++++++++++++++
  include/spl.h        |   1 +
  6 files changed, 406 insertions(+)

create mode 100644 common/spl/spl_atf.c
create mode 100644 include/atf_common.h

common/spl/Kconfig +14 -0

index cba51f5..1bb4360 100644
@@ -577,6 +577,20 @@ config SPL_YMODEM_SUPPORT
  	  means of transmitting U-Boot over a serial line for using in SPL,
  	  with a checksum to ensure correctness.
 
+config SPL_ATF_SUPPORT
+	bool "Support ARM trust firmware"
+	depends on SPL
+	help
+	  ATF(ARM Trust Firmware) is component for ARM arch64 which need to
+	  load by SPL(consider as BL2 in ATF).
+	  More detail at: https://github.com/ARM-software/arm-trusted-firmware
+
+config SPL_ATF_TEXT_BASE
+	depends on SPL_ATF_SUPPORT
+	hex "ATF TEXT BASE addr"
+	help
+	  This is the base address in memory for ATF text and entry point.
+
  config TPL_ENV_SUPPORT
  	bool "Support an environment"
  	depends on TPL

common/spl/Makefile +1 -0

index ed02635..620ae90 100644
@@ -20,6 +20,7 @@ endif
  obj-$(CONFIG_SPL_UBI) += spl_ubi.o
  obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
  obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
  obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
  obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
  obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o

common/spl/spl.c +4 -0

index 1729034..7daf7bd 100644
@@ -390,6 +390,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
  	      gd->malloc_ptr / 1024);
  #endif
 
+#ifdef CONFIG_SPL_ATF_SUPPORT
+	bl31_entry();
+#endif
+
  	debug("loaded - jumping to U-Boot...");
  	spl_board_prepare_for_boot();
  	jump_to_image_no_args(&spl_image);

common/spl/spl_atf.c new file +0 -0

new file mode 100644
index 0000000..cf23b7a
@@ -0,0 +1,91 @@

common/spl/spl_atf.c line 7

Quoted 7 lines

common/spl/spl_atf.c new file +7 -0

+/*
+ * Copyright (C) 2016 Rockchip Electronic Co.,Ltd
+ * Written by Kever Yang <[email protected]>
+ *
+ * origin from arm-trust-firmware
+ * plat/arm/common/arm_bl2_setup.c
+ * SPDX-License-Identifier:     GPL-2.0+

this is not based on gpl file that's why license should be different.

Quoted 41 lines

common/spl/spl_atf.c new file +39 -0

+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <atf_common.h>
+
+static struct bl2_to_bl31_params_mem_t bl31_params_mem;
+static struct bl31_params_t *bl2_to_bl31_params;
+
+/*******************************************************************************
+ * This function assigns a pointer to the memory that the platform has kept
+ * aside to pass platform specific and trusted firmware related information
+ * to BL31. This memory is allocated by allocating memory to
+ * bl2_to_bl31_params_mem_t structure which is a superset of all the
+ * structure whose information is passed to BL31
+ * NOTE: This function should be called only once and should be done
+ * before generating params to BL31
+ ******************************************************************************/
+struct bl31_params_t *bl2_plat_get_bl31_params(void)
+{
+	struct entry_point_info_t *bl33_ep_info;
+
+	/*
+	 * Initialise the memory for all the arguments that needs to
+	 * be passed to BL31
+	 */
+	memset(&bl31_params_mem, 0, sizeof(struct bl2_to_bl31_params_mem_t));
+
+	/* Assign memory for TF related information */
+	bl2_to_bl31_params = &bl31_params_mem.bl31_params;
+	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
+
+	/* Fill BL31 related information */
+	SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
+		       VERSION_1, 0);
+
+	/* Fill BL32 related information if it exists */
+#ifdef BL32_BASE

common/spl/spl_atf.c line 53

Quoted 7 lines

common/spl/spl_atf.c new file +7 -0

+	bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
+	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
+		       VERSION_1, 0);
+	bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
+	SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
+		       VERSION_1, 0);
+#endif /* BL32_BASE */

Is this used?

Quoted 11 lines

common/spl/spl_atf.c new file +10 -0

+
+	/* Fill BL33 related information */
+	bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+	bl33_ep_info = &bl31_params_mem.bl33_ep_info;
+	SET_PARAM_HEAD(bl33_ep_info, PARAM_EP, VERSION_1, EP_NON_SECURE);
+
+	/* BL33 expects to receive the primary CPU MPID (through x0) */
+	bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
+	bl33_ep_info->pc = CONFIG_SYS_TEXT_BASE;
+	bl33_ep_info->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,

common/spl/spl_atf.c line 70

Quoted 7 lines

common/spl/spl_atf.c new file +7 -0

+				     DISABLE_ALL_EXECPTIONS);
+
+	bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
+	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
+		       VERSION_1, 0);
+
+

double lines.

Quoted 49 lines

common/spl/spl_atf.c new file +21 -0

+	return bl2_to_bl31_params;
+}
+
+void raw_write_daif(uint32_t daif)
+{
+	__asm__ __volatile__("msr DAIF, %0\n\t" : : "r" (daif) : "memory");
+}
+
+void bl31_entry(void)
+{
+	struct bl31_params_t *bl31_params;
+	void (*entry)(struct bl31_params_t *params, void *plat_params) = NULL;
+
+	bl31_params = bl2_plat_get_bl31_params();
+	entry = (void *)CONFIG_SPL_ATF_TEXT_BASE;
+
+	raw_write_daif(SPSR_EXCEPTION_MASK);
+	dcache_disable();
+
+	entry(bl31_params, NULL);
+}

include/atf_common.h new file +21 -0

new file mode 100644
index 0000000..8351302
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

include/atf_common.h line 28

Quoted 7 lines

include/atf_common.h new file +7 -0

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.

This should be probably in SPDX format.

Quoted 275 lines

include/atf_common.h new file +267 -0

+ */
+
+#ifndef __BL_COMMON_H__
+#define __BL_COMMON_H__
+
+#define SECURE		0x0
+#define NON_SECURE	0x1
+#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
+
+#define UP	1
+#define DOWN	0
+
+/*******************************************************************************
+ * Constants to identify the location of a memory region in a given memory
+ * layout.
+******************************************************************************/
+#define TOP	0x1
+#define BOTTOM	!TOP
+
+/*******************************************************************************
+ * Constants that allow assembler code to access members of and the
+ * 'entry_point_info' structure at their correct offsets.
+ ******************************************************************************/
+#define ENTRY_POINT_INFO_PC_OFFSET	0x08
+#define ENTRY_POINT_INFO_ARGS_OFFSET	0x18
+
+/* The following are used to set/get image attributes. */
+#define PARAM_EP_SECURITY_MASK		(0x1)
+
+#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK)
+#define SET_SECURITY_STATE(x, security) \
+			((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security))
+
+
+/*
+ * The following are used for image state attributes.
+ * Image can only be in one of the following state.
+ */
+#define IMAGE_STATE_RESET			0
+#define IMAGE_STATE_COPIED			1
+#define IMAGE_STATE_COPYING			2
+#define IMAGE_STATE_AUTHENTICATED		3
+#define IMAGE_STATE_EXECUTED			4
+#define IMAGE_STATE_INTERRUPTED			5
+
+#define EP_SECURE	0x0
+#define EP_NON_SECURE	0x1
+
+#define EP_EE_MASK	0x2
+#define EP_EE_LITTLE	0x0
+#define EP_EE_BIG	0x2
+#define EP_GET_EE(x) (x & EP_EE_MASK)
+#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee))
+
+#define EP_ST_MASK	0x4
+#define EP_ST_DISABLE	0x0
+#define EP_ST_ENABLE	0x4
+#define EP_GET_ST(x) (x & EP_ST_MASK)
+#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee))
+
+#define EP_EXE_MASK	0x8
+#define NON_EXECUTABLE	0x0
+#define EXECUTABLE	0x8
+#define EP_GET_EXE(x) (x & EP_EXE_MASK)
+#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee))
+
+#define PARAM_EP		0x01
+#define PARAM_IMAGE_BINARY	0x02
+#define PARAM_BL31		0x03
+
+#define VERSION_1	0x01
+
+#define INVALID_IMAGE_ID		(0xFFFFFFFF)
+
+#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
+	(_p)->h.type = (uint8_t)(_type); \
+	(_p)->h.version = (uint8_t)(_ver); \
+	(_p)->h.size = (uint16_t)sizeof(*_p); \
+	(_p)->h.attr = (uint32_t)(_attr) ; \
+	} while (0)
+
+/* Following is used for populating structure members statically. */
+#define SET_STATIC_PARAM_HEAD(_p, _type, _ver, _p_type, _attr)	\
+	._p.h.type = (uint8_t)(_type), \
+	._p.h.version = (uint8_t)(_ver), \
+	._p.h.size = (uint16_t)sizeof(_p_type), \
+	._p.h.attr = (uint32_t)(_attr)
+
+#define MODE_RW_SHIFT	0x4
+#define MODE_RW_MASK	0x1
+#define MODE_RW_64	0x0
+#define MODE_RW_32	0x1
+
+#define MODE_EL_SHIFT	0x2
+#define MODE_EL_MASK	0x3
+#define MODE_EL3	0x3
+#define MODE_EL2	0x2
+#define MODE_EL1	0x1
+#define MODE_EL0	0x0
+
+#define MODE_SP_SHIFT	0x0
+#define MODE_SP_MASK	0x1
+#define MODE_SP_EL0	0x0
+#define MODE_SP_ELX	0x1
+
+#define SPSR_DAIF_SHIFT	6
+#define SPSR_DAIF_MASK	0x0f
+
+#define DAIF_FIQ_BIT (1<<0)
+#define DAIF_IRQ_BIT (1<<0)
+#define DAIF_ABT_BIT (1<<0)
+#define DAIF_DBG_BIT (1<<0)
+#define DISABLE_ALL_EXECPTIONS	\
+	(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
+
+#define SPSR_64(el, sp, daif)		\
+	(MODE_RW_64 << MODE_RW_SHIFT |	\
+	 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT |	\
+	 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT |	\
+	 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)
+
+/*******************************************************************************
+ * Constants to indicate type of exception to the common exception handler.
+ ******************************************************************************/
+#define SYNC_EXCEPTION_SP_EL0		0x0
+#define IRQ_SP_EL0			0x1
+#define FIQ_SP_EL0			0x2
+#define SERROR_SP_EL0			0x3
+#define SYNC_EXCEPTION_SP_ELX		0x4
+#define IRQ_SP_ELX			0x5
+#define FIQ_SP_ELX			0x6
+#define SERROR_SP_ELX			0x7
+#define SYNC_EXCEPTION_AARCH64		0x8
+#define IRQ_AARCH64			0x9
+#define FIQ_AARCH64			0xa
+#define SERROR_AARCH64			0xb
+#define SYNC_EXCEPTION_AARCH32		0xc
+#define IRQ_AARCH32			0xd
+#define FIQ_AARCH32			0xe
+#define SERROR_AARCH32			0xf
+
+#define SPSR_USE_L           0
+#define SPSR_USE_H           1
+#define SPSR_L_H_MASK        1
+#define SPSR_M_SHIFT         4
+#define SPSR_ERET_32         (1 << SPSR_M_SHIFT)
+#define SPSR_ERET_64         (0 << SPSR_M_SHIFT)
+#define SPSR_FIQ             (1 << 6)
+#define SPSR_IRQ             (1 << 7)
+#define SPSR_SERROR          (1 << 8)
+#define SPSR_DEBUG           (1 << 9)
+#define SPSR_EXCEPTION_MASK  (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG)
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Structure used for telling the next BL how much of a particular type of
+ * memory is available for its use and how much is already used.
+ ******************************************************************************/
+struct aapcs64_params_t {
+	unsigned long arg0;
+	unsigned long arg1;
+	unsigned long arg2;
+	unsigned long arg3;
+	unsigned long arg4;
+	unsigned long arg5;
+	unsigned long arg6;
+	unsigned long arg7;
+};
+
+/***************************************************************************
+ * This structure provides version information and the size of the
+ * structure, attributes for the structure it represents
+ ***************************************************************************/
+struct param_header_t {
+	uint8_t type;		/* type of the structure */
+	uint8_t version;    /* version of this structure */
+	uint16_t size;      /* size of this structure in bytes */
+	uint32_t attr;      /* attributes: unused bits SBZ */
+};
+
+/*****************************************************************************
+ * This structure represents the superset of information needed while
+ * switching exception levels. The only two mechanisms to do so are
+ * ERET & SMC. Security state is indicated using bit zero of header
+ * attribute
+ * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start
+ * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while
+ * processing SMC to jump to BL31.
+ *****************************************************************************/
+struct entry_point_info_t {
+	struct param_header_t h;
+	uintptr_t pc;
+	uint32_t spsr;
+	struct aapcs64_params_t args;
+};
+
+/*****************************************************************************
+ * Image info binary provides information from the image loader that
+ * can be used by the firmware to manage available trusted RAM.
+ * More advanced firmware image formats can provide additional
+ * information that enables optimization or greater flexibility in the
+ * common firmware code
+ *****************************************************************************/
+struct atf_image_info_t {
+	struct param_header_t h;
+	uintptr_t image_base;   /* physical address of base of image */
+	uint32_t image_size;    /* bytes read from image file */
+};
+
+/*****************************************************************************
+ * The image descriptor struct definition.
+ *****************************************************************************/
+struct image_desc_t {
+	/* Contains unique image id for the image. */
+	unsigned int image_id;
+	/*
+	 * This member contains Image state information.
+	 * Refer IMAGE_STATE_XXX defined above.
+	 */
+	unsigned int state;
+	uint32_t copied_size;	/* image size copied in blocks */
+	struct atf_image_info_t atf_image_info;
+	struct entry_point_info_t ep_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+struct bl31_params_t {
+	struct param_header_t h;
+	struct atf_image_info_t *bl31_image_info;
+	struct entry_point_info_t *bl32_ep_info;
+	struct atf_image_info_t *bl32_image_info;
+	struct entry_point_info_t *bl33_ep_info;
+	struct atf_image_info_t *bl33_image_info;
+};
+
+/*******************************************************************************
+ * This structure represents the superset of information that is passed to
+ * BL31, e.g. while passing control to it from BL2, bl31_params
+ * and other platform specific params
+ ******************************************************************************/
+struct bl2_to_bl31_params_mem_t {
+	struct bl31_params_t bl31_params;
+	struct atf_image_info_t bl31_image_info;
+	struct atf_image_info_t bl32_image_info;
+	struct atf_image_info_t bl33_image_info;
+	struct entry_point_info_t bl33_ep_info;
+	struct entry_point_info_t bl32_ep_info;
+	struct entry_point_info_t bl31_ep_info;
+};
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __BL_COMMON_H__ */

include/spl.h +0 -0

index 918c464..ab5eaca 100644

include/spl.h int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr); · line 255

Quoted 5 lines

include/spl.h +1 -0

@@ -251,4 +251,5 @@ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr);
  int spl_mmc_load_image(struct spl_image_info *spl_image,
  		       struct spl_boot_device *bootdev);
 
+void bl31_entry(void);
  #endif

Thanks,
Michal