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crypto: caam - add Queue Interface (QI) support

PATCH In review Horia Geantă 4 participants 16 messages Mar 17, 2017 – Apr 7, 2017

Subsystems (3)
Crypto API Freescale SoC drivers Freescale CAAM (Cryptographic Acceleration and Assurance Module) driver
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Horia Geantă

author maintainer
#0 lore raw

cover crypto: caam - add Queue Interface (QI) support

RFC -> v1:
-rebased on latest cryptodev-2.6 tree
open-code tsk_cpus_allowed() - sync with commit 0c98d344fe5c "sched/core: Remove the tsk_cpus_allowed() wrapper" -addressed Scott's feedback - removed most of the accessors added in soc/qman (patch 4) and instead open-coded them in caam/qi

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
During RFC stage, we agreed to go with them through the crypto tree:
https://www.mail-archive.com/linux-crypto at vger.kernel.org/msg24105.html

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

Thanks,
Horia

Horia Geant? (7):
soc/qman: export volatile dequeue related structs soc/qman: add dedicated channel ID for CAAM soc/qman: export non-programmable FQD fields query soc/qman: add macros needed by caam/qi driver
crypto: caam - avoid double inclusion in desc_constr.h
crypto: caam - add Queue Interface (QI) backend support
crypto: caam/qi - add ablkcipher and authenc algorithms

 drivers/crypto/caam/Kconfig        |   20 +-
 drivers/crypto/caam/Makefile       |    5 +
 drivers/crypto/caam/caamalg.c      |    9 +-
 drivers/crypto/caam/caamalg_desc.c |   77 +-
 drivers/crypto/caam/caamalg_desc.h |   15 +-
 drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/ctrl.c         |   58 +-
 drivers/crypto/caam/desc_constr.h  |    5 +
 drivers/crypto/caam/intern.h       |   24 +
 drivers/crypto/caam/qi.c           |  805 ++++++++++++
 drivers/crypto/caam/qi.h           |  201 +++
 drivers/crypto/caam/sg_sw_qm.h     |  108 ++
 drivers/soc/fsl/qbman/qman.c       |    4 +-
 drivers/soc/fsl/qbman/qman_ccsr.c  |    6 +-
 drivers/soc/fsl/qbman/qman_priv.h  |   97 --
 include/soc/fsl/qman.h             |  109 ++
 16 files changed, 3786 insertions(+), 144 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/qi.c
 create mode 100644 drivers/crypto/caam/qi.h
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#1 lore raw

PATCH 1/7 soc/qman: export volatile dequeue related structs

Since qman_volatile_dequeue() is already exported, move the related structures into the public header too.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman_priv.h | 36 ------------------------------------
 include/soc/fsl/qman.h            | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 36 deletions(-)
drivers/soc/fsl/qbman/qman_priv.h +0 -36
index 53685b59718e..64781eff6974 100644
@@ -271,42 +271,6 @@ const struct qm_portal_config *qman_destroy_affine_portal(void);
  */
 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
 
-/*
- * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
- * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
- * FQID(n) to fill in the frame queue ID.
- */
-#define QM_VDQCR_PRECEDENCE_VDQCR	0x0
-#define QM_VDQCR_PRECEDENCE_SDQCR	0x80000000
-#define QM_VDQCR_EXACT			0x40000000
-#define QM_VDQCR_NUMFRAMES_MASK		0x3f000000
-#define QM_VDQCR_NUMFRAMES_SET(n)	(((n) & 0x3f) << 24)
-#define QM_VDQCR_NUMFRAMES_GET(n)	(((n) >> 24) & 0x3f)
-#define QM_VDQCR_NUMFRAMES_TILLEMPTY	QM_VDQCR_NUMFRAMES_SET(0)
-
-#define QMAN_VOLATILE_FLAG_WAIT	     0x00000001 /* wait if VDQCR is in use */
-#define QMAN_VOLATILE_FLAG_WAIT_INT  0x00000002 /* if wait, interruptible? */
-#define QMAN_VOLATILE_FLAG_FINISH    0x00000004 /* wait till VDQCR completes */
-
-/*
- * qman_volatile_dequeue - Issue a volatile dequeue command
- * @fq: the frame queue object to dequeue from
- * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
- * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
- *
- * Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
- * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
- * the VDQCR is already in use, otherwise returns non-zero for failure. If
- * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
- * the VDQCR command has finished executing (ie. once the callback for the last
- * DQRR entry resulting from the VDQCR command has been called). If not using
- * the FINISH flag, completion can be determined either by detecting the
- * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
- * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
- * for the QMAN_FQ_STATE_VDQCR bit to disappear.
- */
-int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
-
 int qman_alloc_fq_table(u32 num_fqids);
 
 /*   QMan s/w corenet portal, low-level i/face	 */
include/soc/fsl/qman.h +36 -0
index 3d4df74a96de..4de1ffcc8982 100644
@@ -791,6 +791,23 @@ struct qman_cgr {
 #define QMAN_INITFQ_FLAG_SCHED	     0x00000001 /* schedule rather than park */
 #define QMAN_INITFQ_FLAG_LOCAL	     0x00000004 /* set dest portal */
 
+/*
+ * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
+ * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
+ * FQID(n) to fill in the frame queue ID.
+ */
+#define QM_VDQCR_PRECEDENCE_VDQCR	0x0
+#define QM_VDQCR_PRECEDENCE_SDQCR	0x80000000
+#define QM_VDQCR_EXACT			0x40000000
+#define QM_VDQCR_NUMFRAMES_MASK		0x3f000000
+#define QM_VDQCR_NUMFRAMES_SET(n)	(((n) & 0x3f) << 24)
+#define QM_VDQCR_NUMFRAMES_GET(n)	(((n) >> 24) & 0x3f)
+#define QM_VDQCR_NUMFRAMES_TILLEMPTY	QM_VDQCR_NUMFRAMES_SET(0)
+
+#define QMAN_VOLATILE_FLAG_WAIT	     0x00000001 /* wait if VDQCR is in use */
+#define QMAN_VOLATILE_FLAG_WAIT_INT  0x00000002 /* if wait, interruptible? */
+#define QMAN_VOLATILE_FLAG_FINISH    0x00000004 /* wait till VDQCR completes */
+
 	/* Portal Management */
 /**
  * qman_p_irqsource_add - add processing sources to be interrupt-driven

@@ -963,6 +980,25 @@ int qman_retire_fq(struct qman_fq *fq, u32 *flags);
  */
 int qman_oos_fq(struct qman_fq *fq);
 
+/*
+ * qman_volatile_dequeue - Issue a volatile dequeue command
+ * @fq: the frame queue object to dequeue from
+ * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
+ * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
+ *
+ * Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
+ * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
+ * the VDQCR is already in use, otherwise returns non-zero for failure. If
+ * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
+ * the VDQCR command has finished executing (ie. once the callback for the last
+ * DQRR entry resulting from the VDQCR command has been called). If not using
+ * the FINISH flag, completion can be determined either by detecting the
+ * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
+ * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
+ * for the QMAN_FQ_STATE_VDQCR bit to disappear.
+ */
+int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
+
 /**
  * qman_enqueue - Enqueue a frame to a frame queue
  * @fq: the frame queue object to enqueue to
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#2 lore raw

PATCH 2/7 soc/qman: add dedicated channel ID for CAAM

In reply to Horia Geantă

Add and export the ID of the channel serviced by the CAAM (Cryptographic Acceleration and Assurance Module) DCP.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 6 +++++-
 include/soc/fsl/qman.h            | 3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)
drivers/soc/fsl/qbman/qman_ccsr.c +5 -1
index f4e6e70de259..90bc40c48675 100644
@@ -34,6 +34,8 @@ u16 qman_ip_rev;
 EXPORT_SYMBOL(qman_ip_rev);
 u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
 EXPORT_SYMBOL(qm_channel_pool1);
+u16 qm_channel_caam = QMAN_CHANNEL_CAAM;
+EXPORT_SYMBOL(qm_channel_caam);
 
 /* Register offsets */
 #define REG_QCSP_LIO_CFG(n)	(0x0000 + ((n) * 0x10))

@@ -720,8 +722,10 @@ static int fsl_qman_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	if ((qman_ip_rev & 0xff00) >= QMAN_REV30)
+	if ((qman_ip_rev & 0xff00) >= QMAN_REV30) {
 		qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
+		qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
+	}
 
 	ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
 	WARN_ON(ret);
include/soc/fsl/qman.h +3 -0
index 4de1ffcc8982..10b549783ec5 100644
@@ -36,8 +36,11 @@
 /* Hardware constants */
 #define QM_CHANNEL_SWPORTAL0 0
 #define QMAN_CHANNEL_POOL1 0x21
+#define QMAN_CHANNEL_CAAM 0x80
 #define QMAN_CHANNEL_POOL1_REV3 0x401
+#define QMAN_CHANNEL_CAAM_REV3 0x840
 extern u16 qm_channel_pool1;
+extern u16 qm_channel_caam;
 
 /* Portal processing (interrupt) sources */
 #define QM_PIRQ_CSCI	0x00100000	/* Congestion State Change */
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#3 lore raw

PATCH 3/7 soc/qman: export non-programmable FQD fields query

In reply to Horia Geantă

Export qman_query_fq_np() function and related structures. This will be needed in the caam/qi driver, where "queue empty" condition will be decided based on the frm_cnt.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman.c      |  4 +--
 drivers/soc/fsl/qbman/qman_priv.h | 61 -----------------------------------
 include/soc/fsl/qman.h            | 68 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+), 63 deletions(-)
drivers/soc/fsl/qbman/qman.c +2 -2
index 6f509f68085e..3d891db57ee6 100644
@@ -2019,8 +2019,7 @@ int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
 	return ret;
 }
 
-static int qman_query_fq_np(struct qman_fq *fq,
-			    struct qm_mcr_queryfq_np *np)
+int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
 {
 	union qm_mc_command *mcc;
 	union qm_mc_result *mcr;

@@ -2046,6 +2045,7 @@ static int qman_query_fq_np(struct qman_fq *fq,
 	put_affine_portal();
 	return ret;
 }
+EXPORT_SYMBOL(qman_query_fq_np);
 
 static int qman_query_cgr(struct qman_cgr *cgr,
 			  struct qm_mcr_querycgr *cgrd)
drivers/soc/fsl/qbman/qman_priv.h +0 -61

67 lines not on this page · raw message

include/soc/fsl/qman.h +68 -0

80 lines not on this page · raw message

Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#4 lore raw

PATCH 4/7 soc/qman: add macros needed by caam/qi driver

In reply to Horia Geantă

A few other things need to be added in soc/qman, such that caam/qi won't open-code them.

Signed-off-by Horia Geant? <[email protected]>
---
 include/soc/fsl/qman.h | 2 ++
 1 file changed, 2 insertions(+)
include/soc/fsl/qman.h +2 -0
index 0252c32f7421..d4dfefdee6c1 100644
@@ -168,6 +168,7 @@ static inline void qm_fd_set_param(struct qm_fd *fd, enum qm_fd_format fmt,
 #define qm_fd_set_contig_big(fd, len) \
 	qm_fd_set_param(fd, qm_fd_contig_big, 0, len)
 #define qm_fd_set_sg_big(fd, len) qm_fd_set_param(fd, qm_fd_sg_big, 0, len)
+#define qm_fd_set_compound(fd, len) qm_fd_set_param(fd, qm_fd_compound, 0, len)
 
 static inline void qm_fd_clear_fd(struct qm_fd *fd)
 {

@@ -642,6 +643,7 @@ struct qm_mcc_initcgr {
 #define QM_CGR_WE_MODE			0x0001
 
 #define QMAN_CGR_FLAG_USE_INIT	     0x00000001
+#define QMAN_CGR_MODE_FRAME          0x00000001
 
 	/* Portal and Frame Queues */
 /* Represents a managed portal */
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#5 lore raw

PATCH 5/7 crypto: caam - avoid double inclusion in desc_constr.h

In reply to Horia Geantă
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/desc_constr.h | 5 +++++
 1 file changed, 5 insertions(+)
drivers/crypto/caam/desc_constr.h +5 -0
index b9c8d98ef826..d8e83ca104e0 100644
@@ -4,6 +4,9 @@
  * Copyright 2008-2012 Freescale Semiconductor, Inc.
  */
 
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
 #include "desc.h"
 #include "regs.h"
 

@@ -491,3 +494,5 @@ static inline int desc_inline_query(unsigned int sd_base_len,
 
 	return (rem_bytes >= 0) ? 0 : -1;
 }
+
+#endif /* DESC_CONSTR_H */
Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#6 lore raw

PATCH 6/7 crypto: caam - add Queue Interface (QI) backend support

In reply to Horia Geantă

CAAM engine supports two interfaces for crypto job submission:
-job ring interface - already existing caam/jr driver -Queue Interface (QI) - caam/qi driver added in current patch

QI is present in CAAM engines found on DPAA platforms.
QI gets its I/O (frame descriptors) from QMan (Queue Manager) queues.

This patch adds a platform device for accessing CAAM's queue interface. The requests are submitted to CAAM using one frame queue per cryptographic context. Each crypto context has one shared descriptor. This shared descriptor is attached to frame queue associated with corresponding driver context using context_a.

The driver hides the mechanics of FQ creation, initialisation from its applications. Each cryptographic context needs to be associated with driver context which houses the FQ to be used to transport the job to CAAM. The driver provides API for:
(a) Context creation
(b) Job submission
(c) Context deletion
(d) Congestion indication - whether path to/from CAAM is congested

The driver supports affining its context to a particular CPU. This means that any responses from CAAM for the context in question would arrive at the given CPU. This helps in implementing one CPU per packet round trip in IPsec application.

The driver processes CAAM responses under NAPI contexts. NAPI contexts are instantiated only on cores with affined portals since only cores having their own portal can receive responses from DQRR.

The responses from CAAM for all cryptographic contexts ride on a fixed set of FQs. We use one response FQ per portal owning core. The response FQ is configured in each core's and thus portal's dedicated channel. This gives the flexibility to direct CAAM's responses for a crypto context on a given core.

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/Makefile |   4 +
 drivers/crypto/caam/ctrl.c   |  58 ++--
 drivers/crypto/caam/intern.h |  24 ++
 drivers/crypto/caam/qi.c     | 805 +++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/qi.h     | 201 +++++++++++
 5 files changed, 1064 insertions(+), 28 deletions(-)
 create mode 100644 drivers/crypto/caam/qi.c
 create mode 100644 drivers/crypto/caam/qi.h
drivers/crypto/caam/Makefile +4 -0
index 6554742f357e..2e60e45c2bf1 100644
@@ -16,3 +16,7 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o
 caam-objs := ctrl.o
 caam_jr-objs := jr.o key_gen.o error.o
 caam_pkc-y := caampkc.o pkc_desc.o
+ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)
+	ccflags-y += -DCONFIG_CAAM_QI
+	caam-objs += qi.o
+endif
drivers/crypto/caam/ctrl.c +30 -28

100 lines not on this page · raw message

drivers/crypto/caam/intern.h +24 -0
index e2bcacc1a921..c334df638ff6 100644
@@ -67,6 +67,9 @@ struct caam_drv_private {
 
 	struct device *dev;
 	struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
+#ifdef CONFIG_CAAM_QI
+	struct device *qidev;
+#endif
 	struct platform_device *pdev;
 
 	/* Physical-presence section */

@@ -110,9 +113,30 @@ struct caam_drv_private {
 
 	struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
 	struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk;
+#ifdef CONFIG_CAAM_QI
+	struct dentry *qi_congested;
+#endif
 #endif
 };
 
 void caam_jr_algapi_init(struct device *dev);
 void caam_jr_algapi_remove(struct device *dev);
+
+#ifdef CONFIG_DEBUG_FS
+static int caam_debugfs_u64_get(void *data, u64 *val)
+{
+	*val = caam64_to_cpu(*(u64 *)data);
+	return 0;
+}
+
+static int caam_debugfs_u32_get(void *data, u64 *val)
+{
+	*val = caam32_to_cpu(*(u32 *)data);
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
+#endif
+
 #endif /* INTERN_H */
drivers/crypto/caam/qi.c new file +805 -0

805 lines not on this page · raw message

drivers/crypto/caam/qi.h new file +201 -0

201 lines not on this page · raw message

Signature · 1 line
2.12.0.264.gd6db3f216544
author maintainer
#7 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

In reply to Horia Geantă

Add support to submit ablkcipher and authenc algorithms via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/Kconfig        |   20 +-
 drivers/crypto/caam/Makefile       |    1 +
 drivers/crypto/caam/caamalg.c      |    9 +-
 drivers/crypto/caam/caamalg_desc.c |   77 +-
 drivers/crypto/caam/caamalg_desc.h |   15 +-
 drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_qm.h     |  108 ++
 7 files changed, 2601 insertions(+), 16 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h
drivers/crypto/caam/Kconfig +19 -1
index bc0d3569f8d9..e36aeacd7635 100644
@@ -87,6 +87,23 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
 	  To compile this as a module, choose M here: the module
 	  will be called caamalg.
 
+config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
+	tristate "Queue Interface as Crypto API backend"
+	depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET
+	default y
+	select CRYPTO_AUTHENC
+	select CRYPTO_BLKCIPHER
+	help
+	  Selecting this will use CAAM Queue Interface (QI) for sending
+	  & receiving crypto jobs to/from CAAM. This gives better performance
+	  than job ring interface when the number of cores are more than the
+	  number of job rings assigned to the kernel. The number of portals
+	  assigned to the kernel should also be more than the number of
+	  job rings.
+
+	  To compile this as a module, choose M here: the module
+	  will be called caamalg_qi.
+
 config CRYPTO_DEV_FSL_CAAM_AHASH_API
 	tristate "Register hash algorithm implementations with Crypto API"
 	depends on CRYPTO_DEV_FSL_CAAM_JR

@@ -136,4 +153,5 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG
 	  information in the CAAM driver.
 
 config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
-	def_tristate CRYPTO_DEV_FSL_CAAM_CRYPTO_API
+	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
+		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)
drivers/crypto/caam/Makefile +1 -0
index 2e60e45c2bf1..9e2e98856b9b 100644
@@ -8,6 +8,7 @@ endif
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
drivers/crypto/caam/caamalg.c +5 -4
index 9bc80eb06934..398807d1b77e 100644
@@ -266,8 +266,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 
 	/* aead_encrypt shared descriptor */
 	desc = ctx->sh_desc_enc;
-	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,
-			       is_rfc3686, nonce, ctx1_iv_off);
+	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
+			       ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
+			       false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
 

@@ -299,7 +300,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 	desc = ctx->sh_desc_dec;
 	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
 			       ctx->authsize, alg->caam.geniv, is_rfc3686,
-			       nonce, ctx1_iv_off);
+			       nonce, ctx1_iv_off, false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
 

@@ -333,7 +334,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 	desc = ctx->sh_desc_enc;
 	cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
 				  ctx->authsize, is_rfc3686, nonce,
-				  ctx1_iv_off);
+				  ctx1_iv_off, false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
drivers/crypto/caam/caamalg_desc.c +71 -6

134 lines not on this page · raw message

drivers/crypto/caam/caamalg_desc.h +10 -5
index 95551737333a..8731e4a7ff05 100644
@@ -12,6 +12,9 @@
 #define DESC_AEAD_ENC_LEN		(DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
 #define DESC_AEAD_DEC_LEN		(DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
 #define DESC_AEAD_GIVENC_LEN		(DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_ENC_LEN		(DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_DEC_LEN		(DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_GIVENC_LEN		(DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
 
 /* Note: Nonce is counted in cdata.keylen */
 #define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)

@@ -45,20 +48,22 @@ void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
 				 unsigned int icvsize);
 
 void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
-			    struct alginfo *adata, unsigned int icvsize,
-			    const bool is_rfc3686, u32 *nonce,
-			    const u32 ctx1_iv_off);
+			    struct alginfo *adata, unsigned int ivsize,
+			    unsigned int icvsize, const bool is_rfc3686,
+			    u32 *nonce, const u32 ctx1_iv_off,
+			    const bool is_qi);
 
 void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
 			    struct alginfo *adata, unsigned int ivsize,
 			    unsigned int icvsize, const bool geniv,
 			    const bool is_rfc3686, u32 *nonce,
-			    const u32 ctx1_iv_off);
+			    const u32 ctx1_iv_off, const bool is_qi);
 
 void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
 			       struct alginfo *adata, unsigned int ivsize,
 			       unsigned int icvsize, const bool is_rfc3686,
-			       u32 *nonce, const u32 ctx1_iv_off);
+			       u32 *nonce, const u32 ctx1_iv_off,
+			       const bool is_qi);
 
 void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
 			   unsigned int icvsize);
drivers/crypto/caam/caamalg_qi.c new file +2387 -0

2,387 lines not on this page · raw message

drivers/crypto/caam/sg_sw_qm.h new file +108 -0

108 lines not on this page · raw message

Signature · 1 line
2.12.0.264.gd6db3f216544
#8 lore raw

Re: [7/7] crypto: caam/qi - add ablkcipher and authenc algorithms

Quoted 18 lines · Horia Geantă

Add support to submit ablkcipher and authenc algorithms via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geantă <[email protected]>
Quoted 11 lines
---
 drivers/crypto/caam/Kconfig        |   20 +-
 drivers/crypto/caam/Makefile       |    1 +
 drivers/crypto/caam/caamalg.c      |    9 +-
 drivers/crypto/caam/caamalg_desc.c |   77 +-
 drivers/crypto/caam/caamalg_desc.h |   15 +-
 drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_qm.h     |  108 ++
 7 files changed, 2601 insertions(+), 16 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h

This appears to be blowing up my Freescale (NXP) P5020DS board:

  Unable to handle kernel paging request for data at address 0x00000020
  Faulting instruction address: 0xc0000000004393e4
  Oops: Kernel access of bad area, sig: 11 [#1]
  SMP NR_CPUS=24 
  CoreNet Generic
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789 #5
  task: c0000000f70c0000 task.stack: c0000000f70c8000
  NIP: c0000000004393e4 LR: c0000000004aeba0 CTR: c0000000004fa7d8
  REGS: c0000000f70cb160 TRAP: 0300   Not tainted  (4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789)
  MSR: 0000000080029000 <CE,EE,ME>
    CR: 24adbe48  XER: 20000000
  DEAR: 0000000000000020 ESR: 0000000000000000 SOFTE: 1 
  GPR00: c0000000006feba0 c0000000f70cb3e0 c000000000e60000 0000000000000000 
  GPR04: 0000000000000001 0000000000000000 c000000000e0b290 0000000000000003 
  GPR08: 0000000000000004 c000000000ea5280 0000000000000004 0000000000000004 
  GPR12: 0000000088adbe22 c00000003fff5000 c000000000ba3518 8000080088090fa8 
  GPR16: 0000000000001000 c000000000ba3500 c0000000f72c68d8 0000000000000004 
  GPR20: c000000000ea5280 c000000000ba34e8 0000000000000020 0000000000000004 
  GPR24: c000000000eab7c0 0000000000000000 c0000000f7fc8818 c000000000eb0000 
  GPR28: c0000000f786cc00 c000000000eab780 fffffffff786cc00 c000000000eab7c0 
  NIP [c0000000004393e4] .gen_pool_alloc+0x0/0xc
  LR [c0000000004aeba0] .qman_alloc_cgrid_range+0x24/0x54
  Call Trace:
  [c0000000f70cb3e0] [c000000000504054] .platform_device_register_full+0x12c/0x150 (unreliable)
  [c0000000f70cb460] [c0000000006feba0] .caam_qi_init+0x158/0x63c
  [c0000000f70cb5f0] [c0000000006fc64c] .caam_probe+0x8b8/0x1830
  [c0000000f70cb740] [c000000000503288] .platform_drv_probe+0x60/0xac
  [c0000000f70cb7c0] [c000000000501194] .driver_probe_device+0x248/0x344
  [c0000000f70cb870] [c0000000005013b4] .__driver_attach+0x124/0x128
  [c0000000f70cb900] [c0000000004fed90] .bus_for_each_dev+0x80/0xcc
  [c0000000f70cb9a0] [c000000000500858] .driver_attach+0x24/0x38
  [c0000000f70cba10] [c00000000050043c] .bus_add_driver+0x14c/0x29c
  [c0000000f70cbab0] [c000000000501d64] .driver_register+0x8c/0x154
  [c0000000f70cbb30] [c000000000503000] .__platform_driver_register+0x48/0x5c
  [c0000000f70cbba0] [c000000000c7f798] .caam_driver_init+0x1c/0x30
  [c0000000f70cbc10] [c000000000001904] .do_one_initcall+0x60/0x1a8
  [c0000000f70cbcf0] [c000000000c35f30] .kernel_init_freeable+0x248/0x334
  [c0000000f70cbdb0] [c0000000000020fc] .kernel_init+0x1c/0xf20
  [c0000000f70cbe30] [c0000000000009bc] .ret_from_kernel_thread+0x58/0x9c
  Instruction dump:
  eb61ffd8 eb81ffe0 eba1ffe8 ebc1fff0 ebe1fff8 4e800020 38600000 4bffffb0 
  7ce53b78 4bffff0c 7f67db78 4bffff24 <e8a30020> e8c30028 4bfffd30 fbe1fff8 
  ---[ end trace 9f61087068991b02 ]---

home:linux-next(4)(I)> git bisect log
...
git bisect bad b189817cf7894e03fd3700acd923221d3007259e

# first bad commit: [b189817cf7894e03fd3700acd923221d3007259e] crypto: caam/qi - add ablkcipher and authenc algorithms

The oops is saying gen_pool_alloc() was called with a NULL pointer, so it seems qm_cgralloc is NULL:

static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)

{
	unsigned long addr;

	addr = gen_pool_alloc(p, cnt);
	...

int qman_alloc_cgrid_range(u32 *result, u32 count)

{
	return qman_alloc_range(qm_cgralloc, result, count);
}

I didn't pull the thread any further than that.

cheers

author maintainer
#9 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

Quoted 26 lines · Michael Ellerman
Quoted 24 lines · Horia Geant?

Add support to submit ablkcipher and authenc algorithms via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/Kconfig        |   20 +-
 drivers/crypto/caam/Makefile       |    1 +
 drivers/crypto/caam/caamalg.c      |    9 +-
 drivers/crypto/caam/caamalg_desc.c |   77 +-
 drivers/crypto/caam/caamalg_desc.h |   15 +-
Quoted 9 lines
Quoted 5 lines
 drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_qm.h     |  108 ++
 7 files changed, 2601 insertions(+), 16 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h

This appears to be blowing up my Freescale (NXP) P5020DS board:

Michael,

Unfortunately I was not able to reproduce the issue on my P5020DS using the same SHA1 (b189817cf789). Assuming you've used corenet64_smp_defconfig and the p5020ds dts file in this tree.

Roy, Madalin,

This might be a probing order issue b/w CAAM/QI and QMan (drivers/soc/fsl/qbman/qman_ccsr.c) platform drivers. AFAICT the same dependency exists b/w QMan and DPAA Ethernet, thus is should be fixed there too.

CAAM and QMan are sibling devices, having "soc" DT node as parent. Should device link mechanism (Documentation/driver-api/device_link.rst) be used to register the dependency b/w QMan driver (supplier) and CAAM/QI driver (consumer)?

Thanks,
Horia

Quoted 72 lines
  Unable to handle kernel paging request for data at address 0x00000020
  Faulting instruction address: 0xc0000000004393e4
  Oops: Kernel access of bad area, sig: 11 [#1]
  SMP NR_CPUS=24 
  CoreNet Generic
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789 #5
  task: c0000000f70c0000 task.stack: c0000000f70c8000
  NIP: c0000000004393e4 LR: c0000000004aeba0 CTR: c0000000004fa7d8
  REGS: c0000000f70cb160 TRAP: 0300   Not tainted  (4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789)
  MSR: 0000000080029000 <CE,EE,ME>
    CR: 24adbe48  XER: 20000000
  DEAR: 0000000000000020 ESR: 0000000000000000 SOFTE: 1 
  GPR00: c0000000006feba0 c0000000f70cb3e0 c000000000e60000 0000000000000000 
  GPR04: 0000000000000001 0000000000000000 c000000000e0b290 0000000000000003 
  GPR08: 0000000000000004 c000000000ea5280 0000000000000004 0000000000000004 
  GPR12: 0000000088adbe22 c00000003fff5000 c000000000ba3518 8000080088090fa8 
  GPR16: 0000000000001000 c000000000ba3500 c0000000f72c68d8 0000000000000004 
  GPR20: c000000000ea5280 c000000000ba34e8 0000000000000020 0000000000000004 
  GPR24: c000000000eab7c0 0000000000000000 c0000000f7fc8818 c000000000eb0000 
  GPR28: c0000000f786cc00 c000000000eab780 fffffffff786cc00 c000000000eab7c0 
  NIP [c0000000004393e4] .gen_pool_alloc+0x0/0xc
  LR [c0000000004aeba0] .qman_alloc_cgrid_range+0x24/0x54
  Call Trace:
  [c0000000f70cb3e0] [c000000000504054] .platform_device_register_full+0x12c/0x150 (unreliable)
  [c0000000f70cb460] [c0000000006feba0] .caam_qi_init+0x158/0x63c
  [c0000000f70cb5f0] [c0000000006fc64c] .caam_probe+0x8b8/0x1830
  [c0000000f70cb740] [c000000000503288] .platform_drv_probe+0x60/0xac
  [c0000000f70cb7c0] [c000000000501194] .driver_probe_device+0x248/0x344
  [c0000000f70cb870] [c0000000005013b4] .__driver_attach+0x124/0x128
  [c0000000f70cb900] [c0000000004fed90] .bus_for_each_dev+0x80/0xcc
  [c0000000f70cb9a0] [c000000000500858] .driver_attach+0x24/0x38
  [c0000000f70cba10] [c00000000050043c] .bus_add_driver+0x14c/0x29c
  [c0000000f70cbab0] [c000000000501d64] .driver_register+0x8c/0x154
  [c0000000f70cbb30] [c000000000503000] .__platform_driver_register+0x48/0x5c
  [c0000000f70cbba0] [c000000000c7f798] .caam_driver_init+0x1c/0x30
  [c0000000f70cbc10] [c000000000001904] .do_one_initcall+0x60/0x1a8
  [c0000000f70cbcf0] [c000000000c35f30] .kernel_init_freeable+0x248/0x334
  [c0000000f70cbdb0] [c0000000000020fc] .kernel_init+0x1c/0xf20
  [c0000000f70cbe30] [c0000000000009bc] .ret_from_kernel_thread+0x58/0x9c
  Instruction dump:
  eb61ffd8 eb81ffe0 eba1ffe8 ebc1fff0 ebe1fff8 4e800020 38600000 4bffffb0 
  7ce53b78 4bffff0c 7f67db78 4bffff24 <e8a30020> e8c30028 4bfffd30 fbe1fff8 
  ---[ end trace 9f61087068991b02 ]---

home:linux-next(4)(I)> git bisect log
...
git bisect bad b189817cf7894e03fd3700acd923221d3007259e

# first bad commit: [b189817cf7894e03fd3700acd923221d3007259e] crypto: caam/qi - add ablkcipher and authenc algorithms

The oops is saying gen_pool_alloc() was called with a NULL pointer, so it seems qm_cgralloc is NULL:

static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)

{
	unsigned long addr;

	addr = gen_pool_alloc(p, cnt);
	...

int qman_alloc_cgrid_range(u32 *result, u32 count)

{
	return qman_alloc_range(qm_cgralloc, result, count);
}

I didn't pull the thread any further than that.

cheers

#10 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

In reply to Michael Ellerman

Hi Michael,

Just a couple of basic things to check:
- was the dtb updated to the newest?
- is the qman node present? This should be easily visible in
/proc/device-tree/soc at ffe000000/qman at 318000.

---
Best Regards, Laurentiu

Quoted 107 lines · Michael Ellerman
Quoted 27 lines · Horia Geant?

Add support to submit ablkcipher and authenc algorithms via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
  drivers/crypto/caam/Kconfig        |   20 +-
  drivers/crypto/caam/Makefile       |    1 +
  drivers/crypto/caam/caamalg.c      |    9 +-
  drivers/crypto/caam/caamalg_desc.c |   77 +-
  drivers/crypto/caam/caamalg_desc.h |   15 +-
  drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
  drivers/crypto/caam/sg_sw_qm.h     |  108 ++
  7 files changed, 2601 insertions(+), 16 deletions(-)
Quoted 2 lines

create mode 100644 drivers/crypto/caam/caamalg_qi.c create mode 100644 drivers/crypto/caam/sg_sw_qm.h

This appears to be blowing up my Freescale (NXP) P5020DS board:

   Unable to handle kernel paging request for data at address 0x00000020
   Faulting instruction address: 0xc0000000004393e4
   Oops: Kernel access of bad area, sig: 11 [#1]
   SMP NR_CPUS=24
   CoreNet Generic
   Modules linked in:
   CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789 #5
   task: c0000000f70c0000 task.stack: c0000000f70c8000
   NIP: c0000000004393e4 LR: c0000000004aeba0 CTR: c0000000004fa7d8
   REGS: c0000000f70cb160 TRAP: 0300   Not tainted  (4.11.0-rc3-compiler_gcc-4.6.3-00046-gb189817cf789)
   MSR: 0000000080029000 <CE,EE,ME>
     CR: 24adbe48  XER: 20000000
   DEAR: 0000000000000020 ESR: 0000000000000000 SOFTE: 1
   GPR00: c0000000006feba0 c0000000f70cb3e0 c000000000e60000 0000000000000000
   GPR04: 0000000000000001 0000000000000000 c000000000e0b290 0000000000000003
   GPR08: 0000000000000004 c000000000ea5280 0000000000000004 0000000000000004
   GPR12: 0000000088adbe22 c00000003fff5000 c000000000ba3518 8000080088090fa8
   GPR16: 0000000000001000 c000000000ba3500 c0000000f72c68d8 0000000000000004
   GPR20: c000000000ea5280 c000000000ba34e8 0000000000000020 0000000000000004
   GPR24: c000000000eab7c0 0000000000000000 c0000000f7fc8818 c000000000eb0000
   GPR28: c0000000f786cc00 c000000000eab780 fffffffff786cc00 c000000000eab7c0
   NIP [c0000000004393e4] .gen_pool_alloc+0x0/0xc
   LR [c0000000004aeba0] .qman_alloc_cgrid_range+0x24/0x54
   Call Trace:
   [c0000000f70cb3e0] [c000000000504054] .platform_device_register_full+0x12c/0x150 (unreliable)
   [c0000000f70cb460] [c0000000006feba0] .caam_qi_init+0x158/0x63c
   [c0000000f70cb5f0] [c0000000006fc64c] .caam_probe+0x8b8/0x1830
   [c0000000f70cb740] [c000000000503288] .platform_drv_probe+0x60/0xac
   [c0000000f70cb7c0] [c000000000501194] .driver_probe_device+0x248/0x344
   [c0000000f70cb870] [c0000000005013b4] .__driver_attach+0x124/0x128
   [c0000000f70cb900] [c0000000004fed90] .bus_for_each_dev+0x80/0xcc
   [c0000000f70cb9a0] [c000000000500858] .driver_attach+0x24/0x38
   [c0000000f70cba10] [c00000000050043c] .bus_add_driver+0x14c/0x29c
   [c0000000f70cbab0] [c000000000501d64] .driver_register+0x8c/0x154
   [c0000000f70cbb30] [c000000000503000] .__platform_driver_register+0x48/0x5c
   [c0000000f70cbba0] [c000000000c7f798] .caam_driver_init+0x1c/0x30
   [c0000000f70cbc10] [c000000000001904] .do_one_initcall+0x60/0x1a8
   [c0000000f70cbcf0] [c000000000c35f30] .kernel_init_freeable+0x248/0x334
   [c0000000f70cbdb0] [c0000000000020fc] .kernel_init+0x1c/0xf20
   [c0000000f70cbe30] [c0000000000009bc] .ret_from_kernel_thread+0x58/0x9c
   Instruction dump:
   eb61ffd8 eb81ffe0 eba1ffe8 ebc1fff0 ebe1fff8 4e800020 38600000 4bffffb0
   7ce53b78 4bffff0c 7f67db78 4bffff24 <e8a30020> e8c30028 4bfffd30 fbe1fff8
   ---[ end trace 9f61087068991b02 ]---

home:linux-next(4)(I)> git bisect log
...
git bisect bad b189817cf7894e03fd3700acd923221d3007259e

# first bad commit: [b189817cf7894e03fd3700acd923221d3007259e] crypto: caam/qi - add ablkcipher and authenc algorithms

The oops is saying gen_pool_alloc() was called with a NULL pointer, so it seems qm_cgralloc is NULL:

static int qman_alloc_range(struct gen_pool *p, u32 *result, u32 cnt)

{
	unsigned long addr;

	addr = gen_pool_alloc(p, cnt);
	...

int qman_alloc_cgrid_range(u32 *result, u32 count)

{
	return qman_alloc_range(qm_cgralloc, result, count);
}

I didn't pull the thread any further than that.

cheers

#11 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

Quoted 4 lines · Laurentiu Tudor

Hi Michael,

Just a couple of basic things to check:
- was the dtb updated to the newest?

Possibly not, it's an automated build/boot, I'll have to check what it does with the dtb.

Quoted 2 lines

- is the qman node present? This should be easily visible in
/proc/device-tree/soc at ffe000000/qman at 318000.

No it's not there.

That's running linux-next with:

CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=n

Does that mean I didn't update the device tree?

cheers

#12 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

Quoted 13 lines · Michael Ellerman
Quoted 4 lines · Laurentiu Tudor

Hi Michael,

Just a couple of basic things to check:
- was the dtb updated to the newest?

Possibly not, it's an automated build/boot, I'll have to check what it does with the dtb.

Quoted 2 lines

- is the qman node present? This should be easily visible in
/proc/device-tree/soc at ffe000000/qman at 318000.

Quoted 9 lines

No it's not there.

That's running linux-next with:

CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=n

Does that mean I didn't update the device tree?

I think so. Also, I just checked that the node is actually there by compiling p5020ds.dts and then decompiling the dtb.

---
Best Regards, Laurentiu

#13 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

Quoted 18 lines · Laurentiu Tudor
Quoted 17 lines · Michael Ellerman
Quoted 4 lines · Laurentiu Tudor

Hi Michael,

Just a couple of basic things to check:
- was the dtb updated to the newest?

Possibly not, it's an automated build/boot, I'll have to check what it does with the dtb.

Quoted 2 lines

- is the qman node present? This should be easily visible in
/proc/device-tree/soc at ffe000000/qman at 318000.

No it's not there.

That's running linux-next with:

Quoted 7 lines
Quoted 4 lines

CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=n

Does that mean I didn't update the device tree?

I think so. Also, I just checked that the node is actually there by compiling p5020ds.dts and then decompiling the dtb.

OK, I'll make sure I update the DTB.

It will still be good if the code was a bit more robust about the qman being missing.

cheers

#14 lore raw

PATCH 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

-----Original Message-----
From: Michael Ellerman [mailto:mpe at ellerman.id.au]
Sent: Friday, April 07, 2017 4:22 PM
To: Laurentiu Tudor <[email protected]>; Horia Geant? <[email protected]>; Herbert Xu <[email protected]>; Scott Wood <[email protected]>; Roy Pledge <[email protected]>
Cc: Claudiu Manoil <[email protected]>; Cristian Stoica <[email protected]>; Dan Douglass <[email protected]>; linux-arm-kernel at lists.infradead.org; Vakul Garg <[email protected]>; linuxppc-dev at lists.ozlabs.org; David S. Miller <[email protected]>; Alexandru Porosanu <[email protected]>; linux-crypto at vger.kernel.org
Subject: Re: [7/7] crypto: caam/qi - add ablkcipher and authenc algorithms
Importance: High

Quoted 21 lines · Laurentiu Tudor
Quoted 20 lines · Michael Ellerman
Quoted 4 lines · Laurentiu Tudor

Hi Michael,

Just a couple of basic things to check:
- was the dtb updated to the newest?

Possibly not, it's an automated build/boot, I'll have to check what it does with the dtb.

Quoted 2 lines

- is the qman node present? This should be easily visible in
/proc/device-tree/soc at ffe000000/qman at 318000.

No it's not there.

That's running linux-next with:

CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=n

Quoted 8 lines
Quoted 1 line

Does that mean I didn't update the device tree?

I think so. Also, I just checked that the node is actually there by compiling p5020ds.dts and then decompiling the dtb.

OK, I'll make sure I update the DTB.

It will still be good if the code was a bit more robust about the qman being missing.

Totally agree. We should handle this error condition.

---
Thanks & Best Regards, Laurentiu

maintainer
#15 lore raw

cover crypto: caam - add Queue Interface (QI) support

In reply to Horia Geantă
Quoted 16 lines · Horia Geant?

RFC -> v1:
-rebased on latest cryptodev-2.6 tree
open-code tsk_cpus_allowed() - sync with commit 0c98d344fe5c "sched/core: Remove the tsk_cpus_allowed() wrapper" -addressed Scott's feedback - removed most of the accessors added in soc/qman (patch 4) and instead open-coded them in caam/qi

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
During RFC stage, we agreed to go with them through the crypto tree:
https://www.mail-archive.com/linux-crypto at vger.kernel.org/msg24105.html

Quoted 6 lines

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

All patches applied. Thanks.

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
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