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Support for the Turris Omnia router

PATCH Superseded Marek Behun 3 participants 10 messages Jun 6, 2017 – Jun 7, 2017

Subsystems (6)
Arm (32-bit) Arm sub-architectures Char and misc drivers Watchdog device drivers +2 more subsystems

v3 of 4 Superseded Latest is v4 →

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Marek Behun

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#0 lore raw

v3 cover Support for the Turris Omnia router

This is the third version of patches for adding support for the Turris Omnia board, a router developed by the CZ.NIC.

The only modification from the second version is that the device tree added is unmodified, identical to the one in the Linux kernel. The additions are done in a separate, -u-boot.dtsi file.

The first patch modifies Marvell's DDR3 training code to be more general, so that board topology map can force 2t timing.

The second patch adds support for the hardware watchdog which can be found on Omnia. I have modified the driver to use the new driver model API.

The third patch adds the device tree for Turris Omnia taken from Linux kernel and also armada-385-turris-omnia-u-boot.dtsi file with some additions for U-Boot.

The fourth patch adds support for the I2C multiplexer found on Turris Omnia.

The fifth patch adds support for the ATSHA204A CryptoAuthentication chip, on which the Turris Omnia stores serial number and device MAC address.

The sixth patch adds the proper support for the board. I have modified config to use distro defaults as requested by Andreas Faerber and also removed unnecessary comments.

Marek Behun

author
#1 lore raw

PATCH v3 1/6 driver/ddr: Add support for setting timing in hws_topology_map

From: Marek Behún <[email protected]>

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by Marek Behun <[email protected]>
board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
index cade99c8d7..40fa599865 100644
@@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
board/Marvell/db-88f6820-gp/db-88f6820-gp.c +2 -1
index e700781103..a1974cb4bd 100644
@@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
board/gdsys/a38x/controlcenterdc.c +2 -1
index f0efb53447..32168d3576 100644
@@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_533,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
board/solidrun/clearfog/clearfog.c +2 -1
index 3a8257cac3..8906636f76 100644
@@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/
 	BUS_MASK_32BIT			/* Busses mask */
 };
drivers/ddr/marvell/a38x/ddr3_training.c +5 -0
index 7e0749fde3..c79db6af5a 100644
@@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_
 
 			if (mode2_t != 0xff) {
 				t2t = mode2_t;
+			} else if (tm->interface_params[if_id].
+				   timing != HWS_TIM_DEFAULT) {
+				/* Board topology map is forcing timing */
+				t2t = (tm->interface_params[if_id].
+				       timing == HWS_TIM_2T) ? 1 : 0;
 			} else {
 				/* calculate number of CS (per interface) */
 				CHECK_STATUS(calc_cs_num
drivers/ddr/marvell/a38x/ddr_topology_def.h +9 -0
index f8894e828a..229c3a127a 100644
@@ -37,6 +37,12 @@ enum hws_mem_size {
 	MEM_SIZE_LAST
 };
 
+enum hws_timing {
+	HWS_TIM_DEFAULT,
+	HWS_TIM_1T,
+	HWS_TIM_2T
+};
+
 struct bus_params {
 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
 	u8 cs_bitmask;

@@ -84,6 +90,9 @@ struct if_params {
 
 	/* operation temperature */
 	enum hws_temperature interface_temp;
+
+	/* 2T vs 1T mode (by default computed from number of CSs) */
+	enum hws_timing timing;
 };
 
 struct hws_topology_map {
Signature · 1 line
2.13.0
author
#2 lore raw

PATCH v3 1/6 driver/ddr: Add support for setting timing in hws_topology_map

Damn, I forgot to add the change Stefan suggested in this commit. It will be included in next version of the patches.

Quoted 121 lines · On Tue, 6 Jun 2017 14:04:32 +0200 Marek Behun <[email protected]> wrote:

From: Marek Behún <[email protected]>

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by Marek Behun <[email protected]>
(quoted diff) +0 -0

b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index cade99c8d7..40fa599865 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map =
{ MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */ 0,
0, /* cas_l cas_wl */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e700781103..a1974cb4bd 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map =
{ MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */ 0,
0, /* cas_l cas_wl */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/gdsys/a38x/controlcenterdc.c index f0efb53447..32168d3576 100644 --- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c

board/gdsys/a38x/controlcenterdc.c +2 -1
@@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = {
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_533,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/solidrun/clearfog/clearfog.c index 3a8257cac3..8906636f76 100644 --- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c

(quoted diff) +0 -0
@@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map =

{ MEM_4G, /* mem_size */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
 	    DDR_FREQ_800,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..c79db6af5a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ if (mode2_t != 0xff) {

drivers/ddr/marvell/a38x/ddr3_training.c +3 -0
 				t2t = mode2_t;
+			} else if (tm->interface_params[if_id].
+				   timing != HWS_TIM_DEFAULT) {
+				/* Board topology map is forcing

timing */

drivers/ddr/marvell/a38x/ddr3_training.c +2 -0
+				t2t = (tm->interface_params[if_id].
+				       timing == HWS_TIM_2T) ? 1 : 0;
 			} else {
 				/* calculate number of CS (per

interface) */ CHECK_STATUS(calc_cs_num

(quoted diff) +0 -0

b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST
};

drivers/ddr/marvell/a38x/ddr_topology_def.h +9 -0
+enum hws_timing {
+	HWS_TIM_DEFAULT,
+	HWS_TIM_1T,
+	HWS_TIM_2T
+};
+
 struct bus_params {
 	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
 	u8 cs_bitmask;

@@ -84,6 +90,9 @@ struct if_params {
 
 	/* operation temperature */
 	enum hws_temperature interface_temp;
+
+	/* 2T vs 1T mode (by default computed from number of CSs) */
+	enum hws_timing timing;
 };
 
 struct hws_topology_map {
#3 lore raw

PATCH v3 1/6 driver/ddr: Add support for setting timing in hws_topology_map

Hi Marek,

Quoted 2 lines · Marek Behún

Damn, I forgot to add the change Stefan suggested in this commit. It will be included in next version of the patches.

I was just writing a small comment. ;)

Thanks,
Stefan

Quoted 116 lines
Quoted 113 lines · On Tue, 6 Jun 2017 14:04:32 +0200 Marek Behun <[email protected]> wrote:

From: Marek Behún <[email protected]>

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values:
HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
from the number of CSs
HWS_TIM_1T - enforce 1t
HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by Marek Behun <[email protected]>
(quoted diff) +0 -0

b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index cade99c8d7..40fa599865 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map =
{ MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */ 0,
0, /* cas_l cas_wl */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e700781103..a1974cb4bd 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map =
{ MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */ 0,
0, /* cas_l cas_wl */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/gdsys/a38x/controlcenterdc.c index f0efb53447..32168d3576 100644 --- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c

board/gdsys/a38x/controlcenterdc.c +2 -1
@@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = {
  	    MEM_4G,			/* mem_size */
  	    DDR_FREQ_533,		/* frequency */
  	    0, 0,			/* cas_l cas_wl */
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/board/solidrun/clearfog/clearfog.c index 3a8257cac3..8906636f76 100644 --- a/board/solidrun/clearfog/clearfog.c
+++ b/board/solidrun/clearfog/clearfog.c

(quoted diff) +0 -0
@@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map =

{ MEM_4G, /* mem_size */
DDR_FREQ_800, /* frequency */
0, 0, /* cas_l cas_wl */

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +2 -1
-	    HWS_TEMP_LOW} },		/* temperature */
+	    HWS_TEMP_LOW,		/* temperature */
+	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per

Interface*/ BUS_MASK_32BIT /* Busses mask */
};

(quoted diff) +0 -0

b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..c79db6af5a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ if (mode2_t != 0xff) {
t2t = mode2_t;

drivers/ddr/marvell/a38x/ddr3_training.c +3 -0
+			} else if (tm->interface_params[if_id].
+				   timing != HWS_TIM_DEFAULT) {
+				/* Board topology map is forcing

timing */

drivers/ddr/marvell/a38x/ddr3_training.c +2 -0
+				t2t = (tm->interface_params[if_id].
+				       timing == HWS_TIM_2T) ? 1 : 0;
  			} else {
  				/* calculate number of CS (per

interface) */ CHECK_STATUS(calc_cs_num

(quoted diff) +0 -0

b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST
};

drivers/ddr/marvell/a38x/ddr_topology_def.h +6 -0
+enum hws_timing {
+	HWS_TIM_DEFAULT,
+	HWS_TIM_1T,
+	HWS_TIM_2T
+};
+
  struct bus_params {
  	/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
  	u8 cs_bitmask;

@@ -84,6 +90,9 @@ struct if_params {
Quoted 9 lines

drivers/ddr/marvell/a38x/ddr_topology_def.h struct if_params { · line 98

Quoted 8 lines
drivers/ddr/marvell/a38x/ddr_topology_def.h +3 -0
  	/* operation temperature */
  	enum hws_temperature interface_temp;
+
+	/* 2T vs 1T mode (by default computed from number of CSs) */
+	enum hws_timing timing;
  };
 
  struct hws_topology_map {

Viele Grüße,
Stefan

Signature · 3 lines
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
author
#4 lore raw

PATCH v3 2/6 orion_wdt: Support for the Orion Watchdog

In reply to Marek Behun

From: Marek Behún <[email protected]>

The Orion watchdog can be found on some Marvell Armada chips.

This driver is based on the code by Tomas Hlavacek in the CZ.NIC turris-omnia-uboot repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot, and that one is based on code by Sylver Bruneau. His code is already in mainline Linux kernel.

The code uses the new driver model API.

Signed-off-by Tomas Hlavacek <[email protected]>
Signed-off-by Marek Behun <[email protected]>
 create mode 100644 drivers/watchdog/orion_wdt.c
drivers/watchdog/Kconfig +7 -0
index b911233db3..d360a17d4d 100644
@@ -62,4 +62,11 @@ config WDT_BCM6345
 	  The watchdog timer is stopped when initialized.
 	  It performs full SoC reset.
 
+config WDT_ORION
+	bool "Orion watchdog timer support"
+	depends on WDT
+	help
+	   Select this to enable Orion watchdog timer, which can be found on some
+	   Marvell Armada chips.
+
 endmenu
drivers/watchdog/Makefile +1 -0
index 4b19e4ccf6..3230cbb2ad 100644
@@ -20,3 +20,4 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
 obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
 obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
 obj-$(CONFIG_BCM2835_WDT)       += bcm2835_wdt.o
+obj-$(CONFIG_WDT_ORION) += orion_wdt.o
drivers/watchdog/orion_wdt.c new file +177 -0

177 lines not on this page · raw message

Signature · 1 line
2.13.0
author
#5 lore raw

PATCH v3 3/6 arch/arm/dts: Add Turris Omnia device tree

In reply to Marek Behun

From: Marek Behún <[email protected]>

This device tree is taken from mainline Linux kernel commit 7b7db5ab. Added is also a -u-boot.dtsi file with these additions:

- aliases for I2C devices are added, because u-boot i2cmux doesn't work otherwise
- the ATSHA204A node is added in the i2c at 5 node
- "u-boot,dm-pre-reloc"s are added in needed nodes for SPL build to work correctly

Signed-off-by Marek Behun <[email protected]>
 create mode 100644 arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi
 create mode 100644 arch/arm/dts/armada-385-turris-omnia.dts
arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi new file +51 -0
new file mode 100644
index 0000000000..44631e56d7
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2017 Marek Behun <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/ {
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2cmux;
+	};
+};
+
+&i2c0 {
+	u-boot,dm-pre-reloc;
+
+	i2cmux: i2cmux at 70 {
+		u-boot,dm-pre-reloc;
+
+		i2c at 0 {
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c at 1 {
+			u-boot,dm-pre-reloc;
+		};
+
+		i2c at 5 {
+			u-boot,dm-pre-reloc;
+
+			/* ATSHA204A at address 0x64 */
+			atsha204a at 64 {
+				u-boot,dm-pre-reloc;
+				compatible = "atmel,atsha204a";
+				reg = <0x64>;
+			};
+		};
+	};
+};
+
+&spi0 {
+	u-boot,dm-pre-reloc;
+
+	spi-nor at 0 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
arch/arm/dts/armada-385-turris-omnia.dts new file +392 -0

392 lines not on this page · raw message

Signature · 1 line
2.13.0
author
#6 lore raw

PATCH v3 4/6 drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support

In reply to Marek Behun

From: Marek Behún <[email protected]>

This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by Marek Behun <[email protected]>
drivers/i2c/muxes/pca954x.c +39 -3
index 1a6761858c..383f72f552 100644
@@ -13,11 +13,40 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum pca_type {
+	PCA9544,
+	PCA9547,
+	PCA9548
+};
+
+struct chip_desc {
+	u8 enable;
+	enum muxtype {
+		pca954x_ismux = 0,
+		pca954x_isswi,
+	} muxtype;
+};
+
 struct pca954x_priv {
 	u32 addr; /* I2C mux address */
 	u32 width; /* I2C mux width - number of busses */
 };
 
+static const struct chip_desc chips[] = {
+	[PCA9544] = {
+		.enable = 0x4,
+		.muxtype = pca954x_ismux,
+	},
+	[PCA9547] = {
+		.enable = 0x8,
+		.muxtype = pca954x_ismux,
+	},
+	[PCA9548] = {
+		.enable = 0x8,
+		.muxtype = pca954x_isswi,
+	},
+};
+
 static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
 			    uint channel)
 {

@@ -31,7 +60,13 @@ static int pca954x_select(struct udevice *mux, struct udevice *bus,
 			  uint channel)
 {
 	struct pca954x_priv *priv = dev_get_priv(mux);
-	uchar byte = 1 << channel;
+	const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];
+	uchar byte;
+
+	if (chip->muxtype == pca954x_ismux)
+		byte = channel | chip->enable;
+	else
+		byte = 1 << channel;
 
 	return dm_i2c_write(mux, priv->addr, &byte, 1);
 }

@@ -42,8 +77,9 @@ static const struct i2c_mux_ops pca954x_ops = {
 };
 
 static const struct udevice_id pca954x_ids[] = {
-	{ .compatible = "nxp,pca9548", .data = (ulong)8 },
-	{ .compatible = "nxp,pca9544", .data = (ulong)4 },
+	{ .compatible = "nxp,pca9544", .data = PCA9544 },
+	{ .compatible = "nxp,pca9547", .data = PCA9547 },
+	{ .compatible = "nxp,pca9548", .data = PCA9548 },
 	{ }
 };
Signature · 1 line
2.13.0
#7 lore raw

PATCH v3 4/6 drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support

Hello Marek,

Am 06.06.2017 um 14:04 schrieb Marek Behun:

Quoted 5 lines

From: Marek Behún <[email protected]>

This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by Marek Behun <[email protected]>
Reviewed-by Heiko Schocher <[email protected]>

bye,
Heiko

Quoted 74 lines
drivers/i2c/muxes/pca954x.c +39 -3
index 1a6761858c..383f72f552 100644
@@ -13,11 +13,40 @@
 
  DECLARE_GLOBAL_DATA_PTR;
 
+enum pca_type {
+	PCA9544,
+	PCA9547,
+	PCA9548
+};
+
+struct chip_desc {
+	u8 enable;
+	enum muxtype {
+		pca954x_ismux = 0,
+		pca954x_isswi,
+	} muxtype;
+};
+
  struct pca954x_priv {
  	u32 addr; /* I2C mux address */
  	u32 width; /* I2C mux width - number of busses */
  };
 
+static const struct chip_desc chips[] = {
+	[PCA9544] = {
+		.enable = 0x4,
+		.muxtype = pca954x_ismux,
+	},
+	[PCA9547] = {
+		.enable = 0x8,
+		.muxtype = pca954x_ismux,
+	},
+	[PCA9548] = {
+		.enable = 0x8,
+		.muxtype = pca954x_isswi,
+	},
+};
+
  static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
  			    uint channel)
  {

@@ -31,7 +60,13 @@ static int pca954x_select(struct udevice *mux, struct udevice *bus,
  			  uint channel)
  {
  	struct pca954x_priv *priv = dev_get_priv(mux);
-	uchar byte = 1 << channel;
+	const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];
+	uchar byte;
+
+	if (chip->muxtype == pca954x_ismux)
+		byte = channel | chip->enable;
+	else
+		byte = 1 << channel;
 
  	return dm_i2c_write(mux, priv->addr, &byte, 1);
  }

@@ -42,8 +77,9 @@ static const struct i2c_mux_ops pca954x_ops = {
  };
 
  static const struct udevice_id pca954x_ids[] = {
-	{ .compatible = "nxp,pca9548", .data = (ulong)8 },
-	{ .compatible = "nxp,pca9544", .data = (ulong)4 },
+	{ .compatible = "nxp,pca9544", .data = PCA9544 },
+	{ .compatible = "nxp,pca9547", .data = PCA9547 },
+	{ .compatible = "nxp,pca9548", .data = PCA9548 },
  	{ }
  };
Signature · 2 lines
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
author
#8 lore raw

PATCH v3 5/6 drivers/misc: Add basic support for ATSHA204A Crypto module

In reply to Marek Behun

From: Marek Behún <[email protected]>

This module can be found on the Turris Omnia board connected via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit One Time Programmable memory, 88 byte configuration memory and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in the OTP memory.

This commit adds basic support for reading the EEPROM and also exposes the chips Random Number Generator.

The driver is based on code by
Josh Datko, Cryptotronix, jbd at cryptotronix.com
and also
Tomas Hlavacek, CZ.NIC, tomas.hlavacek at nic.cz

Signed-off-by Tomas Hlavacek <[email protected]>
Signed-off-by Marek Behun <[email protected]>
 create mode 100644 drivers/misc/atsha204a-i2c.c
 create mode 100644 include/atsha204a-i2c.h
drivers/misc/Kconfig +8 -0
index ecca159d14..8073cdc628 100644
@@ -20,6 +20,14 @@ config ALTERA_SYSID
 	  Select this to enable a sysid for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ATSHA204A
+	bool "Support for Atmel ATSHA204A module"
+	depends on MISC
+	help
+	   Enable support for I2C connected Atmel's ATSHA204A
+	   CryptoAuthentication module found for example on the Turris Omnia
+	   board.
+
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC
drivers/misc/Makefile +1 -0
index 4543cd647e..bb51f9fafe 100644
@@ -8,6 +8,7 @@
 obj-$(CONFIG_MISC) += misc-uclass.o
 obj-$(CONFIG_ALI152X) += ali512x.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
+obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
 obj-$(CONFIG_DS4510)  += ds4510.o
 obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
 ifndef CONFIG_SPL_BUILD
drivers/misc/atsha204a-i2c.c new file +307 -0

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include/atsha204a-i2c.h new file +69 -0

69 lines not on this page · raw message

Signature · 1 line
2.13.0
author
#9 lore raw

PATCH v3 6/6 marvell: armada385: Add the Turris Omnia board

In reply to Marek Behun

From: Marek Behún <[email protected]>

The Turris Omnia is a open-source router created by CZ.NIC.

The code is based on the Marvell/db-88f6820-gp by Stefan Roese with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot repository, which can be found at
https://gitlab.labs.nic.cz/turris/turris-omnia-uboot

By default, the Turris Omnia uses btrfs as the main and only filesystem, and also loads kernel and device tree from this filesystem. Since U-Boot does not yet support btrfs, you should not flash your Turris Omnia board with this unless you know what you are doing.

Signed-off-by Tomas Hlavacek <[email protected]>
Signed-off-by Marek Behun <[email protected]>
 create mode 100644 board/CZ.NIC/turris_omnia/Makefile
 create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg
 create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c
 create mode 100644 configs/turris_omnia_defconfig
 create mode 100644 include/configs/turris_omnia.h
arch/arm/mach-mvebu/Kconfig +22 -0
index 6ae54ef46a..6b16f57464 100644
@@ -90,6 +90,10 @@ config TARGET_DB_88F6820_AMC
 	bool "Support DB-88F6820-AMC"
 	select 88F6820
 
+config TARGET_TURRIS_OMNIA
+	bool "Support Turris Omnia"
+	select 88F6820
+
 config TARGET_MVEBU_ARMADA_8K
 	bool "Support Armada 7k/8k platforms"
 	select ARMADA_8K

@@ -124,6 +128,7 @@ config SYS_BOARD
 	default "db-88f6720" if TARGET_DB_88F6720
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
+	default "turris_omnia" if TARGET_TURRIS_OMNIA
 	default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
 	default "ds414" if TARGET_DS414

@@ -141,6 +146,7 @@ config SYS_CONFIG_NAME
 	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
 	default "theadorable" if TARGET_THEADORABLE
+	default "turris_omnia" if TARGET_TURRIS_OMNIA
 
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP

@@ -151,10 +157,26 @@ config SYS_VENDOR
 	default "Marvell" if TARGET_MVEBU_ARMADA_8K
 	default "solidrun" if TARGET_CLEARFOG
 	default "Synology" if TARGET_DS414
+	default "CZ.NIC" if TARGET_TURRIS_OMNIA
 
 config SYS_SOC
 	default "mvebu"
 
+if TARGET_TURRIS_OMNIA
+
+choice
+	prompt "Turris Omnia boot method"
+
+config TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI
+	bool "SPI NOR flash"
+
+config TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC
+	bool "SDIO/MMC card"
+
+endchoice
+
+endif
+
 config MVEBU_EFUSE
 	bool "Enable eFuse support"
 	default n
board/CZ.NIC/turris_omnia/Makefile new file +7 -0
new file mode 100644
index 0000000000..f2ae50654f
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2017 Marek Behun <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= turris_omnia.o
board/CZ.NIC/turris_omnia/kwbimage.cfg new file +12 -0
new file mode 100644
index 0000000000..cc05792556
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <[email protected]>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl.bin 0000005b 00000068
board/CZ.NIC/turris_omnia/turris_omnia.c new file +504 -0

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configs/turris_omnia_defconfig new file +62 -0

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include/configs/turris_omnia.h new file +174 -0

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Signature · 1 line
2.13.0