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powerpc, 8xx: Implement GLL2 ERRATA

PATCH New Christophe Leroy 4 participants 4 messages Jul 6, 2017 – Jul 9, 2017 PowerPC

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Christophe Leroy

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#0 lore raw

PATCH 4/10 powerpc, 8xx: Implement GLL2 ERRATA

Signed-off-by Christophe Leroy <[email protected]>

---
Takes into account comments received from Wolfgang and Heiko. Superseeds the one included in v2 of the serie 'powerpc, 8xx:
Modernise the 8xx'. Not resending the entire serie.

 arch/powerpc/cpu/mpc8xx/cpu_init.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
arch/powerpc/cpu/mpc8xx/cpu_init.c +20 -0
index cf1280983a..a51596a583 100644
@@ -51,6 +51,26 @@ void cpu_init_f(immap_t __iomem *immr)
 	clrsetbits_be32(&immr->im_clkrst.car_sccr, ~SCCR_MASK,
 			CONFIG_SYS_SCCR);
 
+	/*
+	 * MPC866/885 ERRATA GLL2
+	 * Description:
+	 *   In 1:2:1 mode, when HRESET is detected at the positive edge of
+	 *   EXTCLK, then there will be a loss of phase between
+	 *   EXTCLK and CLKOUT.
+	 *
+	 * Workaround:
+	 *   Reprogram the SCCR:
+	 *   1.   Write 1'b00 to SCCR[EBDF].
+	 *   2.   Write 1'b01 to SCCR[EBDF].
+	 *   3.   Rewrite the desired value to the PLPRCR register.
+	 */
+	reg = in_be32(&immr->im_clkrst.car_sccr);
+	/* Are we in mode 1:2:1 ? */
+	if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
+		clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
+		setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
+	}
+
 	/* PLL (CPU clock) settings (15-30) */
 
 	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
Signature · 1 line
2.12.0
#1 lore raw

PATCH 4/10 powerpc, 8xx: Implement GLL2 ERRATA

Dear Christophe,

Quoted 8 lines · In message <[email protected]> you wrote:
Signed-off-by Christophe Leroy <[email protected]>

---
Takes into account comments received from Wolfgang and Heiko. Superseeds the one included in v2 of the serie 'powerpc, 8xx:
Modernise the 8xx'. Not resending the entire serie.

 arch/powerpc/cpu/mpc8xx/cpu_init.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Thanks.

Acked-by Wolfgang Denk <[email protected]>

Best regards,

Wolfgang Denk

Signature · 4 lines
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I'd rather be led to hell than managed to heaven.
#2 lore raw

PATCH 4/10 powerpc, 8xx: Implement GLL2 ERRATA

In reply to Christophe Leroy

Hello Christophe,

Am 06.07.2017 um 16:49 schrieb Christophe Leroy:

Quoted 8 lines
Signed-off-by Christophe Leroy <[email protected]>

---
Takes into account comments received from Wolfgang and Heiko. Superseeds the one included in v2 of the serie 'powerpc, 8xx:
Modernise the 8xx'. Not resending the entire serie.

  arch/powerpc/cpu/mpc8xx/cpu_init.c | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)

Thanks!

Reviewed-by Heiko Schocher <[email protected]>

bye,
Heiko

Signature · 3 lines
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
#3 lore raw

PATCH 4/10 powerpc, 8xx: Implement GLL2 ERRATA

In reply to Christophe Leroy
Quoted 3 lines · Christophe Leroy
Signed-off-by Christophe Leroy <[email protected]>
Acked-by Wolfgang Denk <[email protected]>
Reviewed-by Heiko Schocher <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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