SMP and CPU hotplug support for Meson8/Meson8b

From: Carlo Caione <[email protected]>

With this patch we add documentation for:

* power-management-unit: the PMU is used to bring up the cores during SMP operations
* sram: among other things the sram is used to store the first code executed by the core when it is powered up
* cpu-enable-method: the CPU enable method used by Amlogic Meson8 and Meson8b SoCs

Signed-off-by Carlo Caione <[email protected]>

[also add Meson8 to the documentation]

Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Rob Herring <[email protected]>

---
 .../devicetree/bindings/arm/amlogic/pmu.txt        | 18 ++++++++++++
 .../devicetree/bindings/arm/amlogic/smp-sram.txt   | 32 ++++++++++++++++++++++
 Documentation/devicetree/bindings/arm/cpus.txt     |  2 ++
 3 files changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt
 create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt

Documentation/devicetree/bindings/arm/amlogic/pmu.txt new file +18 -0

new file mode 100644
index 000000000000..72f8d08198b6
@@ -0,0 +1,18 @@
+Amlogic Meson8 and Meson8b power-management-unit:
+-------------------------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : depending on the SoC this should be one of:
+			"amlogic,meson8-pmu"
+			"amlogic,meson8b-pmu"
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	pmu at c81000e4 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xc81000e0 0x18>;
+	};

Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt new file +32 -0

new file mode 100644
index 000000000000..3473ddaadfac
@@ -0,0 +1,32 @@
+Amlogic Meson8 and Meson8b SRAM for smp bringup:
+------------------------------------------------
+
+Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
+Once the core gets powered up it executes the code that is residing at a
+specific location.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+		"amlogic,meson8-smp-sram"
+		"amlogic,meson8b-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+	sram: sram at d9000000 {
+		compatible = "mmio-sram";
+		reg = <0xd9000000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xd9000000 0x20000>;
+
+		smp-sram at 1ff80 {
+			compatible = "amlogic,meson8b-smp-sram";
+			reg = <0x1ff80 0x8>;
+		};
+	};

Documentation/devicetree/bindings/arm/cpus.txt +0 -0

index a44253cad269..1ef3e53b9be7 100644

This adds the necessary SMP-operations and startup code to use the additional cores on the Amlogic Meson8/Meson8m2 (both are using the same
sequence) and Meson8b (using a slightly difference sequence) SoCs.

Signed-off-by Carlo Caione <[email protected]>

[add Meson8/Meson8m2 support and allow taking CPU cores offline as well]

Signed-off-by Martin Blumenstingl <[email protected]>

---

arch/arm/mach-meson/platsmp.c new file +4 -0

+static void meson_smp_begin_secondary_boot(unsigned int cpu)
+{
+	/*
+	 * Set the entry point before powering on the CPU through the SCU.

This

arch/arm/mach-meson/platsmp.c new file +13 -0

+
+	/*
+	 * SCU Power on CPU (needs to be done before starting the CPU,
+	 * otherwise the secondary CPU will not start).
+	 */
+	scu_cpu_power_enable(scu_base, cpu);
+}
+
+static int meson_smp_finalize_secondary_boot(unsigned int cpu)
+{
+	unsigned long timeout;
+
+	timeout = jiffies + (10 * HZ);

Export the soft reset lines for the CPU cores so they can be used in the dt-bindings (required for SMP booting the CPU cores).

Signed-off-by Martin Blumenstingl <[email protected]>

---
 drivers/clk/meson/meson8b.h              | 8 ++++----
 include/dt-bindings/clock/meson8b-clkc.h | 7 ++++++-
 2 files changed, 10 insertions(+), 5 deletions(-)

drivers/clk/meson/meson8b.h +4 -4

index 5f4d8e49dd4d..d6e35c1acc05 100644
@@ -169,10 +169,10 @@
 #define RESETID_L2_CACHE_SOFT_RESET				0
 #define RESETID_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET		1
 #define RESETID_SCU_SOFT_RESET					2
-#define RESETID_CPU0_SOFT_RESET					3
-#define RESETID_CPU1_SOFT_RESET					4
-#define RESETID_CPU2_SOFT_RESET					5
-#define RESETID_CPU3_SOFT_RESET					6
+/* RESETID_CPU0_SOFT_RESET */
+/* RESETID_CPU1_SOFT_RESET */
+/* RESETID_CPU2_SOFT_RESET */
+/* RESETID_CPU3_SOFT_RESET */
 #define RESETID_A5_GLOBAL_RESET					7
 #define RESETID_A5_AXI_SOFT_RESET				8
 #define RESETID_A5_ABP_SOFT_RESET				9

include/dt-bindings/clock/meson8b-clkc.h +1 -1

index e29227fb52a1..76920cfd1f33 100644
@@ -1,5 +1,5 @@
 /*
- * Meson8b clock tree IDs
+ * Meson8b clock and reset tree IDs
  */
 
 #ifndef __MESON8B_CLKC_H

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU cores
- a range in the SRAM specifically reserved for booting secondary CPU cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU cores.

Suggested-by Carlo Caione <[email protected]>

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/boot/dts/meson8.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

arch/arm/boot/dts/meson8.dtsi +13 -0

index b98d44fde6b6..44515733df29 100644
@@ -60,6 +60,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
 		};
 
 		cpu at 201 {

@@ -67,6 +69,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
 		};
 
 		cpu at 202 {

@@ -74,6 +78,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
 		};
 
 		cpu at 203 {

@@ -81,6 +87,8 @@
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8-smp";
+			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
 		};
 	};
 

@@ -118,6 +126,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu at e0 {
+		compatible = "amlogic,meson8-pmu", "syscon";
+		reg = <0xe0 0x8>;
+	};
+
 	pinctrl_aobus: pinctrl at 84 {
 		compatible = "amlogic,meson8-aobus-pinctrl";
 		reg = <0x84 0xc>;

@@ -249,6 +262,13 @@
 	};
 };
 

From: Carlo Caione <[email protected]>

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU cores
- a range in the SRAM specifically reserved for booting secondary CPU cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU cores.

Signed-off-by Carlo Caione <[email protected]>

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

arch/arm/boot/dts/meson8b.dtsi +13 -0

index bc278da7df0d..c9e74d2fcbdf 100644
@@ -59,6 +59,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU0_SOFT_RESET>;
 		};
 
 		cpu at 201 {

@@ -66,6 +68,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU1_SOFT_RESET>;
 		};
 
 		cpu at 202 {

@@ -73,6 +77,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU2_SOFT_RESET>;
 		};
 
 		cpu at 203 {

@@ -80,6 +86,8 @@
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc RESETID_CPU3_SOFT_RESET>;
 		};
 	};
 

@@ -90,6 +98,11 @@
 }; /* end of / */
 
 &aobus {
+	pmu: pmu at e0 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xe0 0x18>;
+	};
+
 	pinctrl_aobus: pinctrl at 84 {
 		compatible = "amlogic,meson8b-aobus-pinctrl";
 		reg = <0x84 0xc>;

@@ -157,6 +170,13 @@
 	};
 };