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arm64: dts: hisi: add PCIe host controller node for hip07 SoC

PATCH New Zhou Wang 2 participants 3 messages Jul 18, 2017 – Aug 7, 2017

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Device tree bindings Arm/HiSilicon SoC support
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Zhou Wang

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#0 lore raw

PATCH 1/1 arm64: dts: hisi: add PCIe host controller node for hip07 SoC

Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in D05 board.

Signed-off-by Zhou Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)
arch/arm64/boot/dts/hisilicon/hip07-d05.dts +4 -0
index f5d7f08..fe7c16c 100644
@@ -84,3 +84,7 @@
 &sas1 {
 	status = "ok";
 };
+
+&p0_pcie2_a {
+	status = "ok";
+};
arch/arm64/boot/dts/hisilicon/hip07.dtsi +21 -0
index 283d7b5..077b2d7b 100644
@@ -1534,5 +1534,26 @@
 				     <637 1>,<638 1>,<639 1>;
 			status = "disabled";
 		};
+
+		p0_pcie2_a: pcie at a00a0000 {
+			compatible = "hisilicon,pcie-almost-ecam";
+			reg = <0 0xa8000000 0 0x800000>,<0 0xa00a0000 0 0x10000>;
+			bus-range = <0x80 0x87>;
+			msi-map = <0x8000 &p0_its_dsa_a 0x8000 0x800>;
+			msi-map-mask = <0xffff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			ranges = <0x02000000 0 0xa8800000 0 0xa8800000 0 0x77f0000
+				  0x01000000 0 0 0 0xafff0000 0 0x10000>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
+					 0x0 0 0 2 &mbigen_pcie2_a 671 4
+					 0x0 0 0 3 &mbigen_pcie2_a 671 4
+					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
+			status = "disabled";
+		};
 	};
 };
Signature · 1 line
1.9.1
maintainer
#1 lore raw

PATCH 1/1 arm64: dts: hisi: add PCIe host controller node for hip07 SoC

Hi Zhou,

Quoted 26 lines · Zhou Wang

Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in D05 board.

Signed-off-by Zhou Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)
arch/arm64/boot/dts/hisilicon/hip07-d05.dts +4 -0
index f5d7f08..fe7c16c 100644
@@ -84,3 +84,7 @@
 &sas1 {
 	status = "ok";
 };
+
+&p0_pcie2_a {
+	status = "ok";
+};
arch/arm64/boot/dts/hisilicon/hip07.dtsi +0 -0
index 283d7b5..077b2d7b 100644

arch/arm64/boot/dts/hisilicon/hip07.dtsi line 1539

Quoted 6 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +3 -0
@@ -1534,5 +1534,26 @@
 				     <637 1>,<638 1>,<639 1>;
 			status = "disabled";
 		};
+
+		p0_pcie2_a: pcie at a00a0000 {
+			compatible = "hisilicon,pcie-almost-ecam";

The compatible string should be "hisilicon,hip07-pcie-ecam".

arch/arm64/boot/dts/hisilicon/hip07.dtsi line 1549

Quoted 10 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +10 -0
+			reg = <0 0xa8000000 0 0x800000>,<0 0xa00a0000 0 0x10000>;
+			bus-range = <0x80 0x87>;
+			msi-map = <0x8000 &p0_its_dsa_a 0x8000 0x800>;
+			msi-map-mask = <0xffff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			ranges = <0x02000000 0 0xa8800000 0 0xa8800000 0 0x77f0000
+				  0x01000000 0 0 0 0xafff0000 0 0x10000>;

Can you also check whether the ranges are working or not with current UEFI? Thanks!

Best Regards,
Wei

Quoted 11 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +8 -0
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
+					 0x0 0 0 2 &mbigen_pcie2_a 671 4
+					 0x0 0 0 3 &mbigen_pcie2_a 671 4
+					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
+			status = "disabled";
+		};
 	};
 };
author
#2 lore raw

PATCH 1/1 arm64: dts: hisi: add PCIe host controller node for hip07 SoC

Quoted 29 lines · Wei Xu

Hi Zhou,

Quoted 26 lines · Zhou Wang

Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in D05 board.

Signed-off-by Zhou Wang <[email protected]>
---
 arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  4 ++++
 arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 21 +++++++++++++++++++++
 2 files changed, 25 insertions(+)
arch/arm64/boot/dts/hisilicon/hip07-d05.dts +4 -0
index f5d7f08..fe7c16c 100644
@@ -84,3 +84,7 @@
 &sas1 {
 	status = "ok";
 };
+
+&p0_pcie2_a {
+	status = "ok";
+};
arch/arm64/boot/dts/hisilicon/hip07.dtsi +0 -0
index 283d7b5..077b2d7b 100644
@@ -1534,5 +1534,26 @@
Quoted 8 lines

arch/arm64/boot/dts/hisilicon/hip07.dtsi line 1539

Quoted 6 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +3 -0
 				     <637 1>,<638 1>,<639 1>;
 			status = "disabled";
 		};
+
+		p0_pcie2_a: pcie at a00a0000 {
+			compatible = "hisilicon,pcie-almost-ecam";

The compatible string should be "hisilicon,hip07-pcie-ecam".

OK, I will modify this and resend it later.

Quoted 14 lines

arch/arm64/boot/dts/hisilicon/hip07.dtsi line 1549

Quoted 11 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +10 -0
+			reg = <0 0xa8000000 0 0x800000>,<0 0xa00a0000 0 0x10000>;
+			bus-range = <0x80 0x87>;
+			msi-map = <0x8000 &p0_its_dsa_a 0x8000 0x800>;
+			msi-map-mask = <0xffff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			dma-coherent;
+			ranges = <0x02000000 0 0xa8800000 0 0xa8800000 0 0x77f0000
+				  0x01000000 0 0 0 0xafff0000 0 0x10000>;

Can you also check whether the ranges are working or not with current UEFI? Thanks!

Sure.

Thanks,
Zhou

Quoted 19 lines

Best Regards,
Wei

arch/arm64/boot/dts/hisilicon/hip07.dtsi line 1559

Quoted 11 lines
arch/arm64/boot/dts/hisilicon/hip07.dtsi +8 -0
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
+					 0x0 0 0 2 &mbigen_pcie2_a 671 4
+					 0x0 0 0 3 &mbigen_pcie2_a 671 4
+					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
+			status = "disabled";
+		};
 	};
 };

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