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arm64: dts: hi6220: add acpu_sctrl

PATCH New Zhangfei Gao 2 participants 2 messages Aug 16, 2017

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Device tree bindings Arm/HiSilicon SoC support
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Zhangfei Gao

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#0 lore raw

PATCH v2 1/1 arm64: dts: hi6220: add acpu_sctrl

Add acpu_sctrl clock node

Signed-off-by Zhangfei Gao <[email protected]>
Signed-off-by Li Pengcheng <[email protected]>

---
Update name to acpu_sctrl at f6504000

 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +6 -0
index eacbe0d..f8012d5 100644
@@ -262,6 +262,12 @@
 			#clock-cells = <1>;
 		};
 
+		acpu_sctrl: acpu_sctrl at f6504000 {
+			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
+			reg = <0x0 0xf6504000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		medianoc_ade: medianoc_ade at f4520000 {
 			compatible = "syscon";
 			reg = <0x0 0xf4520000 0x0 0x4000>;
Signature · 1 line
2.7.4
maintainer
#1 lore raw

PATCH v2 1/1 arm64: dts: hi6220: add acpu_sctrl

Hi Zhangfei,

Quoted 18 lines · Zhangfei Gao

Add acpu_sctrl clock node

Signed-off-by Zhangfei Gao <[email protected]>
Signed-off-by Li Pengcheng <[email protected]>

---
Update name to acpu_sctrl at f6504000

 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +0 -0
index eacbe0d..f8012d5 100644
@@ -262,6 +262,12 @@
 			#clock-cells = <1>;
 		};

arch/arm64/boot/dts/hisilicon/hi6220.dtsi line 273

Quoted 10 lines
arch/arm64/boot/dts/hisilicon/hi6220.dtsi +6 -0
 
+		acpu_sctrl: acpu_sctrl at f6504000 {
+			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
+			reg = <0x0 0xf6504000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		medianoc_ade: medianoc_ade at f4520000 {
 			compatible = "syscon";
 			reg = <0x0 0xf4520000 0x0 0x4000>;

Thanks!
Dropped the v1 and applied v2 to the hisilicon dt tree.

Best Regards,
Wei