clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk

PATCH New Sylwester Nawrocki 2 participants 6 messages Mar 7, 2018 – Mar 12, 2018 1 message not in the archive

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Common clk Arm Samsung Exynos Samsung SoC clock drivers

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A message that is not in the archive (sent off-list or not yet received): CGME20180307164708epcas1p27e6599e85617f559c5c4c8eb92a70a47@epcas1p2.samsung.com

Sylwester Nawrocki

author maintainer

2018-03-07 16:46 UTC #1 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk

This allows changing the EPLL output frequency through the audio subsystem clock tree leaf clocks. This change is needed to support audio on the HDMI interface on Peach-Pi(t) Chromebook.

Signed-off-by Sylwester Nawrocki <[email protected]>

---
 drivers/clk/samsung/clk-exynos5420.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

drivers/clk/samsung/clk-exynos5420.c +2 -1

index 8c050ff63536..1f204ba37f0f 100644
@@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 			mout_group5_5800_p, SRC_TOP7, 16, 2),
-	MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
+	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
+	      CLK_SET_RATE_PARENT, 0),
 
 	MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 };

Signature · 1 line

2.14.2

Sylwester Nawrocki

author maintainer

2018-03-07 16:46 UTC #2 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add more entries to EPLL rate table

Adding these EPLL output frequency entries allows to support all required audio sample rates on the CODEC and the HDMI interface on Peach-Pit Chromebook.

Signed-off-by Sylwester Nawrocki <[email protected]>

---
 drivers/clk/samsung/clk-exynos5420.c | 3 +++
 1 file changed, 3 insertions(+)

drivers/clk/samsung/clk-exynos5420.c +3 -0

index 1f204ba37f0f..f2607cb97a97 100644
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
 	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
 	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
 	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
+	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
 	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
 	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
+	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
 	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
 };

Signature · 1 line

2.14.2

Chanwoo Choi

maintainer

2018-03-08 01:55 UTC #3 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add more entries to EPLL rate table

Quoted 16 lines · Sylwester Nawrocki

Adding these EPLL output frequency entries allows to support all required audio sample rates on the CODEC and the HDMI interface on Peach-Pit Chromebook.
Signed-off-by Sylwester Nawrocki <[email protected]>
---
 drivers/clk/samsung/clk-exynos5420.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +0 -0
index 1f204ba37f0f..f2607cb97a97 100644
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
 	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { · line 1370

Quoted 10 lines

drivers/clk/samsung/clk-exynos5420.c +3 -0

 	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
 	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
+	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
 	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
 	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
+	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
 	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
 };

Looks good to me.

Acked-by Chanwoo Choi <[email protected]>

Signature · 3 lines

Best Regards,
Chanwoo Choi
Samsung Electronics

Sylwester Nawrocki

author maintainer

2018-03-12 10:31 UTC #4 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add more entries to EPLL rate table

Quoted 28 lines · Chanwoo Choi

Quoted 16 lines · Sylwester Nawrocki
Adding these EPLL output frequency entries allows to support all required audio sample rates on the CODEC and the HDMI interface on Peach-Pit Chromebook.
Signed-off-by Sylwester Nawrocki <[email protected]>
---
 drivers/clk/samsung/clk-exynos5420.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/samsung/clk-exynos5420.c +0 -0
index 1f204ba37f0f..f2607cb97a97 100644
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
 	PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
drivers/clk/samsung/clk-exynos5420.c static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { · line 1370
Quoted 10 lines
drivers/clk/samsung/clk-exynos5420.c +3 -0
 	PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
 	PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+	PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
+	PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
 	PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
 	PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
+	PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
 	PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
 };
 
Looks good to me.

Quoted 1 line

Acked-by Chanwoo Choi <[email protected]>

Thanks for your review, patch applied to the clk/samsung tree.

Signature · 2 lines

Regards,
Sylwester

Chanwoo Choi

maintainer

2018-03-08 02:25 UTC #5 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk

In reply to Sylwester Nawrocki

Hi Sylwester,

Quoted 15 lines · Sylwester Nawrocki

This allows changing the EPLL output frequency through the audio subsystem clock tree leaf clocks. This change is needed to support audio on the HDMI interface on Peach-Pi(t) Chromebook.
Signed-off-by Sylwester Nawrocki <[email protected]>
---
 drivers/clk/samsung/clk-exynos5420.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +0 -0
index 8c050ff63536..1f204ba37f0f 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { · line 628

Quoted 9 lines

drivers/clk/samsung/clk-exynos5420.c +2 -1

@@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 			mout_group5_5800_p, SRC_TOP7, 16, 2),
-	MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
+	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
+	      CLK_SET_RATE_PARENT, 0),
 
 	MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 };

Looks good to me.

Acked-by Chanwoo Choi <[email protected]>

Signature · 3 lines

Best Regards,
Chanwoo Choi
Samsung Electronics

Sylwester Nawrocki

author maintainer

2018-03-12 10:29 UTC #6 lore raw

PATCH 1/1 clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk

Quoted 22 lines · Chanwoo Choi

Quoted 21 lines · Sylwester Nawrocki
This allows changing the EPLL output frequency through the audio subsystem clock tree leaf clocks. This change is needed to support audio on the HDMI interface on Peach-Pi(t) Chromebook.
Signed-off-by Sylwester Nawrocki <[email protected]>
---
 drivers/clk/samsung/clk-exynos5420.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/clk/samsung/clk-exynos5420.c +2 -1
index 8c050ff63536..1f204ba37f0f 100644
@@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
 
 	MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
 			mout_group5_5800_p, SRC_TOP7, 16, 2),
-	MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
+	MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
+	      CLK_SET_RATE_PARENT, 0),
 

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { · line 628
Quoted 3 lines
drivers/clk/samsung/clk-exynos5420.c +0 -0
 	MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
 };
Looks good to me.
Acked-by Chanwoo Choi <[email protected]>

Thanks for your review, patch applied to the clk/samsung tree.

Signature · 2 lines

Regards,
Sylwester