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clk:aspeed: Fix reset bits for PCI/VGA and PECI

PATCH New Jae Hyun Yoo 2 participants 3 messages Apr 24, 2018 – Apr 26, 2018

Subsystems (3)
Device tree bindings Common clk Arm/Aspeed machine support
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Jae Hyun Yoo

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#0 lore raw

PATCH 1/1 clk:aspeed: Fix reset bits for PCI/VGA and PECI

This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset logic is missing so added bit 10 as its reset bit.

Signed-off-by Jae Hyun Yoo <[email protected]>
---
 drivers/clk/clk-aspeed.c                 | 4 ++--
 include/dt-bindings/clock/aspeed-clock.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/clk-aspeed.c +2 -2
index de8e1db..71404a2 100644
@@ -100,7 +100,7 @@ static const struct aspeed_gate_data aspeed_gates[] = {
 	[ASPEED_CLK_GATE_GCLK] =	{  1,  7, "gclk-gate",		NULL,	0 }, /* 2D engine */
 	[ASPEED_CLK_GATE_MCLK] =	{  2, -1, "mclk-gate",		"mpll",	CLK_IS_CRITICAL }, /* SDRAM */
 	[ASPEED_CLK_GATE_VCLK] =	{  3,  6, "vclk-gate",		NULL,	0 }, /* Video Capture */
-	[ASPEED_CLK_GATE_BCLK] =	{  4, 10, "bclk-gate",		"bclk",	CLK_IS_CRITICAL }, /* PCIe/PCI */
+	[ASPEED_CLK_GATE_BCLK] =	{  4,  8, "bclk-gate",		"bclk",	CLK_IS_CRITICAL }, /* PCIe/PCI */
 	[ASPEED_CLK_GATE_DCLK] =	{  5, -1, "dclk-gate",		NULL,	CLK_IS_CRITICAL }, /* DAC */
 	[ASPEED_CLK_GATE_REFCLK] =	{  6, -1, "refclk-gate",	"clkin", CLK_IS_CRITICAL },
 	[ASPEED_CLK_GATE_USBPORT2CLK] =	{  7,  3, "usb-port2-gate",	NULL,	0 }, /* USB2.0 Host port 2 */

@@ -315,8 +315,8 @@ static const u8 aspeed_resets[] = {
 	[ASPEED_RESET_ADC]	= 23,
 	[ASPEED_RESET_JTAG_MASTER] = 22,
 	[ASPEED_RESET_MIC]	= 18,
+	[ASPEED_RESET_PECI]	= 10,
 	[ASPEED_RESET_PWM]	=  9,
-	[ASPEED_RESET_PCIVGA]	=  8,
 	[ASPEED_RESET_I2C]	=  2,
 	[ASPEED_RESET_AHB]	=  1,
include/dt-bindings/clock/aspeed-clock.h +2 -2
index e983d17..379f727 100644
@@ -43,8 +43,8 @@
 #define ASPEED_RESET_ADC		2
 #define ASPEED_RESET_JTAG_MASTER	3
 #define ASPEED_RESET_MIC		4
-#define ASPEED_RESET_PWM		5
-#define ASPEED_RESET_PCIVGA		6
+#define ASPEED_RESET_PECI		5
+#define ASPEED_RESET_PWM		6
 #define ASPEED_RESET_I2C		7
 #define ASPEED_RESET_AHB		8
 #define ASPEED_RESET_CRT1		9
Signature · 1 line
2.7.4
maintainer
#1 lore raw

PATCH 1/1 clk:aspeed: Fix reset bits for PCI/VGA and PECI

Hello Jae,

Quoted 5 lines · Jae Hyun Yoo

This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset logic is missing so added bit 10 as its reset bit.

Great find!

Can you please send these upstream as a fix? Apply to 4.17-rc2, and use get_maintainers.pl to identify the lists to send it to.

Also add:

Fixes 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc stable <[email protected]>

include/dt-bindings/clock/aspeed-clock.h line 47

Quoted 9 lines

+++ b/include/dt-bindings/clock/aspeed-clock.h

include/dt-bindings/clock/aspeed-clock.h +2 -2
@@ -43,8 +43,8 @@
 #define ASPEED_RESET_ADC               2
 #define ASPEED_RESET_JTAG_MASTER       3
 #define ASPEED_RESET_MIC               4
-#define ASPEED_RESET_PWM               5
-#define ASPEED_RESET_PCIVGA            6
+#define ASPEED_RESET_PECI              5
+#define ASPEED_RESET_PWM               6

This numbers form the kernel ABI, so we shouldn't be changing them. However, none of the mainline device trees use PCIVGA, so we can rename that without breaking any one.

If we leave PWM as 5, and rename PCIVGA to PECI, we won't break any existing device trees.

Cheers,

Joel

Quoted 6 lines
include/dt-bindings/clock/aspeed-clock.h +0 -1
 #define ASPEED_RESET_I2C               7
 #define ASPEED_RESET_AHB               8
 #define ASPEED_RESET_CRT1              9
--

2.7.4

author
#2 lore raw

PATCH 1/1 clk:aspeed: Fix reset bits for PCI/VGA and PECI

Hello Joel,

Quoted 11 lines · Joel Stanley

Hello Jae,

Quoted 5 lines · Jae Hyun Yoo

This commit fixes incorrect setting of reset bits for PCI/VGA and PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset logic is missing so added bit 10 as its reset bit.

Great find!

Quoted 8 lines

Can you please send these upstream as a fix? Apply to 4.17-rc2, and use get_maintainers.pl to identify the lists to send it to.

Also add:

Fixes 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc stable <[email protected]>

Thanks! I'll send it to upstream maintainers after adding the tags.

Quoted 14 lines

include/dt-bindings/clock/aspeed-clock.h line 47

Quoted 9 lines

+++ b/include/dt-bindings/clock/aspeed-clock.h

include/dt-bindings/clock/aspeed-clock.h +2 -2
@@ -43,8 +43,8 @@
  #define ASPEED_RESET_ADC               2
  #define ASPEED_RESET_JTAG_MASTER       3
  #define ASPEED_RESET_MIC               4
-#define ASPEED_RESET_PWM               5
-#define ASPEED_RESET_PCIVGA            6
+#define ASPEED_RESET_PECI              5
+#define ASPEED_RESET_PWM               6

This numbers form the kernel ABI, so we shouldn't be changing them. However, none of the mainline device trees use PCIVGA, so we can rename that without breaking any one.

Quoted 7 lines

If we leave PWM as 5, and rename PCIVGA to PECI, we won't break any existing device trees.

Cheers,

Joel

Got it. I'll rename the PCIVGA to PECI with Keeping the PWM.

Thanks,

Jae

Quoted 7 lines
Quoted 7 lines
include/dt-bindings/clock/aspeed-clock.h +0 -1
  #define ASPEED_RESET_I2C               7
  #define ASPEED_RESET_AHB               8
  #define ASPEED_RESET_CRT1              9
--

2.7.4