irqchip: augment Gemini bindings to reflect Faraday origin
Subsystems (4)
PATCH v2 1/4 irqchip: augment Gemini bindings to reflect Faraday origin
When we merged the Gemini interrupt controller it was not yet discovered that this IP block is actually a standard Faraday Technology interrupt controller.
As the IP block will probably appear in other designs as well, let's augment the DT bindings to reflect that it is first and foremost a standard Faraday part with a function name (FTINTC010) so that people reusing the IP easily find the driver they need.
Sorry for the mistakes due to lack of information.
---
ChangeLog v1->v2:
- No changes, just resending with the rest.
---
...,gemini-interrupt-controller.txt => faraday,ftintc010.txt} | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/interrupt-controller/{cortina,gemini-interrupt-controller.txt => faraday,ftintc010.txt} (63%)Documentation/devicetree/bindings/interrupt-controller/faraday,ftintc010.txt renamed from Documentation/devicetree/bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt +7 -4
@@ -1,9 +1,12 @@ -* Cortina Systems Gemini interrupt controller +* Faraday Technologt FTINTC010 interrupt controller -This interrupt controller is found on the Gemini SoCs. +This interrupt controller is a stock IP block from Faraday Technology found +in the Gemini SoCs and other designs. Required properties: -- compatible: must be "cortina,gemini-interrupt-controller" +- compatible: must be one of + "faraday,ftintc010" + "cortina,gemini-interrupt-controller" (deprecated) - reg: The register bank for the interrupt controller. - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: The number of cells to define the interrupts.
@@ -15,7 +18,7 @@ Required properties: Example: interrupt-controller at 48000000 { - compatible = "cortina,gemini-interrupt-controller"; + compatible = "faraday,ftintc010" reg = <0x48000000 0x1000>; interrupt-controller; #interrupt-cells = <2>;
Signature · 1 line
2.9.3
PATCH v2 2/4 irqchip: refactor Gemini driver to reflect Faraday origin
The Gemini irqchip turns out to be a standard IP component from Faraday Technology named FTINTC010 after some research and new information.
- Rename the driver and all symbols to reflect the new information.
- Add the new compatible string "faraday,ftintc010"
- Create a Kconfig symbol CONFIG_FARADAY_FTINTC010 so that SoCs using this interrupt controller can easily select and reuse it instead of hardwiring it to ARCH_GEMINI
I have created a separate patch to select the new Kconfig symbol from the Gemini machine, which will be merged through the ARM SoC tree.
---
ChangeLog v1->v2:
- Fix Paulius email address.
--- drivers/irqchip/Kconfig | 6 ++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-ftintc010.c | 187 ++++++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gemini.c | 185 --------------------------------------- 4 files changed, 194 insertions(+), 186 deletions(-) create mode 100644 drivers/irqchip/irq-ftintc010.c delete mode 100644 drivers/irqchip/irq-gemini.c
drivers/irqchip/Kconfig +6 -0
@@ -115,6 +115,12 @@ config DW_APB_ICTL select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config FARADAY_FTINTC010 + bool + select IRQ_DOMAIN + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + config HISILICON_IRQ_MBIGEN bool select ARM_GIC_V3
drivers/irqchip/Makefile +1 -1
@@ -6,7 +6,7 @@ obj-$(CONFIG_ATH79) += irq-ath79-misc.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o -obj-$(CONFIG_ARCH_GEMINI) += irq-gemini.o +obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
drivers/irqchip/irq-ftintc010.c new file +187 -0
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drivers/irqchip/irq-gemini.c deleted +0 -185
185 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH v2 3/4 irqchip: faraday: fix the trigger types
In reply to Linus WalleijThe triggers in the driver were right for high level triggered IRQs but the edge detection on edge triggered IRQs was wrong. After studying a proper driver from Po-Yu Chuang I now know how to handle these right, and we can properly implement low level IRQs as well.
The device trees for the Gemini had polarity switched around so these have been fixed to conform to the right polarity as well.
---
ChangeLog v1->v2:
- No changes, just resending with the rest.
--- drivers/irqchip/irq-ftintc010.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
drivers/irqchip/irq-ftintc010.c +10 -5
@@ -26,7 +26,9 @@#define FT010_IRQ_SOURCE (base_addr) (base_addr + 0x00)#define FT010_IRQ_MASK (base_addr) (base_addr + 0x04)#define FT010_IRQ_CLEAR (base_addr) (base_addr + 0x08) +/* Selects level- or edge-triggered */ #define FT010_IRQ_MODE (base_addr) (base_addr + 0x0C) +/* Selects active low/high or falling/rising edge */ #define FT010_IRQ_POLARITY (base_addr) (base_addr + 0x10)#define FT010_IRQ_STATUS (base_addr) (base_addr + 0x14)#define FT010_FIQ_SOURCE (base_addr) (base_addr + 0x20)
@@ -84,22 +86,25 @@ static int ft010_irq_set_type(struct irq_data *d, unsigned int trigger) mode =readl (FT010_IRQ_MODE (f->base)); polarity =readl (FT010_IRQ_POLARITY (f->base)); -if (trigger & (IRQ_TYPE_LEVEL_HIGH )) { +if (trigger & (IRQ_TYPE_LEVEL_LOW )) { +irq_set_handler_locked (d, handle_level_irq); + mode &= ~BIT (offset); + polarity |=BIT (offset); + }else if (trigger & (IRQ_TYPE_LEVEL_HIGH )) {irq_set_handler_locked (d, handle_level_irq); -/* Disable edge detection */ mode &= ~BIT (offset); polarity &= ~BIT (offset); - }else if (trigger &IRQ_TYPE_EDGE_RISING ) { + }else if (trigger &IRQ_TYPE_EDGE_FALLING ) {irq_set_handler_locked (d, handle_edge_irq); mode |=BIT (offset); polarity |=BIT (offset); - }else if (trigger &IRQ_TYPE_EDGE_FALLING ) { + }else if (trigger &IRQ_TYPE_EDGE_RISING ) {irq_set_handler_locked (d, handle_edge_irq); mode |=BIT (offset); polarity &= ~BIT (offset); }else {irq_set_handler_locked (d, handle_bad_irq); -pr_warn ("GEMINI IRQ: no supported trigger selected for line %d\n" , +pr_warn ("Faraday IRQ: no supported trigger selected for line %d\n" , offset); }
Signature · 1 line
2.9.3
PATCH v2 4/4 irqchip: replace moxa with ftintc010
In reply to Linus WalleijThe Moxa Art interrupt controller is very very likely just an instance of the Faraday FTINTC010 interrupt controller from Faraday Technology. An indication would be its close association with the FA526 ARM core and the fact that the register layout is the same.
The implementation in irq-moxart.c can probably be right off replaced with the irq-ftintc010.c driver by adding a compatible string, selecting this irqchip from the machine and run.
As a bonus we have an irqchip driver supporting high/low and rising/falling edges for the Moxa Art, and shared code with the Gemini platform.
---
ChangeLog v1->v2:
- No longer a RFT patch, Jonas has successfully tested this on the Moxart board.
- Add Olof's ACK so it can be applied to the irqchip tree.
--- arch/arm/mach-moxart/Kconfig | 2 +- drivers/irqchip/Makefile | 1 - drivers/irqchip/irq-ftintc010.c | 2 + drivers/irqchip/irq-moxart.c | 116 ---------------------------------------- 4 files changed, 3 insertions(+), 118 deletions(-) delete mode 100644 drivers/irqchip/irq-moxart.c
arch/arm/mach-moxart/Kconfig +1 -1
@@ -3,8 +3,8 @@ menuconfig ARCH_MOXART depends on ARCH_MULTI_V4 select CPU_FA526 select ARM_DMA_MEM_BUFFERABLE + select FARADAY_FTINTC010 select MOXART_TIMER - select GENERIC_IRQ_CHIP select GPIOLIB select PHYLIB if NETDEVICES help
drivers/irqchip/Makefile +0 -1
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o -obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
drivers/irqchip/irq-ftintc010.c +2 -0
@@ -190,3 +190,5 @@ IRQCHIP_DECLARE(faraday, "faraday,ftintc010", ft010_of_init_irq);IRQCHIP_DECLARE (gemini,"cortina,gemini-interrupt-controller" , ft010_of_init_irq); +IRQCHIP_DECLARE (moxa,"moxa,moxart-ic" , + ft010_of_init_irq);
drivers/irqchip/irq-moxart.c deleted +0 -116
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Signature · 1 line
2.9.3
PATCH v2 1/4 irqchip: augment Gemini bindings to reflect Faraday origin
In reply to Linus WalleijHi Linus
Quoted 9 lines · Linus Walleij
When we merged the Gemini interrupt controller it was not yet discovered that this IP block is actually a standard Faraday Technology interrupt controller.
As the IP block will probably appear in other designs as well, let's augment the DT bindings to reflect that it is first and foremost a standard Faraday part with a function name (FTINTC010) so that people reusing the IP easily find the driver they need.
Quoted 5 lines
Sorry for the mistakes due to lack of information.
Cc Greentime Hu <[email protected]>Signed-off-by Linus Walleij <[email protected]>---
You can add my
on the whole series, if you want.
Greetings form Cologne
Hans Ulli Kroll
PATCH v2 1/4 irqchip: augment Gemini bindings to reflect Faraday origin
In reply to Linus WalleijQuoted 9 lines · Linus Walleij
When we merged the Gemini interrupt controller it was not yet discovered that this IP block is actually a standard Faraday Technology interrupt controller.
As the IP block will probably appear in other designs as well, let's augment the DT bindings to reflect that it is first and foremost a standard Faraday part with a function name (FTINTC010) so that people reusing the IP easily find the driver they need.
Quoted 7 lines
Sorry for the mistakes due to lack of information.
Cc Greentime Hu <[email protected]>Signed-off-by Linus Walleij <[email protected]>---
ChangeLogv1->v2:
- No changes, just resending with the rest.
I've queued the series for 4.12.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...