Skip to contentSkip to conversation

MediaTek PLL Refactors and Fixes

PATCH RESEND Applied Nicolas Frattaroli 4 participants 15 messages Dec 15, 2025 – Jan 28

Subsystems (3)
Arm MediaTek Common clk MediaTek MT6735 clock & reset drivers
lore
Share & tools
lore

Nicolas Frattaroli

author
#0 lore raw

v3 cover MediaTek PLL Refactors and Fixes

This series refactors all users of mtk-pll, just so we can enable runtime power management for the clock controllers that want it. It's also generally more useful to have the struct device in the pll code, rather than the device node.

Also fix up MT8196 mfgpll to declare its parent-child relationship with mfg_eb, and fix the common clock framework core to take CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.

The reason why this is all in the same series is that it grew out of me first modelling this as an RPM clock for mfgpll, which Angelo disagreed with, so I did some investigation and it seems MFG_EB indeed is a parent clock. However, the earlier refactoring to pass the device pointer down is still useful.

Signed-off-by Nicolas Frattaroli <[email protected]>

---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks

 drivers/clk/clk.c                            | 13 +++++++++++++
 drivers/clk/mediatek/clk-mt2701.c            |  2 +-
 drivers/clk/mediatek/clk-mt2712-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt6735-apmixedsys.c |  4 ++--
 drivers/clk/mediatek/clk-mt6765.c            |  2 +-
 drivers/clk/mediatek/clk-mt6779.c            |  2 +-
 drivers/clk/mediatek/clk-mt6795-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt6797.c            |  2 +-
 drivers/clk/mediatek/clk-mt7622-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt7629.c            |  2 +-
 drivers/clk/mediatek/clk-mt7981-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt7986-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt7988-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt8135-apmixedsys.c |  3 ++-
 drivers/clk/mediatek/clk-mt8167-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
 drivers/clk/mediatek/clk-mt8183-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8186-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8188-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8192-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8195-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8195-apusys_pll.c |  3 ++-
 drivers/clk/mediatek/clk-mt8196-apmixedsys.c |  3 ++-
 drivers/clk/mediatek/clk-mt8196-mcu.c        |  2 +-
 drivers/clk/mediatek/clk-mt8196-mfg.c        | 15 ++++++++-------
 drivers/clk/mediatek/clk-mt8196-vlpckgen.c   |  2 +-
 drivers/clk/mediatek/clk-mt8365-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8516-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-pll.c               | 19 +++++++++++++------
 drivers/clk/mediatek/clk-pll.h               | 15 ++++++++-------
 drivers/clk/mediatek/clk-pllfh.c             | 13 ++++++++-----
 drivers/clk/mediatek/clk-pllfh.h             |  2 +-
 32 files changed, 87 insertions(+), 59 deletions(-)

---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016

Best regards,

Signature · 1 line
Nicolas Frattaroli <[email protected]>
author
#1 lore raw

PATCH RESEND v3 1/5 clk: Respect CLK_OPS_PARENT_ENABLE during recalc

When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency.

Add parent enables/disables where the recalc_rate op is called directly.

Fixes fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>
---
 drivers/clk/clk.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
drivers/clk/clk.c +13 -0
index 85d2f2481acf..1b0f9d567f48 100644
@@ -1921,7 +1921,14 @@ static unsigned long clk_recalc(struct clk_core *core,
 	unsigned long rate = parent_rate;
 
 	if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
+		if (core->flags & CLK_OPS_PARENT_ENABLE)
+			clk_core_prepare_enable(core->parent);
+
 		rate = core->ops->recalc_rate(core->hw, parent_rate);
+
+		if (core->flags & CLK_OPS_PARENT_ENABLE)
+			clk_core_disable_unprepare(core->parent);
+
 		clk_pm_runtime_put(core);
 	}
 	return rate;

@@ -4031,6 +4038,9 @@ static int __clk_core_init(struct clk_core *core)
 	 */
 	clk_core_update_duty_cycle_nolock(core);
 
+	if (core->flags & CLK_OPS_PARENT_ENABLE)
+		clk_core_prepare_enable(core->parent);
+
 	/*
 	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For
 	 * simple clocks and lazy developers the default fallback is to use the

@@ -4046,6 +4056,9 @@ static int __clk_core_init(struct clk_core *core)
 		rate = 0;
 	core->rate = core->req_rate = rate;
 
+	if (core->flags & CLK_OPS_PARENT_ENABLE)
+		clk_core_disable_unprepare(core->parent);
+
 	/*
 	 * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
 	 * don't get accidentally disabled when walking the orphan tree and
Signature · 1 line
2.52.0
maintainer Applied
#2 lore raw

Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

Quoting Nicolas Frattaroli (2025-12-15 03:23:58)

Quoted 5 lines

When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency.

Quoted 8 lines

Add parent enables/disables where the recalc_rate op is called directly.

Fixes fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

#3 lore raw

Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

Hello,

Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd:

Quoted 8 lines

Quoting Nicolas Frattaroli (2025-12-15 03:23:58)

Quoted 7 lines

When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency.

Add parent enables/disables where the recalc_rate op is called directly.

Quoted 8 lines
Quoted 6 lines
Fixes fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126. Last lines on bootlog (earlycon is necessary)

Quoted 6 lines
[    1.175639] Initialise system trusted keyrings
[    1.178907] workingset: timestamp_bits=42 max_order=19 bucket_order=0
[    1.185822] NFS: Registering the id_resolver key type
[    1.190295] Key type id_resolver registered
[    1.194473] Key type id_legacy registered
[    1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
Quoted 8 lines
[    1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver
Registering... [    1.213235] cryptd: max_cpu_qlen set to 1000
[    1.274689] Key type asymmetric registered
[    1.275939] Asymmetric key parser 'x509' registered
[    1.280896] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 242) [    1.288278] io scheduler mq-deadline registered
[    1.292840] io scheduler kyber registered
[    1.299245] ledtrig-cpu: registered to indicate activity on CPUs

Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the problem.

Best regards,
Alexander

Signature · 4 lines
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
author
#4 lore raw

Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

Quoted 37 lines · On Tuesday, 27 January 2026 15:55:29 Central European Standard Time Alexander…

Hello,

Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd:

Quoted 8 lines

Quoting Nicolas Frattaroli (2025-12-15 03:23:58)

Quoted 7 lines

When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency.

Add parent enables/disables where the recalc_rate op is called directly.

Quoted 8 lines
Quoted 6 lines
Fixes fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126. Last lines on bootlog (earlycon is necessary)

Quoted 6 lines
[    1.175639] Initialise system trusted keyrings
[    1.178907] workingset: timestamp_bits=42 max_order=19 bucket_order=0
[    1.185822] NFS: Registering the id_resolver key type
[    1.190295] Key type id_resolver registered
[    1.194473] Key type id_legacy registered
[    1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
Quoted 8 lines
[    1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver
Registering... [    1.213235] cryptd: max_cpu_qlen set to 1000
[    1.274689] Key type asymmetric registered
[    1.275939] Asymmetric key parser 'x509' registered
[    1.280896] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 242) [    1.288278] io scheduler mq-deadline registered
[    1.292840] io scheduler kyber registered
[    1.299245] ledtrig-cpu: registered to indicate activity on CPUs
Quoted 1 line

Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the problem.

Hi Alexander,

sorry for breaking -next.

Can you try the following patch to print which clock+parent is causing the hang on your platform?

---

drivers/clk/clk.c +20 -4
index 1b0f9d567f48..fa1443517768 100644
@@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *core,
 	unsigned long rate = parent_rate;
 
 	if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
-		if (core->flags & CLK_OPS_PARENT_ENABLE)
+		if (core->flags & CLK_OPS_PARENT_ENABLE) {
+			pr_info("%s: enabling parent %s for %s\n", __func__,
+				core->parent ? core->parent->name : "(null)",
+				core->name);
 			clk_core_prepare_enable(core->parent);
+		}
 
 		rate = core->ops->recalc_rate(core->hw, parent_rate);
 
-		if (core->flags & CLK_OPS_PARENT_ENABLE)
+		if (core->flags & CLK_OPS_PARENT_ENABLE) {
+			pr_info("%s: disabling parent %s for %s\n", __func__,
+				core->parent ? core->parent->name : "(null)",
+				core->name);
 			clk_core_disable_unprepare(core->parent);
+		}
 
 		clk_pm_runtime_put(core);
 	}

@@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core)
 	 */
 	clk_core_update_duty_cycle_nolock(core);
 
-	if (core->flags & CLK_OPS_PARENT_ENABLE)
+	if (core->flags & CLK_OPS_PARENT_ENABLE) {
+		pr_info("%s: enabling parent %s for %s\n", __func__,
+			core->parent ? core->parent->name : "(null)",
+			core->name);
 		clk_core_prepare_enable(core->parent);
+	}
 
 	/*
 	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For

@@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core)
 		rate = 0;
 	core->rate = core->req_rate = rate;
 
-	if (core->flags & CLK_OPS_PARENT_ENABLE)
+	if (core->flags & CLK_OPS_PARENT_ENABLE) {
+		pr_info("%s: disabling parent %s for %s\n", __func__,
+			core->parent ? core->parent->name : "(null)",
+			core->name);
 		clk_core_disable_unprepare(core->parent);
+	}
 
 	/*
 	 * Enable CLK_IS_CRITICAL clocks so newly added critical clocks

---

Thanks for reporting this.

Kind regards,
Nicolas Frattaroli

Quoted 4 lines

Best regards,
Alexander

#5 lore raw

Re: [PATCH RESEND v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc

Hi Nicolas,

Am Mittwoch, 28. Januar 2026, 15:11:33 CET schrieb Nicolas Frattaroli:

Quoted 106 lines · On Tuesday, 27 January 2026 15:55:29 Central European Standard Time Alexander…
Quoted 37 lines

Hello,

Am Freitag, 23. Januar 2026, 02:45:33 CET schrieb Stephen Boyd:

Quoted 8 lines

Quoting Nicolas Frattaroli (2025-12-15 03:23:58)

Quoted 7 lines

When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock operations, such as setting the rate or switching parents. However, another operation that can and often does touch actual hardware state is recalc_rate, which may also be affected by such a dependency.

Add parent enables/disables where the recalc_rate op is called directly.

Quoted 8 lines
Quoted 6 lines
Fixes fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

Unfortunately this breaks my board TQMa8MPxL+MBa8MPxL on next-20260126. Last lines on bootlog (earlycon is necessary)

Quoted 6 lines
[    1.175639] Initialise system trusted keyrings
[    1.178907] workingset: timestamp_bits=42 max_order=19 bucket_order=0
[    1.185822] NFS: Registering the id_resolver key type
[    1.190295] Key type id_resolver registered
[    1.194473] Key type id_legacy registered
[    1.198515] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
Quoted 8 lines
[    1.205235] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver
Registering... [    1.213235] cryptd: max_cpu_qlen set to 1000
[    1.274689] Key type asymmetric registered
[    1.275939] Asymmetric key parser 'x509' registered
[    1.280896] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 242) [    1.288278] io scheduler mq-deadline registered
[    1.292840] io scheduler kyber registered
[    1.299245] ledtrig-cpu: registered to indicate activity on CPUs
Quoted 1 line

Reverting commit 669917676e93fca5ea3c66fc9539830312bec58e fixes the problem.

Hi Alexander,

sorry for breaking -next.

Can you try the following patch to print which clock+parent is causing the hang on your platform?

---

drivers/clk/clk.c +20 -5
index 1b0f9d567f48..fa1443517768 100644
@@ -1921,13 +1921,21 @@ static unsigned long clk_recalc(struct clk_core *core,
 	unsigned long rate = parent_rate;
 
 	if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
-		if (core->flags & CLK_OPS_PARENT_ENABLE)
+		if (core->flags & CLK_OPS_PARENT_ENABLE) {
+			pr_info("%s: enabling parent %s for %s\n", __func__,
+				core->parent ? core->parent->name : "(null)",
+				core->name);
 			clk_core_prepare_enable(core->parent);
+		}
 
 		rate = core->ops->recalc_rate(core->hw, parent_rate);
 
-		if (core->flags & CLK_OPS_PARENT_ENABLE)
+		if (core->flags & CLK_OPS_PARENT_ENABLE) {
+			pr_info("%s: disabling parent %s for %s\n", __func__,
+				core->parent ? core->parent->name : "(null)",
+				core->name);
 			clk_core_disable_unprepare(core->parent);
+		}
 
 		clk_pm_runtime_put(core);
 	}

@@ -4038,8 +4046,12 @@ static int __clk_core_init(struct clk_core *core)
 	 */
 	clk_core_update_duty_cycle_nolock(core);
 
-	if (core->flags & CLK_OPS_PARENT_ENABLE)
+	if (core->flags & CLK_OPS_PARENT_ENABLE) {
+		pr_info("%s: enabling parent %s for %s\n", __func__,
+			core->parent ? core->parent->name : "(null)",
+			core->name);
 		clk_core_prepare_enable(core->parent);
+	}
 
 	/*
 	 * Set clk's rate.  The preferred method is to use .recalc_rate.  For

@@ -4056,8 +4068,12 @@ static int __clk_core_init(struct clk_core *core)
 		rate = 0;
 	core->rate = core->req_rate = rate;
 
-	if (core->flags & CLK_OPS_PARENT_ENABLE)
+	if (core->flags & CLK_OPS_PARENT_ENABLE) {
+		pr_info("%s: disabling parent %s for %s\n", __func__,
+			core->parent ? core->parent->name : "(null)",
+			core->name);
 		clk_core_disable_unprepare(core->parent);
+	}
 
 	/*
 	 * Enable CLK_IS_CRITICAL clocks so newly added critical clocks
---
Quoted 1 line

Thanks for reporting this.

thanks for the debugging patch. I'll respond to the other thread where Mark is active as well.

Best regards,
Alexander

Quoted 13 lines

Kind regards,
Nicolas Frattaroli

Quoted 4 lines

Best regards,
Alexander

Signature · 4 lines
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/
author
#6 lore raw

PATCH RESEND v3 2/5 clk: mediatek: Refactor pll registration to pass device

In reply to Nicolas Frattaroli

As it stands, mtk_clk_register_plls takes a struct device_node pointer as its first argument. This is a tragic happenstance, as it's trivial to get the device_node from a struct device, but the opposite not so much. The struct device is a much more useful thing to have passed down.

Refactor mtk_clk_register_plls to take a struct device pointer instead of a struct device_node pointer, and fix up all users of this function.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>
---
 drivers/clk/mediatek/clk-mt2701.c            |  2 +-
 drivers/clk/mediatek/clk-mt2712-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt6735-apmixedsys.c |  4 ++--
 drivers/clk/mediatek/clk-mt6765.c            |  2 +-
 drivers/clk/mediatek/clk-mt6779.c            |  2 +-
 drivers/clk/mediatek/clk-mt6797.c            |  2 +-
 drivers/clk/mediatek/clk-mt7622-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt7629.c            |  2 +-
 drivers/clk/mediatek/clk-mt7981-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt7986-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt7988-apmixed.c    |  2 +-
 drivers/clk/mediatek/clk-mt8135-apmixedsys.c |  3 ++-
 drivers/clk/mediatek/clk-mt8167-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8183-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8188-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8195-apusys_pll.c |  3 ++-
 drivers/clk/mediatek/clk-mt8196-apmixedsys.c |  3 ++-
 drivers/clk/mediatek/clk-mt8196-mcu.c        |  2 +-
 drivers/clk/mediatek/clk-mt8196-mfg.c        |  2 +-
 drivers/clk/mediatek/clk-mt8196-vlpckgen.c   |  2 +-
 drivers/clk/mediatek/clk-mt8365-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8516-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-pll.c               |  7 ++++---
 drivers/clk/mediatek/clk-pll.h               | 10 ++++------
 24 files changed, 34 insertions(+), 32 deletions(-)
drivers/clk/mediatek/clk-mt2701.c +1 -1
index 1e88ad8b93f4..d9f40fda73d1 100644
@@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
+	mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
 								clk_data);
 	mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
 								clk_data);
drivers/clk/mediatek/clk-mt2712-apmixedsys.c +1 -1
index a60622d251ff..54b18e9f83f8 100644
@@ -119,7 +119,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (r)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt6735-apmixedsys.c +2 -2
index e0949911e8f7..9e30c089a209 100644
@@ -93,8 +93,8 @@ static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	platform_set_drvdata(pdev, clk_data);
 
-	ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
-				   ARRAY_SIZE(apmixedsys_plls), clk_data);
+	ret = mtk_clk_register_plls(&pdev->dev, apmixedsys_plls,
+				    ARRAY_SIZE(apmixedsys_plls), clk_data);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
 		return ret;
drivers/clk/mediatek/clk-mt6765.c +1 -1
index d53731e7933f..60f6f9fa7dcf 100644
@@ -740,7 +740,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 
 	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 			       ARRAY_SIZE(apmixed_clks), clk_data);
drivers/clk/mediatek/clk-mt6779.c +1 -1
index 86732f5acf93..4b9dcb910b03 100644
@@ -1220,7 +1220,7 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 
 	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
 			       ARRAY_SIZE(apmixed_clks), clk_data);
drivers/clk/mediatek/clk-mt6797.c +1 -1
index fb59e71af58e..ebf850ac57f5 100644
@@ -655,7 +655,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 
 	return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 }
drivers/clk/mediatek/clk-mt7622-apmixedsys.c +1 -1
index 2350592d9a93..8a29eaab0cfc 100644
@@ -96,7 +96,7 @@ static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (ret)
 		return ret;
drivers/clk/mediatek/clk-mt7629.c +1 -1
index baf94e7bea37..e154771b1b8b 100644
@@ -634,7 +634,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
 			      clk_data);
 
 	mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
drivers/clk/mediatek/clk-mt7981-apmixed.c +1 -1
index e8211eb4e09e..6606b54fb376 100644
@@ -76,7 +76,7 @@ static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 
 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 	if (r) {
drivers/clk/mediatek/clk-mt7986-apmixed.c +1 -1
index 93751abe6be8..1c79418d08a7 100644
@@ -74,7 +74,7 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 
 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
 	if (r) {
drivers/clk/mediatek/clk-mt7988-apmixed.c +1 -1
index 63d33a78cb48..416a4b88d100 100644
@@ -86,7 +86,7 @@ static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (r)
 		goto free_apmixed_data;
drivers/clk/mediatek/clk-mt8135-apmixedsys.c +2 -1
index bdadc35c64cb..19e4ee489ec3 100644
@@ -57,7 +57,8 @@ static int clk_mt8135_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
+				    clk_data);
 	if (ret)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt8167-apmixedsys.c +1 -1
index adf576786696..fb6c21bbeef8 100644
@@ -105,7 +105,7 @@ static int clk_mt8167_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (ret)
 		return ret;
drivers/clk/mediatek/clk-mt8183-apmixedsys.c +1 -1
index 551adbfd7ac9..6242d4f5376e 100644
@@ -155,7 +155,7 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (ret)
 		return ret;
drivers/clk/mediatek/clk-mt8188-apmixedsys.c +1 -1
index 21d7a9a2ab1a..a1de596bff99 100644
@@ -106,7 +106,7 @@ static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (r)
 		goto free_apmixed_data;
drivers/clk/mediatek/clk-mt8195-apusys_pll.c +2 -1
index 8b45a3fad02f..a2d98ed58e34 100644
@@ -66,7 +66,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, apusys_plls,
+				  ARRAY_SIZE(apusys_plls), clk_data);
 	if (r)
 		goto free_apusys_pll_data;
drivers/clk/mediatek/clk-mt8196-apmixedsys.c +2 -1
index 617f5449b88b..c4ebb0170b82 100644
@@ -152,7 +152,8 @@ static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks,
+				  clk_data);
 	if (r)
 		goto free_apmixed_data;
drivers/clk/mediatek/clk-mt8196-mcu.c +1 -1
index 5cbcc411ae73..13642fc673c2 100644
@@ -122,7 +122,7 @@ static int clk_mt8196_mcu_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
 	if (r)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt8196-mfg.c +1 -1
index ae1eb9de79ae..8e09c0f7b754 100644
@@ -105,7 +105,7 @@ static int clk_mt8196_mfg_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
+	r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
 	if (r)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt8196-vlpckgen.c +1 -1
index d59a8a9d9855..7dcc164627c5 100644
@@ -664,7 +664,7 @@ static int clk_mt8196_vlp_probe(struct platform_device *pdev)
 	if (r)
 		goto unregister_factors;
 
-	r = mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls),
+	r = mtk_clk_register_plls(dev, vlp_plls, ARRAY_SIZE(vlp_plls),
 				  clk_data);
 	if (r)
 		goto unregister_muxes;
drivers/clk/mediatek/clk-mt8365-apmixedsys.c +1 -1
index f41b991a0178..e331aa28a4bd 100644
@@ -133,7 +133,7 @@ static int clk_mt8365_apmixed_probe(struct platform_device *pdev)
 		return PTR_ERR(hw);
 	clk_data->hws[CLK_APMIXED_USB20_EN] = hw;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (ret)
 		return ret;
drivers/clk/mediatek/clk-mt8516-apmixedsys.c +1 -1
index edd9174d2f2f..2a6206cae2f0 100644
@@ -87,7 +87,7 @@ static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
 	if (!clk_data)
 		return -ENOMEM;
 
-	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
+	ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
 	if (ret)
 		return ret;
drivers/clk/mediatek/clk-pll.c +4 -3
index cd2b6ce551c6..5caf91ae9ddb 100644
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of_address.h>
+#include <linux/platform_device.h>
 #include <linux/slab.h>
 
 #include "clk-pll.h"

@@ -404,7 +405,7 @@ void mtk_clk_unregister_pll(struct clk_hw *hw)
 	kfree(pll);
 }
 
-int mtk_clk_register_plls(struct device_node *node,
+int mtk_clk_register_plls(struct device *dev,
 			  const struct mtk_pll_data *plls, int num_plls,
 			  struct clk_hw_onecell_data *clk_data)
 {

@@ -412,7 +413,7 @@ int mtk_clk_register_plls(struct device_node *node,
 	int i;
 	struct clk_hw *hw;
 
-	base = of_iomap(node, 0);
+	base = of_iomap(dev->of_node, 0);
 	if (!base) {
 		pr_err("%s(): ioremap failed\n", __func__);
 		return -EINVAL;

@@ -423,7 +424,7 @@ int mtk_clk_register_plls(struct device_node *node,
 
 		if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
 			pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
-				node, pll->id);
+				dev->of_node, pll->id);
 			continue;
 		}
drivers/clk/mediatek/clk-pll.h +4 -6
index d71c150ce83e..38fde1a273bf 100644
@@ -10,9 +10,7 @@
 #include <linux/clk-provider.h>
 #include <linux/types.h>
 
-struct clk_ops;
-struct clk_hw_onecell_data;
-struct device_node;
+struct device;
 
 struct mtk_pll_div_table {
 	u32 div;

@@ -78,9 +76,9 @@ struct mtk_clk_pll {
 	const struct mtk_pll_data *data;
 };
 
-int mtk_clk_register_plls(struct device_node *node,
-			  const struct mtk_pll_data *plls, int num_plls,
-			  struct clk_hw_onecell_data *clk_data);
+int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls,
+			  int num_plls, struct clk_hw_onecell_data *clk_data);
+
 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
 			     struct clk_hw_onecell_data *clk_data);
Signature · 1 line
2.52.0
maintainer Applied
#7 lore raw

Re: [PATCH RESEND v3 2/5] clk: mediatek: Refactor pll registration to pass device

Quoting Nicolas Frattaroli (2025-12-15 03:23:59)

Quoted 5 lines

As it stands, mtk_clk_register_plls takes a struct device_node pointer as its first argument. This is a tragic happenstance, as it's trivial to get the device_node from a struct device, but the opposite not so much. The struct device is a much more useful thing to have passed down.

Quoted 7 lines

Refactor mtk_clk_register_plls to take a struct device pointer instead of a struct device_node pointer, and fix up all users of this function.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Reviewed-by Chen-Yu Tsai <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

author
#8 lore raw

PATCH RESEND v3 3/5 clk: mediatek: Pass device to clk_hw_register for PLLs

In reply to Nicolas Frattaroli

Passing the struct device pointer to clk_hw_register allows for runtime power management to work for the registered clock controllers. However, the mediatek PLL clocks do not do this.

Change this by adding a struct device pointer argument to mtk_clk_register_pll, and fix up the only other user of it. Also add a new member to the struct mtk_clk_pll for the struct device pointer, which is set by mtk_clk_register_pll and is used by mtk_clk_register_pll_ops.

If mtk_clk_register_pll is called with a NULL struct device pointer, then everything still works as expected; the clock core will simply treat them as previously, i.e. without runtime power management.

Reviewed-by Chen-Yu Tsai <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>
---
 drivers/clk/mediatek/clk-pll.c   | 9 ++++++---
 drivers/clk/mediatek/clk-pll.h   | 4 +++-
 drivers/clk/mediatek/clk-pllfh.c | 2 +-
 3 files changed, 10 insertions(+), 5 deletions(-)
drivers/clk/mediatek/clk-pll.c +6 -3
index 5caf91ae9ddb..c4f9c06e5133 100644
@@ -366,7 +366,7 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
 		init.parent_names = &parent_name;
 	init.num_parents = 1;
 
-	ret = clk_hw_register(NULL, &pll->hw);
+	ret = clk_hw_register(pll->dev, &pll->hw);
 
 	if (ret)
 		return ERR_PTR(ret);

@@ -374,7 +374,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
 	return &pll->hw;
 }
 
-struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
+struct clk_hw *mtk_clk_register_pll(struct device *dev,
+				    const struct mtk_pll_data *data,
 				    void __iomem *base)
 {
 	struct mtk_clk_pll *pll;

@@ -385,6 +386,8 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
 	if (!pll)
 		return ERR_PTR(-ENOMEM);
 
+	pll->dev = dev;
+
 	hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
 	if (IS_ERR(hw))
 		kfree(pll);

@@ -428,7 +431,7 @@ int mtk_clk_register_plls(struct device *dev,
 			continue;
 		}
 
-		hw = mtk_clk_register_pll(pll, base);
+		hw = mtk_clk_register_pll(dev, pll, base);
 
 		if (IS_ERR(hw)) {
 			pr_err("Failed to register clk %s: %pe\n", pll->name,
drivers/clk/mediatek/clk-pll.h +3 -1
index 38fde1a273bf..f6493699c4e3 100644
@@ -61,6 +61,7 @@ struct mtk_pll_data {
  */
 
 struct mtk_clk_pll {
+	struct device *dev;
 	struct clk_hw	hw;
 	void __iomem	*base_addr;
 	void __iomem	*pd_addr;

@@ -108,7 +109,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
 					const struct mtk_pll_data *data,
 					void __iomem *base,
 					const struct clk_ops *pll_ops);
-struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
+struct clk_hw *mtk_clk_register_pll(struct device *dev,
+				    const struct mtk_pll_data *data,
 				    void __iomem *base);
 void mtk_clk_unregister_pll(struct clk_hw *hw);
drivers/clk/mediatek/clk-pllfh.c +1 -1
index 83630ee07ee9..62bfe4a480f1 100644
@@ -220,7 +220,7 @@ int mtk_clk_register_pllfhs(struct device_node *node,
 		if (use_fhctl)
 			hw = mtk_clk_register_pllfh(pll, pllfh, base);
 		else
-			hw = mtk_clk_register_pll(pll, base);
+			hw = mtk_clk_register_pll(NULL, pll, base);
 
 		if (IS_ERR(hw)) {
 			pr_err("Failed to register %s clk %s: %ld\n",
Signature · 1 line
2.52.0
maintainer Applied
#9 lore raw

Re: [PATCH RESEND v3 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs

Quoting Nicolas Frattaroli (2025-12-15 03:24:00)

Quoted 10 lines

Passing the struct device pointer to clk_hw_register allows for runtime power management to work for the registered clock controllers. However, the mediatek PLL clocks do not do this.

Change this by adding a struct device pointer argument to mtk_clk_register_pll, and fix up the only other user of it. Also add a new member to the struct mtk_clk_pll for the struct device pointer, which is set by mtk_clk_register_pll and is used by mtk_clk_register_pll_ops.

Quoted 8 lines

If mtk_clk_register_pll is called with a NULL struct device pointer, then everything still works as expected; the clock core will simply treat them as previously, i.e. without runtime power management.

Reviewed-by Chen-Yu Tsai <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

author
#10 lore raw

PATCH RESEND v3 4/5 clk: mediatek: Refactor pllfh registration to pass device

In reply to Nicolas Frattaroli

After refactoring all of PLL to pass the device, it's now fairly easy to refactor pllfh and its users, as pllfh registration wraps PLL registration.

Do this refactor and move all of the pllfh users to pass the device as well.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>
---
 drivers/clk/mediatek/clk-mt6795-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
 drivers/clk/mediatek/clk-mt8186-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8192-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-mt8195-apmixedsys.c |  2 +-
 drivers/clk/mediatek/clk-pllfh.c             | 13 ++++++++-----
 drivers/clk/mediatek/clk-pllfh.h             |  2 +-
 7 files changed, 20 insertions(+), 17 deletions(-)
drivers/clk/mediatek/clk-mt6795-apmixedsys.c +1 -1
index 91665d7f125e..123d5d7fea85 100644
@@ -152,7 +152,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-	ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+	ret = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls),
 				      pllfhs, ARRAY_SIZE(pllfhs), clk_data);
 	if (ret)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt8173-apmixedsys.c +7 -7
index 95385bb67d55..d7d416172ab3 100644
@@ -140,13 +140,13 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
 static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
 {
 	const u8 *fhctl_node = "mediatek,mt8173-fhctl";
-	struct device_node *node = pdev->dev.of_node;
 	struct clk_hw_onecell_data *clk_data;
+	struct device *dev = &pdev->dev;
 	void __iomem *base;
 	struct clk_hw *hw;
 	int r;
 
-	base = of_iomap(node, 0);
+	base = of_iomap(dev->of_node, 0);
 	if (!base)
 		return -ENOMEM;
 

@@ -157,25 +157,25 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
 	}
 
 	fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
-	r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
-				    pllfhs, ARRAY_SIZE(pllfhs), clk_data);
+	r = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs,
+				    ARRAY_SIZE(pllfhs), clk_data);
 	if (r)
 		goto free_clk_data;
 
 	hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
 	if (IS_ERR(hw)) {
 		r = PTR_ERR(hw);
-		dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
+		dev_err(dev, "Failed to register ref2usb_tx: %d\n", r);
 		goto unregister_plls;
 	}
 	clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
 
-	hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
+	hw = devm_clk_hw_register_divider(dev, "hdmi_ref", "tvdpll_594m", 0,
 					  base + REGOFF_HDMI_REF, 16, 3,
 					  CLK_DIVIDER_POWER_OF_TWO, NULL);
 	clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
 
-	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+	r = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_data);
 	if (r)
 		goto unregister_ref2usb;
drivers/clk/mediatek/clk-mt8186-apmixedsys.c +1 -1
index 4b2b16578232..d35dd2632e43 100644
@@ -151,7 +151,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
 
 	fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
 
-	r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+	r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
 				    pllfhs, ARRAY_SIZE(pllfhs), clk_data);
 	if (r)
 		goto free_apmixed_data;
drivers/clk/mediatek/clk-mt8192-apmixedsys.c +1 -1
index 0b66a27e4d5a..b0563a285bd6 100644
@@ -162,7 +162,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
 
 	fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
 
-	r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+	r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
 				    pllfhs, ARRAY_SIZE(pllfhs), clk_data);
 	if (r)
 		goto free_clk_data;
drivers/clk/mediatek/clk-mt8195-apmixedsys.c +1 -1
index 282a3137dc89..44917ab034c5 100644
@@ -181,7 +181,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
 
 	fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
 
-	r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
+	r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
 				    pllfhs, ARRAY_SIZE(pllfhs), clk_data);
 	if (r)
 		goto free_apmixed_data;
drivers/clk/mediatek/clk-pllfh.c +8 -5
index 62bfe4a480f1..8ad11023d911 100644
@@ -10,6 +10,7 @@
 #include <linux/slab.h>
 #include <linux/clkdev.h>
 #include <linux/delay.h>
+#include <linux/device.h>
 
 #include "clk-mtk.h"
 #include "clk-pllfh.h"

@@ -149,7 +150,7 @@ static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
 }
 
 static struct clk_hw *
-mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
+mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data,
 		       struct mtk_pllfh_data *pllfh_data, void __iomem *base)
 {
 	struct clk_hw *hw;

@@ -166,6 +167,8 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
 		goto out;
 	}
 
+	fh->clk_pll.dev = dev;
+
 	hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
 				      &mtk_pllfh_ops);
 

@@ -194,7 +197,7 @@ static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
 	kfree(fh);
 }
 
-int mtk_clk_register_pllfhs(struct device_node *node,
+int mtk_clk_register_pllfhs(struct device *dev,
 			    const struct mtk_pll_data *plls, int num_plls,
 			    struct mtk_pllfh_data *pllfhs, int num_fhs,
 			    struct clk_hw_onecell_data *clk_data)

@@ -203,7 +206,7 @@ int mtk_clk_register_pllfhs(struct device_node *node,
 	int i;
 	struct clk_hw *hw;
 
-	base = of_iomap(node, 0);
+	base = of_iomap(dev->of_node, 0);
 	if (!base) {
 		pr_err("%s(): ioremap failed\n", __func__);
 		return -EINVAL;

@@ -218,9 +221,9 @@ int mtk_clk_register_pllfhs(struct device_node *node,
 		use_fhctl = fhctl_is_supported_and_enabled(pllfh);
 
 		if (use_fhctl)
-			hw = mtk_clk_register_pllfh(pll, pllfh, base);
+			hw = mtk_clk_register_pllfh(dev, pll, pllfh, base);
 		else
-			hw = mtk_clk_register_pll(NULL, pll, base);
+			hw = mtk_clk_register_pll(dev, pll, base);
 
 		if (IS_ERR(hw)) {
 			pr_err("Failed to register %s clk %s: %ld\n",
drivers/clk/mediatek/clk-pllfh.h +1 -1
index 5f419c2ec01f..a4f337acad71 100644
@@ -68,7 +68,7 @@ struct fh_operation {
 	int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
 };
 
-int mtk_clk_register_pllfhs(struct device_node *node,
+int mtk_clk_register_pllfhs(struct device *dev,
 			    const struct mtk_pll_data *plls, int num_plls,
 			    struct mtk_pllfh_data *pllfhs, int num_pllfhs,
 			    struct clk_hw_onecell_data *clk_data);
Signature · 1 line
2.52.0
maintainer Applied
#11 lore raw

Re: [PATCH RESEND v3 4/5] clk: mediatek: Refactor pllfh registration to pass device

Quoting Nicolas Frattaroli (2025-12-15 03:24:01)

Quoted 10 lines

After refactoring all of PLL to pass the device, it's now fairly easy to refactor pllfh and its users, as pllfh registration wraps PLL registration.

Do this refactor and move all of the pllfh users to pass the device as well.

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

author
#12 lore raw

PATCH RESEND v3 5/5 clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks

In reply to Nicolas Frattaroli

All the MFGPLL require MFG_EB to be on for any operation on them, and they only tick when MFG_EB is on as well, therefore making this a parent-child relationship.

This dependency wasn't clear during the initial upstreaming of these clock controllers, as it only made itself known when I could observe the effects of the clock by bringing up a different piece of hardware.

Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it when initialising the pll to then translate it into the actual CLK_OPS_PARENT_ENABLE flag.

Then add the mfg_eb parent to the mfgpll clocks, and set the new PLL_PARENT_EN flag.

Fixes 03dc02f8c7dc ("clk: mediatek: Add MT8196 mfg clock support")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>
---
 drivers/clk/mediatek/clk-mt8196-mfg.c | 13 +++++++------
 drivers/clk/mediatek/clk-pll.c        |  3 +++
 drivers/clk/mediatek/clk-pll.h        |  1 +
 3 files changed, 11 insertions(+), 6 deletions(-)
drivers/clk/mediatek/clk-mt8196-mfg.c +7 -6
index 8e09c0f7b754..a317183f1681 100644
@@ -58,24 +58,25 @@
 		.pcw_shift = _pcw_shift,			\
 		.pcwbits = _pcwbits,				\
 		.pcwibits = MT8196_INTEGER_BITS,		\
+		.parent_name = "mfg_eb",			\
 	}
 
 static const struct mtk_pll_data mfg_ao_plls[] = {
-	PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
-	    BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
+	PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0,
+	    PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
 	    MFGPLL_CON1, 0, 22),
 };
 
 static const struct mtk_pll_data mfgsc0_ao_plls[] = {
 	PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
-	    MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
-	    MFGPLL_SC0_CON1, 0, 22),
+	    MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,
+	    0, 0, 0, MFGPLL_SC0_CON1, 0, 22),
 };
 
 static const struct mtk_pll_data mfgsc1_ao_plls[] = {
 	PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
-	    MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
-	    MFGPLL_SC1_CON1, 0, 22),
+	    MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,
+	    0, 0, 0, MFGPLL_SC1_CON1, 0, 22),
 };
 
 static const struct of_device_id of_match_clk_mt8196_mfg[] = {
drivers/clk/mediatek/clk-pll.c +3 -0
index c4f9c06e5133..0f3759fcd9d0 100644
@@ -359,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
 
 	init.name = data->name;
 	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
+	if (data->flags & PLL_PARENT_EN)
+		init.flags |= CLK_OPS_PARENT_ENABLE;
+
 	init.ops = pll_ops;
 	if (data->parent_name)
 		init.parent_names = &data->parent_name;
drivers/clk/mediatek/clk-pll.h +1 -0
index f6493699c4e3..f49dc2732ffe 100644
@@ -19,6 +19,7 @@ struct mtk_pll_div_table {
 
 #define HAVE_RST_BAR	BIT(0)
 #define PLL_AO		BIT(1)
+#define PLL_PARENT_EN	BIT(2)
 #define POSTDIV_MASK	GENMASK(2, 0)
 
 struct mtk_pll_data {
Signature · 1 line
2.52.0
maintainer Applied
#13 lore raw

Re: [PATCH RESEND v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks

Quoting Nicolas Frattaroli (2025-12-15 03:24:02)

Quoted 12 lines

All the MFGPLL require MFG_EB to be on for any operation on them, and they only tick when MFG_EB is on as well, therefore making this a parent-child relationship.

This dependency wasn't clear during the initial upstreaming of these clock controllers, as it only made itself known when I could observe the effects of the clock by bringing up a different piece of hardware.

Add a new PLL_PARENT_EN flag to mediatek's clk-pll.h, and check for it when initialising the pll to then translate it into the actual CLK_OPS_PARENT_ENABLE flag.

Quoted 7 lines

Then add the mfg_eb parent to the mfgpll clocks, and set the new PLL_PARENT_EN flag.

Fixes 03dc02f8c7dc ("clk: mediatek: Add MT8196 mfg clock support")
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Signed-off-by Nicolas Frattaroli <[email protected]>

---

Applied to clk-next

maintainer Reviewed-by on the v3 series
#14 lore raw
In reply to Nicolas Frattaroli

Il 15/12/25 11:23, Nicolas Frattaroli ha scritto:

Quoted 9 lines

This series refactors all users of mtk-pll, just so we can enable runtime power management for the clock controllers that want it. It's also generally more useful to have the struct device in the pll code, rather than the device node.

Also fix up MT8196 mfgpll to declare its parent-child relationship with mfg_eb, and fix the common clock framework core to take CLK_OPS_PARENT_ENABLE into account for the recalc_rate op as well.

Quoted 7 lines

The reason why this is all in the same series is that it grew out of me first modelling this as an RPM clock for mfgpll, which Angelo disagreed with, so I did some investigation and it seems MFG_EB indeed is a parent clock. However, the earlier refactoring to pass the device pointer down is still useful.

Signed-off-by Nicolas Frattaroli <[email protected]>

Whole series is

Reviewed-by AngeloGioacchino Del Regno <[email protected]>
Quoted 65 lines

---
Changes in v3:
- Make device_node forward declaration a device forward declaration
- Remove forward declarations of struct clk_ops and struct clk_hw_onecell_data. (clk-provider.h include remains as it's needed
for a complete type of clk_hw)
- Move PLL_PARENT_EN flag to individual mfgpll definitions.
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Drop bindings patch
- Drop mfgpll RPM patch
- Add patch to also transition pllfh to passing device
- Add fixes patch to make CLK_OPS_PARENT_ENABLE also apply to the
recalc_rate operation
- Remodel mfgpll's mfg_eb dependency as parent-child with CLK_OPS_PARENT_ENABLE
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Nicolas Frattaroli (5):
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
clk: mediatek: Refactor pll registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks

  drivers/clk/clk.c                            | 13 +++++++++++++
  drivers/clk/mediatek/clk-mt2701.c            |  2 +-
  drivers/clk/mediatek/clk-mt2712-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt6735-apmixedsys.c |  4 ++--
  drivers/clk/mediatek/clk-mt6765.c            |  2 +-
  drivers/clk/mediatek/clk-mt6779.c            |  2 +-
  drivers/clk/mediatek/clk-mt6795-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt6797.c            |  2 +-
  drivers/clk/mediatek/clk-mt7622-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt7629.c            |  2 +-
  drivers/clk/mediatek/clk-mt7981-apmixed.c    |  2 +-
  drivers/clk/mediatek/clk-mt7986-apmixed.c    |  2 +-
  drivers/clk/mediatek/clk-mt7988-apmixed.c    |  2 +-
  drivers/clk/mediatek/clk-mt8135-apmixedsys.c |  3 ++-
  drivers/clk/mediatek/clk-mt8167-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8173-apmixedsys.c | 14 +++++++-------
  drivers/clk/mediatek/clk-mt8183-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8186-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8188-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8192-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8195-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8195-apusys_pll.c |  3 ++-
  drivers/clk/mediatek/clk-mt8196-apmixedsys.c |  3 ++-
  drivers/clk/mediatek/clk-mt8196-mcu.c        |  2 +-
  drivers/clk/mediatek/clk-mt8196-mfg.c        | 15 ++++++++-------
  drivers/clk/mediatek/clk-mt8196-vlpckgen.c   |  2 +-
  drivers/clk/mediatek/clk-mt8365-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-mt8516-apmixedsys.c |  2 +-
  drivers/clk/mediatek/clk-pll.c               | 19 +++++++++++++------
  drivers/clk/mediatek/clk-pll.h               | 15 ++++++++-------
  drivers/clk/mediatek/clk-pllfh.c             | 13 ++++++++-----
  drivers/clk/mediatek/clk-pllfh.h             |  2 +-
  32 files changed, 87 insertions(+), 59 deletions(-)

---
base-commit: adff43957b0d8b9f6ad0e1b1f6daa7136f9ffbef
change-id: 20250929-mtk-pll-rpm-bf28192dd016

Best regards,