arm64: dts: hi3798cv200: Fix clocks order of sd0
Subsystems (2)
PATCH 1/1 arm64: dts: hi3798cv200: Fix clocks order of sd0
"ciu" and "biu" were incorrectly swapped. Fix their order.
Signed-off-by David Yang <[email protected]>
--- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +2 -2
@@ -302,8 +302,8 @@ sd0: mmc@9820000 { compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; + clocks = <&crg HISTB_SDIO0_BIU_CLK>, + <&crg HISTB_SDIO0_CIU_CLK>; clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset";
Signature · 1 line
2.39.2
Hi David，
Quoted 13 lines · David Yang
"ciu" and "biu" were incorrectly swapped. Fix their order.
Signed-off-by David Yang <[email protected]>--- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +0
-0
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi sd0: mmc@9820000 { · line 309
Quoted 10 lines
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +2
-2@@ -302,8 +302,8 @@ sd0: mmc@9820000 { compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; + clocks = <&crg HISTB_SDIO0_BIU_CLK>, + <&crg HISTB_SDIO0_CIU_CLK>; clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset";
Applied to the HiSilicon arm64 dt tree.
Thanks!
Best Regards,
Wei