vpmu: Add the BTS extension
PATCH 1/1 vpmu: Add the BTS extension
Add the BTS functionality to the existing vpmu implementation for Intel cpus.
xen/arch/x86/hvm/vmx/vmx.c | 12 +- xen/arch/x86/hvm/vmx/vpmu_core2.c | 156 +++++++++++++++++++++++++----- xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 1 + xen/include/asm-x86/hvm/vpmu.h | 3 + xen/include/asm-x86/msr-index.h | 5 + 5 files changed, 148 insertions(+), 29 deletions(-)
xen/arch/x86/hvm/vmx/vmx.c +10 -2
@@ -1823,6 +1823,9 @@ static int vmx_msr_read_intercept(unsign/* Debug Trace Store is not supported. */ *msr_content |=MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL ; +/* Perhaps vpmu will change some bits. */ +if (vpmu_do_rdmsr (msr, msr_content) ) + goto done;break ;default :if (vpmu_do_rdmsr (msr, msr_content) )
@@ -1950,9 +1953,14 @@ static int vmx_msr_write_intercept(unsigint i, rc =0 ;uint64_t supported =IA32_DEBUGCTLMSR_LBR |IA32_DEBUGCTLMSR_BTF ; -if ( !msr_content || (msr_content & ~supported) ) +if ( !msr_content )break ; - +if ( msr_content & ~supported ) + { +/* Perhaps some other bits are supported in vpmu. */ +if ( !vpmu_do_wrmsr (msr, msr_content) ) +break ; + }if ( msr_content &IA32_DEBUGCTLMSR_LBR ) {const struct lbr_info *lbr =last_branch_msr_get ();
xen/arch/x86/hvm/vmx/vpmu_core2.c +129 -27
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xen/include/asm-x86/hvm/vmx/vpmu_core2.h +1 -0
@@ -29,6 +29,7 @@ struct arch_msr_pair { };struct core2_pmu_enable { +char ds_area_enable;char fixed_ctr_enable[3 ];char arch_pmc_enable[1 ]; };
xen/include/asm-x86/hvm/vpmu.h +3 -0
@@ -72,6 +72,9 @@ struct vpmu_struct {#define VPMU_CONTEXT_LOADED 0x2#define VPMU_RUNNING 0x4#define VPMU_PASSIVE_DOMAIN_ALLOCATED 0x8 +#define VPMU_CPU_HAS_DS 0x10/* Has Debug Store */ +#define VPMU_CPU_HAS_BTS 0x20/* Has Branche Trace Store */ +#define vpmu_set (_vpmu, _x) ((_vpmu)->flags |= (_x))#define vpmu_reset (_vpmu, _x) ((_vpmu)->flags &= ~(_x))
xen/include/asm-x86/msr-index.h +5 -0
@@ -67,6 +67,11 @@#define MSR_IA32_DEBUGCTLMSR 0x000001d9#define IA32_DEBUGCTLMSR_LBR (1<<0)/* Last Branch Record */ #define IA32_DEBUGCTLMSR_BTF (1<<1)/* Single Step on Branches */ +#define IA32_DEBUGCTLMSR_TR (1<<6)/* Trace Message Enable */ +#define IA32_DEBUGCTLMSR_BTS (1<<7)/* Branch Trace Store */ +#define IA32_DEBUGCTLMSR_BTINT (1<<8)/* Branch Trace Interrupt */ +#define IA32_DEBUGCTLMSR_BTS_OFF_OS (1<<9)/* BTS off if CPL 0 */ +#define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10)/* BTS off if CPL > 0 */ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
Signature · 1 line
Company details: http://ts.fujitsu.com/imprint.html
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 409
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Quoted 1 line · Dietmar Hahn
xen/arch/x86/hvm/vmx/vpmu_core2.c +6
-0@@ -401,7 +401,31 @@ static int core2_vpmu_do_wrmsr(unsignedstruct core2_vpmu_context *core2_vpmu_cxt =NULL ;if ( !core2_vpmu_msr_common_check (msr, &type, &index) ) + { +/* Special handling for BTS */ +if ( msr ==MSR_IA32_DEBUGCTLMSR ) + { +uint64_t supported =IA32_DEBUGCTLMSR_TR |IA32_DEBUGCTLMSR_BTS | +IA32_DEBUGCTLMSR_BTINT ;
Was the code to make BTINT work magically in place already? I can't spot anything to the effect in the patch...
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xen/arch/x86/hvm/vmx/vpmu_core2.c +21
-2+ +if (cpu_has (¤t_cpu_data,X86_FEATURE_DSCPL ) ) + { + supported |=IA32_DEBUGCTLMSR_BTS_OFF_OS | +IA32_DEBUGCTLMSR_BTS_OFF_USR ; + } +if ( msr_content & supported ) + { +if ( !vpmu_is_set (vpmu,VPMU_CPU_HAS_BTS ) ) + { +gdprintk (XENLOG_WARNING ,"Debug Store is not supported on this cpu\n" ); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 0 ; + } +return 1 ; + } + }return 0 ; + } core2_vpmu_cxt = vpmu->context; switch ( msr )@@ -420,8 +444,26 @@ static int core2_vpmu_do_wrmsr(unsigned "which is not supported.\n");return 1 ;case MSR_IA32_DS_AREA : -gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); -return 1 ; +if (vpmu_is_set (vpmu,VPMU_CPU_HAS_DS ) ) + { +if (!msr_content || !is_canonical_address (msr_content))
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 459
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xen/arch/x86/hvm/vmx/vpmu_core2.c +10
-0+ { +gdprintk (XENLOG_WARNING ,"Illegal address for IA32_DS_AREA: 0x%lx\n" , + msr_content); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 1 ; + } + else + { + core2_vpmu_cxt->pmu_enable->ds_area_enable = msr_content ?1 :0 ; +break ;
How do you manage to get away without storing the value the guest attempted to write?
Jan
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+ } + } +else + { +gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); +return 1 ; + }case MSR_CORE_PERF_GLOBAL_CTRL : global_ctrl = msr_content;for ( i =0 ; i <core2_get_pmc_count (); i++ )
Am Dienstag 14 Februar 2012, 11:51:39 schrieb Jan Beulich:
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-0@@ -401,7 +401,31 @@ static int core2_vpmu_do_wrmsr(unsigned struct core2_vpmu_context *core2_vpmu_cxt = NULL;
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 409
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xen/arch/x86/hvm/vmx/vpmu_core2.c +6
-0if ( !core2_vpmu_msr_common_check (msr, &type, &index) ) + { +/* Special handling for BTS */ +if ( msr ==MSR_IA32_DEBUGCTLMSR ) + { +uint64_t supported =IA32_DEBUGCTLMSR_TR |IA32_DEBUGCTLMSR_BTS | +IA32_DEBUGCTLMSR_BTINT ;Was the code to make BTINT work magically in place already? I can't spot anything to the effect in the patch...
No, BTINT wasn't handled before.
The writing of the MSR's is done in the calling function vmx_msr_write_intercept() in xen/arch/x86/hvm/vmx/vmx.c.
There I added the call of vpmu_do_wrmsr() in the case of MSR_IA32_DEBUGCTLMSR. If vpmu_do_wrmsr() returns 1 the MSR gets written in the line
__vmwrite(GUEST_IA32_DEBUGCTL, msr_content);
Maybe I can change this and write the MSR here in this function.
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xen/arch/x86/hvm/vmx/vpmu_core2.c +26
-2+ +if (cpu_has (¤t_cpu_data,X86_FEATURE_DSCPL ) ) + { + supported |=IA32_DEBUGCTLMSR_BTS_OFF_OS | +IA32_DEBUGCTLMSR_BTS_OFF_USR ; + } +if ( msr_content & supported ) + { +if ( !vpmu_is_set (vpmu,VPMU_CPU_HAS_BTS ) ) + { +gdprintk (XENLOG_WARNING ,"Debug Store is not supported on this cpu\n" ); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 0 ; + } +return 1 ; + } + }return 0 ; + } core2_vpmu_cxt = vpmu->context; switch ( msr )@@ -420,8 +444,26 @@ static int core2_vpmu_do_wrmsr(unsigned "which is not supported.\n");return 1 ;case MSR_IA32_DS_AREA : -gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); -return 1 ; +if (vpmu_is_set (vpmu,VPMU_CPU_HAS_DS ) ) + { +if (!msr_content || !is_canonical_address (msr_content)) + { +gdprintk (XENLOG_WARNING ,"Illegal address for IA32_DS_AREA: 0x%lx\n" , + msr_content); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 1 ;
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 459
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xen/arch/x86/hvm/vmx/vpmu_core2.c +5
-0+ } +else + { + core2_vpmu_cxt->pmu_enable->ds_area_enable = msr_content ?1 :0 ; +break ;How do you manage to get away without storing the value the guest attempted to write?
In the case of MSR_IA32_DS_AREA the value is stored some lines later core2_vpmu_save_msr_context(v, type, index, msr_content);
in an internal data structure.
The values of this structure are loaded - core2_vpmu_load() - and stored
- core2_vpmu_save() - on context switch.
Thanks.
Dietmar.
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Jan
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 469
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+ } + } +else + { +gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); +return 1 ; + }case MSR_CORE_PERF_GLOBAL_CTRL : global_ctrl = msr_content;for ( i =0 ; i <core2_get_pmc_count (); i++ )_______________________________________________
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Company details: http://ts.fujitsu.com/imprint.html
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Quoted 1 line · Dietmar Hahn
Am Dienstag 14 Februar 2012, 11:51:39 schrieb Jan Beulich:
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 408
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xen/arch/x86/hvm/vmx/vpmu_core2.c +5
-0@@ -401,7 +401,31 @@ static int core2_vpmu_do_wrmsr(unsignedstruct core2_vpmu_context *core2_vpmu_cxt =NULL ;if ( !core2_vpmu_msr_common_check (msr, &type, &index) ) + { +/* Special handling for BTS */ +if ( msr ==MSR_IA32_DEBUGCTLMSR ) + { + uint64_t supported = IA32_DEBUGCTLMSR_TR |
IA32_DEBUGCTLMSR_BTS|Quoted 4 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 409
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xen/arch/x86/hvm/vmx/vpmu_core2.c +1
-0+IA32_DEBUGCTLMSR_BTINT ;Was the code to make BTINT work magically in place already? I can't spot anything to the effect in the patch...
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No, BTINT wasn't handled before.
The writing of the MSR's is done in the calling functionvmx_msr_write_intercept()inxen/arch/x86/hvm/vmx/vmx.c. There I added the call ofvpmu_do_wrmsr()in the case ofMSR_IA32_DEBUGCTLMSR.
Ifvpmu_do_wrmsr()returns 1 the MSR gets written in the line
__vmwrite(GUEST_IA32_DEBUGCTL, msr_content);
The question was more towards what happens if a guest enables this bit without first setting up the corresponding LVT.
Plus enforcing the buffer requirements to avoid CPU deadlock (contiguous present pages, alignment). Failure to do so can hang the CPU, and hence would represent a DoS vulnerability.
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Maybe I can change this and write the MSR here in this function.
That might still be good to do, so checks and actual writing are in one place.
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned
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xen/arch/x86/hvm/vmx/vpmu_core2.c +11
-0+ +if (cpu_has (¤t_cpu_data,X86_FEATURE_DSCPL ) ) + { + supported |=IA32_DEBUGCTLMSR_BTS_OFF_OS | +IA32_DEBUGCTLMSR_BTS_OFF_USR ; + } +if ( msr_content & supported ) + { +if ( !vpmu_is_set (vpmu,VPMU_CPU_HAS_BTS ) ) + { + gdprintk(XENLOG_WARNING, "Debug Store is not supportedon this cpu\n");
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 0 ; + } +return 1 ; + } + }return 0 ; + }Quoted 13 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 451
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xen/arch/x86/hvm/vmx/vpmu_core2.c +5
-2core2_vpmu_cxt = vpmu->context; switch ( msr )@@ -420,8 +444,26 @@ static int core2_vpmu_do_wrmsr(unsigned "which is not supported.\n");return 1 ;case MSR_IA32_DS_AREA : -gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); -return 1 ; +if (vpmu_is_set (vpmu,VPMU_CPU_HAS_DS ) ) + { +if (!msr_content || !is_canonical_address (msr_content)) + { + gdprintk(XENLOG_WARNING, "Illegal address for
IA32_DS_AREA: 0x%lx\n",Quoted 7 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+ msr_content); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 1 ; + } +else + { + core2_vpmu_cxt->pmu_enable->ds_area_enable = msr_content ? 1 :0;
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-0+ break;
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How do you manage to get away without storing the value the guest attempted to write?
In the case of
MSR_IA32_DS_AREAthe value is stored some lines latercore2_vpmu_save_msr_context(v, type, index, msr_content);
in an internal data structure.
The values of this structure are loaded -core2_vpmu_load()- and stored
-core2_vpmu_save()- on context switch.
Okay, I must have missed that part then.
However, in the context of the above the simple is_canonical_address() check here clearly isn't enough.
Jan
Am Dienstag 14 Februar 2012, 13:27:08 schrieb Jan Beulich:
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Quoted 1 line · Dietmar Hahn
Am Dienstag 14 Februar 2012, 11:51:39 schrieb Jan Beulich:
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 408
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Quoted 1 line · Dietmar Hahn
xen/arch/x86/hvm/vmx/vpmu_core2.c +5
-0@@ -401,7 +401,31 @@ static int core2_vpmu_do_wrmsr(unsignedstruct core2_vpmu_context *core2_vpmu_cxt =NULL ;if ( !core2_vpmu_msr_common_check (msr, &type, &index) ) + { +/* Special handling for BTS */ +if ( msr ==MSR_IA32_DEBUGCTLMSR ) + { + uint64_t supported = IA32_DEBUGCTLMSR_TR |
IA32_DEBUGCTLMSR_BTS|Quoted 4 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 409
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xen/arch/x86/hvm/vmx/vpmu_core2.c +1
-0+IA32_DEBUGCTLMSR_BTINT ;Was the code to make BTINT work magically in place already? I can't spot anything to the effect in the patch...
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No, BTINT wasn't handled before.
The writing of the MSR's is done in the calling functionvmx_msr_write_intercept()inxen/arch/x86/hvm/vmx/vmx.c. There I added the call ofvpmu_do_wrmsr()in the case ofMSR_IA32_DEBUGCTLMSR.
Ifvpmu_do_wrmsr()returns 1 the MSR gets written in the line
__vmwrite(GUEST_IA32_DEBUGCTL, msr_content);
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The question was more towards what happens if a guest enables this bit without first setting up the corresponding LVT.
The apic is checked and set, see apic_write_around() in vpmu_core2.c.
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Plus enforcing the buffer requirements to avoid CPU deadlock (contiguous present pages, alignment). Failure to do so can hang the CPU, and hence would represent a DoS vulnerability.
I'm not sure what you mean here. Are you speaking about the DS buffer? If yes, this is no problem, because the DS buffer addressm must be a domU virtual address. The processor only writes data into the buffer, if the domU is running so in the worst case the domU gets triggered a page fault or what I testet a triple fault occurs and the domU gets rebootet.
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Maybe I can change this and write the MSR here in this function.
That might still be good to do, so checks and actual writing are in one place.
After thinking about this. The writing should better be in vmx_msr_write_intercept() because vpmu_do_wrmsr() in this case does only a check of illegal set bits in the vpmu environment. In such a case a TRAP_gp_fault is initiated otherwise nothing is done.
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xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned
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xen/arch/x86/hvm/vmx/vpmu_core2.c +11
-0+ +if (cpu_has (¤t_cpu_data,X86_FEATURE_DSCPL ) ) + { + supported |=IA32_DEBUGCTLMSR_BTS_OFF_OS | +IA32_DEBUGCTLMSR_BTS_OFF_USR ; + } +if ( msr_content & supported ) + { +if ( !vpmu_is_set (vpmu,VPMU_CPU_HAS_BTS ) ) + { + gdprintk(XENLOG_WARNING, "Debug Store is not supportedon this cpu\n");
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 0 ; + } +return 1 ; + } + }return 0 ; + }Quoted 13 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned · line 451
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xen/arch/x86/hvm/vmx/vpmu_core2.c +5
-2core2_vpmu_cxt = vpmu->context; switch ( msr )@@ -420,8 +444,26 @@ static int core2_vpmu_do_wrmsr(unsigned "which is not supported.\n");return 1 ;case MSR_IA32_DS_AREA : -gdprintk (XENLOG_WARNING ,"Guest setting of DTS is ignored.\n" ); -return 1 ; +if (vpmu_is_set (vpmu,VPMU_CPU_HAS_DS ) ) + { +if (!msr_content || !is_canonical_address (msr_content)) + { + gdprintk(XENLOG_WARNING, "Illegal address for
IA32_DS_AREA: 0x%lx\n",Quoted 7 lines
xen/arch/x86/hvm/vmx/vpmu_core2.c static int core2_vpmu_do_wrmsr(unsigned
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xen/arch/x86/hvm/vmx/vpmu_core2.c +7
-0+ msr_content); +vmx_inject_hw_exception (TRAP_gp_fault,0 ); +return 1 ; + } +else + { + core2_vpmu_cxt->pmu_enable->ds_area_enable = msr_content ? 1 :0;
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How do you manage to get away without storing the value the guest attempted to write?
In the case of
MSR_IA32_DS_AREAthe value is stored some lines latercore2_vpmu_save_msr_context(v, type, index, msr_content);
in an internal data structure.
The values of this structure are loaded -core2_vpmu_load()- and stored
-core2_vpmu_save()- on context switch.
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Okay, I must have missed that part then.
However, in the context of the above the simple
is_canonical_address()check here clearly isn't enough.
As described above, the access to this buffer is only done while running the domU.
Dietmar.
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Jan
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Quoted 1 line · Dietmar Hahn
Am Dienstag 14 Februar 2012, 13:27:08 schrieb Jan Beulich:
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Plus enforcing the buffer requirements to avoid CPU deadlock (contiguous present pages, alignment). Failure to do so can hang the CPU, and hence would represent a DoS vulnerability.
I'm not sure what you mean here. Are you speaking about the DS buffer? If yes, this is no problem, because the DS buffer addressm must be a domU virtual address. The processor only writes data into the buffer, if the domU is running so in the worst case the domU gets triggered a page fault or what I testet a triple fault occurs and the domU gets rebootet.
This certainly can be CPU model dependent, but on raw hardware I know that not meeting the buffer constraints can hang (not triple fault, perhaps a live lock) a CPU. Therefore, unless you can prove this is impossible when running in VMX non-root, you will have to add provisions for this (and this was the major reason keeping me from trying to add DS support a year or two ago). At the very minimum the whole functionality would otherwise need to be disabled by default, and when enabled a prominent warning be issued (along the lines of that of sync_console).
Jan
Am Dienstag 14 Februar 2012, 14:50:30 schrieb Jan Beulich:
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Quoted 1 line · Dietmar Hahn
Am Dienstag 14 Februar 2012, 13:27:08 schrieb Jan Beulich:
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Plus enforcing the buffer requirements to avoid CPU deadlock (contiguous present pages, alignment). Failure to do so can hang the CPU, and hence would represent a DoS vulnerability.
I'm not sure what you mean here. Are you speaking about the DS buffer? If yes, this is no problem, because the DS buffer addressm must be a domU virtual address. The processor only writes data into the buffer, if the domU is running so in the worst case the domU gets triggered a page fault or what I testet a triple fault occurs and the domU gets rebootet.
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This certainly can be CPU model dependent, but on raw hardware I know that not meeting the buffer constraints can hang (not triple fault, perhaps a live lock) a CPU. Therefore, unless you can prove this is impossible when running in VMX non-root, you will have to add provisions for this (and this was the major reason keeping me from trying to add DS support a year or two ago). At the very minimum the whole functionality would otherwise need to be disabled by default, and when enabled a prominent warning be issued (along the lines of that of
sync_console).
Of course I can't prove anything.
While I experimented with this I couldn't find any statement in the cpu specs about this buffer stuff and what the cpu does with wrong addresses. I found that writing a non canonical address into the MSR_IA32_DS_AREA leads to a
general protection fault in the hypervisor. This was the cause for the check of
is_canonical_address(msr_content).
But with this check I tried different addresses, also wrong addresses within the buffer and the hypervisor didn't crash anymore but the domU always failed with the:
hvm.c:1141:d10 Triple fault on VCPU0 - invoking HVM system reset. But of course there may be other critical pathes.
Currently we have the vpmu boot flag. So by default this is disabled. The question is, should the BTS suff get an own flag or should we change the vpmu flag to a string with multiple meanings? If the warning should be printed only for the BTS stuff then an own BTS flag is needed.
Dietmar.
Signature · 1 line
Company details: http://ts.fujitsu.com/imprint.html
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Quoted 1 line · Dietmar Hahn
Currently we have the vpmu boot flag. So by default this is disabled. The question is, should the BTS suff get an own flag or should we change the vpmu flag to a string with multiple meanings? If the warning should be printed only for the BTS stuff then an own BTS flag is needed.
I'd recommend "vpmu=bts" to enable vPMU including BTS, while the normal boolean values (parse_bool()) would enable the "safe" parts of vPMU code only.
Jan