arm64: dts: rockchip: add RK3399-Gru-Bob and prepare for Scarlet
Subsystems (2)
Heiko Stuebner
maintainercover arm64: dts: rockchip: add RK3399-Gru-Bob and prepare for Scarlet
So far the Gru series of ChromeOS devices has seen 3 public devices. Two clamshell devices with the already supported Kevin and Bob (aka Chromebook Flip C101PA), as well as one table-style device Scarlet.
So this series not only adds a devicetree file for Bob, but also prepares for Scarlets arrival, in that common properties of the clamshell-devices get moved into a rk3399-gru-chromebook.dtsi, similar to what we have on RK3288-Veyron, as Scarlet does some things a bit differently.
Scarlet itself needs a bit more time, as its display is connected via dual-dsi, where the patches are still pending.
Heiko Stuebner (4):
arm64: dts: rockchip: move Chromebook-specific Gru-parts to a separate
file
arm64: dts: rockchip: add phandles to some nodes on rk3399-gru
arm64: dts: rockchip: move core edp from rk3399-kevin to shared
chromebook
arm64: dts: rockchip: add Google Bob
.../devicetree/bindings/arm/rockchip.txt | 9 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-gru-bob.dts | 79 ++++ .../dts/rockchip/rk3399-gru-chromebook.dtsi | 399 ++++++++++++++++++ .../boot/dts/rockchip/rk3399-gru-kevin.dts | 47 +-- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 328 +------------- 6 files changed, 496 insertions(+), 367 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
Signature · 1 line
2.17.0
Heiko Stuebner
maintainerPATCH 1/4 arm64: dts: rockchip: move Chromebook-specific Gru-parts to a separate file
Similar to rk3288-Veyron before, the Gru-series does contain Chromebook (aka clamshell laptops) and non-Chromebook devices. And while the two Chromebook devices Kevin and Bob are quite similar, Scarlet the tablet- device is quite different in its design.
Therefore move the Chromebook parts into a gru-chromebook dtsi file to make sharing easier.
Signed-off-by Heiko Stuebner <[email protected]>
--- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 365 ++++++++++++++++++ .../boot/dts/rockchip/rk3399-gru-kevin.dts | 8 +- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 322 --------------- 3 files changed, 366 insertions(+), 329 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi new file +363 -0
@@ -0,0 +1,363 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Chromebook shared properties + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/ { + pp900_ap: pp900-ap { + compatible = "regulator-fixed"; + regulator-name = "pp900_ap"; + + /* EC turns on w/ pp900_ap_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + /* EC turns on w/ pp900_usb_en */ + pp900_usb: pp900-ap { + }; + + /* EC turns on w/ pp900_pcie_en */ + pp900_pcie: pp900-ap { + }; + + pp3000: pp3000 { + compatible = "regulator-fixed"; + regulator-name = "pp3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3000_en>; + + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_centerlogic"; + + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + + ctrl-supply = <&ppvar_centerlogic_pwm>; + ctrl-voltage-range = <799434 1049925>; + + regulator-settling-time-up-us = <378>; + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ + ppvar_logic: ppvar-logic { + compatible = "regulator-fixed"; + regulator-name = "ppvar_logic"; + + /* EC turns on w/ ppvar_logic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800_audio: pp1800-audio { + compatible = "regulator-fixed"; + regulator-name = "pp1800_audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_audio_en>; + + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp1800>; + }; + + /* gpio is shared with pp3300_wifi_bt */ + pp1800_pcie: pp1800-pcie { + compatible = "regulator-fixed"; + regulator-name = "pp1800_pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_pd_l>; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Need to wait 1ms + ramp-up time before we can power on WiFi. + * This has been approximated as 8ms total. + */ + regulator-enable-ramp-delay = <8000>; + + vin-supply = <&pp1800>; + }; + + /* Always on; plain and simple */ + pp3000_ap: pp3000_emmc: pp3000 { + }; + + pp1500_ap_io: pp1500-ap-io { + compatible = "regulator-fixed"; + regulator-name = "pp1500_ap_io"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1500_en>; + + enable-active-high; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&pp1800>; + }; + + pp3300_disp: pp3300-disp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_disp"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_disp_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <2000>; + vin-supply = <&pp3300>; + }; + + /* EC turns on w/ pp3300_usb_en_l */ + pp3300_usb: pp3300 { + }; + + /* gpio is shared with pp1800_pcie and pinctrl is set there */ + pp3300_wifi_bt: pp3300-wifi-bt { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wifi_bt"; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3300>; + }; + + /* + * This is a bit of a hack. The WiFi module should be reset at least + * 1ms after its regulators have ramped up (max rampup time is ~7ms). + * With some stretching of the imagination, we can call the 1.8V + * regulator a supply. + */ + wlan_pd_n: wlan-pd-n { + compatible = "regulator-fixed"; + regulator-name = "wlan_pd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_reset_l>; + + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp1800_pcie>; + }; +}; + +&ppvar_bigcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_litcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_gpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + +ap_i2c_mic: &i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + headsetcodec: rt5514 at 57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + realtek,dmic-init-delay-ms = <20>; + }; +}; + +ap_i2c_tp: &i2c5 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* + * Note strange pullup enable. Apparently this avoids leakage but + * still allows us to get nice 4.7K pullups for high speed i2c + * transfers. Basically we want the pullup on whenever the ap is + * alive, so the "en" pin just gets set to output high. + */ + pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +}; + +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + usbc_extcon1: extcon at 1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; +}; + +&sound { + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio &cdn_dp>; +}; + +&spi2 { + wacky_spi_audio: spi2 at 0 { + compatible = "realtek,rt5514"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + wakeup-source; + }; +}; + +&pci_rootport { + mvl_wifi: wifi at 0,0 { + compatible = "pci1b4b,2b42"; + reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 + 0x83010000 0x0 0x00100000 0x0 0x00100000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake_l>; + wakeup-source; + }; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&pinctrl { + discrete-regulators { + pp1500_en: pp1500-en { + rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp1800_audio_en: pp1800-audio-en { + rockchip,pins = <RK_GPIO0 2 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + + pp3000_en: pp3000-en { + rockchip,pins = <RK_GPIO0 12 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp3300_disp_en: pp3300-disp-en { + rockchip,pins = <RK_GPIO4 27 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + wlan_module_pd_l: wlan-module-pd-l { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + }; +}; + +&wifi { + wifi_perst_l: wifi-perst-l { + rockchip,pins = <2 27 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; +};
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +1 -7
@@ -6,7 +6,7 @@ */ /dts-v1/; -#include "rk3399-gru.dtsi" +#include "rk3399-gru-chromebook.dtsi" #include <dt-bindings/input/linux-event-codes.h> /*
@@ -337,10 +337,4 @@ ap_i2c_dig: &i2c2 { rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - - wifi { - wlan_host_wake_l: wlan-host-wake-l { - rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; };
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +0 -322
467 lines not on this page · raw message
Signature · 1 line
2.17.0
Heiko Stuebner
maintainerPATCH 2/4 arm64: dts: rockchip: add phandles to some nodes on rk3399-gru
In reply to Heiko StuebnerSome nodes will need to be refined on a per board level, so add phandles to them to reference them later.
Signed-off-by Heiko Stuebner <[email protected]>
--- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +3 -3
@@ -267,7 +267,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>; - wake-on-bt { + wake_on_bt: wake-on-bt { label = "Wake-on-Bluetooth"; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>;
@@ -285,7 +285,7 @@ status = "okay"; }; - sound { + sound: sound { compatible = "rockchip,rk3399-gru-sound"; rockchip,cpu = <&i2s0 &i2s2>; };
@@ -813,7 +813,7 @@ ap_i2c_audio: &i2c8 { }; }; - wifi { + wifi: wifi { wlan_module_reset_l: wlan-module-reset-l { rockchip,pins = <1 11 RK_FUNC_GPIO &pcfg_pull_none>; };
Signature · 1 line
2.17.0
Heiko Stuebner
maintainerPATCH 3/4 arm64: dts: rockchip: move core edp from rk3399-kevin to shared chromebook
In reply to Heiko StuebnerBob needs the same backlight and core edp settings, so move these node to the shared dtsi that both will use as a base.
Signed-off-by Heiko Stuebner <[email protected]>
--- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 34 ++++++++++++++++ .../boot/dts/rockchip/rk3399-gru-kevin.dts | 39 ++----------------- 2 files changed, 38 insertions(+), 35 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +34 -0
@@ -191,6 +191,23 @@ vin-supply = <&pp1800_pcie>; }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 + 45 46 47 48 49 50 51 52 53 54 55 56 57 58 + 59 60 61 62 63 64 65 66 67 68 69 70 71 72 + 73 74 75 76 77 78 79 80 81 82 83 84 85 86 + 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; + default-brightness-level = <51>; + enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + power-supply = <&pp3300_disp>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwm-delay-us = <10000>; + }; }; &ppvar_bigcpu {
@@ -212,6 +229,23 @@ extcon = <&usbc_extcon0>, <&usbc_extcon1>; }; +&edp { + status = "okay"; + + ports { + edp_out: port at 1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint at 0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + ap_i2c_mic: &i2c1 { status = "okay";
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +4 -35
@@ -38,24 +38,6 @@ vin-supply = <&pp3300>; }; - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 1>; - brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 45 46 47 48 49 50 51 52 53 54 55 56 57 58 - 59 60 61 62 63 64 65 66 67 68 69 70 71 72 - 73 74 75 76 77 78 79 80 81 82 83 84 85 86 - 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; - default-brightness-level = <51>; - enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; - power-supply = <&pp3300_disp>; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en>; - pwm-delay-us = <10000>; - }; - edp_panel: edp-panel { compatible = "sharp,lq123p1jx31", "simple-panel"; backlight = <&backlight>;
@@ -87,6 +69,10 @@ }; }; +&backlight { + pwms = <&cros_ec_pwm 1>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>;
@@ -243,23 +229,6 @@ ap_i2c_dig: &i2c2 { }; }; -&edp { - status = "okay"; - - ports { - edp_out: port at 1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - edp_out_panel: endpoint at 0 { - reg = <0>; - remote-endpoint = <&panel_in_edp>; - }; - }; - }; -}; - &ppvar_bigcpu_pwm { regulator-min-microvolt = <798674>; regulator-max-microvolt = <1302172>;
Signature · 1 line
2.17.0
Heiko Stuebner
maintainerPATCH 4/4 arm64: dts: rockchip: add Google Bob
In reply to Heiko StuebnerAfter Kevin, the second chromebook-incarnation of the Gru series is Bob. This materializes as the Asus Chromebook Flip C101PA, whose formfactor is quite similar to Minnie from the Veyron series.
Add the devicetree file and binding update for it.
Signed-off-by Heiko Stuebner <[email protected]>
--- .../devicetree/bindings/arm/rockchip.txt | 9 +++ arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3399-gru-bob.dts | 79 +++++++++++++++++++ 3 files changed, 89 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
Documentation/devicetree/bindings/arm/rockchip.txt +9 -0
@@ -66,6 +66,15 @@ Rockchip platforms device tree bindings Required root node properties: - compatible = "geekbuying,geekbox", "rockchip,rk3368"; +- Google Bob (Asus Chromebook Flip C101PA): + Required root node properties: + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + - Google Brain (dev-board): Required root node properties: - compatible = "google,veyron-brain-rev0", "google,veyron-brain",
arch/arm64/boot/dts/rockchip/Makefile +1 -0
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts new file +79 -0
79 lines not on this page · raw message
Signature · 1 line
2.17.0
Heiko Stuebner
maintainercover arm64: dts: rockchip: add RK3399-Gru-Bob and prepare for Scarlet
In reply to Heiko StuebnerAm Donnerstag, 14. Juni 2018, 13:30:35 CEST schrieb Heiko Stuebner:
Quoted 13 lines
So far the Gru series of ChromeOS devices has seen 3 public devices. Two clamshell devices with the already supported Kevin and Bob (aka Chromebook Flip C101PA), as well as one table-style device Scarlet.
So this series not only adds a devicetree file for Bob, but also prepares for Scarlets arrival, in that common properties of the clamshell-devices get moved into a
rk3399-gru-chromebook.dtsi, similar to what we have on RK3288-Veyron, as Scarlet does some things a bit differently.Scarlet itself needs a bit more time, as its display is connected via dual-dsi, where the patches are still pending.
Quoted 7 lines
Heiko Stuebner (4):
arm64: dts: rockchip: move Chromebook-specific Gru-parts to a separate
file
arm64: dts: rockchip: add phandles to some nodes on rk3399-gru
arm64: dts: rockchip: move core edp from rk3399-kevin to shared
chromebook
arm64: dts: rockchip: add Google Bob
nobody complained for 3 weeks, so I've applied these 4 patches for 4.19.