mxc: Fix SDHC multi-instance clock

PATCH New Benoît Thébaudeau 2 participants 6 messages Sep 27, 2012 – Oct 10, 2012 MMC, SD and SDIO

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Benoît Thébaudeau

author

2012-09-27 20:31 UTC #0 lore raw

PATCH 1/1 mxc: Fix SDHC multi-instance clock

On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not suitable for the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).

This patch fixes this issue by adding a configuration field for the SDHC input clock frequency.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Eric B?nard <[email protected]>

Cc Otavio Salvador <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Jason Liu <[email protected]>

Cc Matt Sealey <[email protected]>

Cc Andy Fleming <[email protected]>

---
This patch should be applied after (series of series...):
http://patchwork.ozlabs.org/patch/187467/
http://patchwork.ozlabs.org/patch/187468/
http://patchwork.ozlabs.org/patch/187475/

 .../board/esg/ima3-mx53/ima3-mx53.c                |    1 +
 .../board/freescale/mx35pdk/mx35pdk.c              |    2 ++
 .../board/freescale/mx51evk/mx51evk.c              |    4 ++++
 .../board/freescale/mx53ard/mx53ard.c              |    4 ++++
 .../board/freescale/mx53evk/mx53evk.c              |    4 ++++
 .../board/freescale/mx53loco/mx53loco.c            |    3 +++
 .../board/freescale/mx53smd/mx53smd.c              |    3 +++
 .../board/freescale/mx6qarm2/mx6qarm2.c            |    4 ++++
 .../board/freescale/mx6qsabrelite/mx6qsabrelite.c  |    3 +++
 .../board/genesi/mx51_efikamx/efikamx.c            |    4 ++++
 .../board/ttcontrol/vision2/vision2.c              |    2 ++
 .../drivers/mmc/fsl_esdhc.c                        |    5 +++--
 .../include/fsl_esdhc.h                            |    1 +
 13 files changed, 38 insertions(+), 2 deletions(-)

board/esg/ima3-mx53/ima3-mx53.c +1 -0

index e947330..41d6bb6 100644
@@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
 		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif

board/freescale/mx35pdk/mx35pdk.c +2 -0

index 7cb6b30..a12531f 100644
@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/mx35_pins.h>
 #include <asm/arch/iomux.h>
 #include <i2c.h>

@@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
 	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }

board/freescale/mx51evk/mx51evk.c +4 -0

index a94701c..3412952 100644
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 			index++) {
 		switch (index) {

board/freescale/mx53ard/mx53ard.c +4 -0

index 08c7795..2fc8570 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53evk/mx53evk.c +4 -0

index b11a94c..bb4621d 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>

@@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53loco/mx53loco.c +3 -0

index 8f82125..8f9b8df 100644
@@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53smd/mx53smd.c +3 -0

index 7f35ddd..761f727 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx6qarm2/mx6qarm2.c +4 -0

index d43b327..dad4b95 100644
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>

@@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
 	s32 status = 0;
 	u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 		switch (index) {
 		case 0:

board/freescale/mx6qsabrelite/mx6qsabrelite.c +3 -0

index 4b4e89b..3af8437 100644
@@ -264,6 +264,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 	       switch (index) {
 	       case 0:

board/genesi/mx51_efikamx/efikamx.c +4 -0

index cfd2e93..e334c01 100644
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
 		gpio_direction_input(EFIKASB_SDHC1_CD);
 	}
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 
 	if (machine_is_efikasb()) {

board/ttcontrol/vision2/vision2.c +2 -0

index f28eab0..ba3307b 100644
@@ -28,6 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>

@@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 		PAD_CTL_HYS_ENABLE);
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif

drivers/mmc/fsl_esdhc.c +3 -2

index 3f8d30d..aa6a9f1 100644
@@ -410,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-	int sdhc_clk = gd->sdhc_clk;
 	int div, pre_div;
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+	int sdhc_clk = cfg->sdhc_clk;
 	uint clk;
 
 	if (clock < mmc->f_min)

@@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
 	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
 	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->sdhc_clk;
 	return fsl_esdhc_initialize(bis, cfg);
 }

include/fsl_esdhc.h +1 -0

index 4e321e7..47d2fe4 100644
@@ -167,6 +167,7 @@
 
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
+	u32	sdhc_clk;
 };
 
 /* Select the correct accessors depending on endianess */

Benoît Thébaudeau

author

2012-09-28 13:09 UTC #1 lore raw

PATCH 1/1 mxc: Fix SDHC multi-instance clock

Quoted 303 lines · Beno?t Th?baudeau

On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Eric B?nard <[email protected]>

Cc Otavio Salvador <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Jason Liu <[email protected]>

Cc Matt Sealey <[email protected]>

Cc Andy Fleming <[email protected]>

---
This patch should be applied after (series of series...):
http://patchwork.ozlabs.org/patch/187467/
http://patchwork.ozlabs.org/patch/187468/
http://patchwork.ozlabs.org/patch/187475/

 .../board/esg/ima3-mx53/ima3-mx53.c                |    1 +
 .../board/freescale/mx35pdk/mx35pdk.c              |    2 ++
 .../board/freescale/mx51evk/mx51evk.c              |    4 ++++
 .../board/freescale/mx53ard/mx53ard.c              |    4 ++++
 .../board/freescale/mx53evk/mx53evk.c              |    4 ++++
 .../board/freescale/mx53loco/mx53loco.c            |    3 +++
 .../board/freescale/mx53smd/mx53smd.c              |    3 +++
 .../board/freescale/mx6qarm2/mx6qarm2.c            |    4 ++++
 .../board/freescale/mx6qsabrelite/mx6qsabrelite.c  |    3 +++
 .../board/genesi/mx51_efikamx/efikamx.c            |    4 ++++
 .../board/ttcontrol/vision2/vision2.c              |    2 ++
 .../drivers/mmc/fsl_esdhc.c                        |    5 +++--
 .../include/fsl_esdhc.h                            |    1 +
 13 files changed, 38 insertions(+), 2 deletions(-)

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/esg/ima3-mx53/ima3-mx53.c index e947330..41d6bb6 100644

board/esg/ima3-mx53/ima3-mx53.c +1 -0

@@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
 		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/freescale/mx35pdk/mx35pdk.c index 7cb6b30..a12531f 100644

board/freescale/mx35pdk/mx35pdk.c +2 -0

@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/mx35_pins.h>
 #include <asm/arch/iomux.h>
 #include <i2c.h>

@@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
 	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/freescale/mx51evk/mx51evk.c index a94701c..3412952 100644

board/freescale/mx51evk/mx51evk.c +4 -0

@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 			index++) {
 		switch (index) {

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/freescale/mx53ard/mx53ard.c index 08c7795..2fc8570 100644

board/freescale/mx53ard/mx53ard.c +4 -0

@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/freescale/mx53evk/mx53evk.c index b11a94c..bb4621d 100644

board/freescale/mx53evk/mx53evk.c +4 -0

@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>

@@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx53loco/mx53loco.c u-boot-imx-e1eb75b/board/freescale/mx53loco/mx53loco.c index 8f82125..8f9b8df 100644

board/freescale/mx53loco/mx53loco.c +3 -0

@@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/freescale/mx53smd/mx53smd.c index 7f35ddd..761f727 100644

board/freescale/mx53smd/mx53smd.c +3 -0

@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx6qarm2/mx6qarm2.c u-boot-imx-e1eb75b/board/freescale/mx6qarm2/mx6qarm2.c index d43b327..dad4b95 100644

board/freescale/mx6qarm2/mx6qarm2.c +4 -0

@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>

@@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
 	s32 status = 0;
 	u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 		switch (index) {
 		case 0:

diff --git u-boot-imx-e1eb75b.orig/board/freescale/mx6qsabrelite/mx6qsabrelite.c u-boot-imx-e1eb75b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 4b4e89b..3af8437 100644
---
u-boot-imx-e1eb75b.orig/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ u-boot-imx-e1eb75b/board/freescale/mx6qsabrelite/mx6qsabrelite.c

board/freescale/mx6qarm2/mx6qarm2.c +3 -0

@@ -264,6 +264,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 	       switch (index) {
 	       case 0:

diff --git u-boot-imx-e1eb75b.orig/board/genesi/mx51_efikamx/efikamx.c u-boot-imx-e1eb75b/board/genesi/mx51_efikamx/efikamx.c index cfd2e93..e334c01 100644

board/genesi/mx51_efikamx/efikamx.c +4 -0

@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
 		gpio_direction_input(EFIKASB_SDHC1_CD);
 	}
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 
 	if (machine_is_efikasb()) {

(quoted diff) +0 -0

u-boot-imx-e1eb75b/board/ttcontrol/vision2/vision2.c index f28eab0..ba3307b 100644

board/ttcontrol/vision2/vision2.c +2 -0

@@ -28,6 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>

@@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 		PAD_CTL_HYS_ENABLE);
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif

(quoted diff) +0 -0

u-boot-imx-e1eb75b/drivers/mmc/fsl_esdhc.c
index 3f8d30d..aa6a9f1 100644

drivers/mmc/fsl_esdhc.c +2 -2

@@ -410,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd
 *cmd, struct mmc_data *data)
 	return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-	int sdhc_clk = gd->sdhc_clk;
 	int div, pre_div;
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc
 	*)cfg->esdhc_base;
+	int sdhc_clk = cfg->sdhc_clk;
 	uint clk;

drivers/mmc/fsl_esdhc.c +1 -0

 	if (clock < mmc->f_min)

@@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
 	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
 	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->sdhc_clk;
 	return fsl_esdhc_initialize(bis, cfg);
 }

(quoted diff) +0 -0

u-boot-imx-e1eb75b/include/fsl_esdhc.h
index 4e321e7..47d2fe4 100644

include/fsl_esdhc.h line 173

Quoted 7 lines

include/fsl_esdhc.h +1 -0

@@ -167,6 +167,7 @@
 
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
+	u32	sdhc_clk;
 };
 
 /* Select the correct accessors depending on endianess */

Note that, just like for http://patchwork.ozlabs.org/patch/187454/, this will have to be extended to new boards like mx6qsabresd if this is applied to u-boot-imx/next rather than to u-boot-imx/master.

Best regards,
Beno?t

Benoît Thébaudeau

author

2012-10-01 18:36 UTC #2 lore raw

PATCH v2 1/1 mxc: Fix SDHC multi-instance clock

In reply to Benoît Thébaudeau

On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not suitable for the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).

This patch fixes this issue by adding a configuration field for the SDHC input clock frequency.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Eric B?nard <[email protected]>

Cc Otavio Salvador <[email protected]>

Cc Fabio Estevam <[email protected]>

Cc Jason Liu <[email protected]>

Cc Matt Sealey <[email protected]>

Cc Andy Fleming <[email protected]>

---
This patch should be applied after (series of series...):
http://patchwork.ozlabs.org/patch/187467/
http://patchwork.ozlabs.org/patch/187468/
http://patchwork.ozlabs.org/patch/187475/

This patch supersedes http://patchwork.ozlabs.org/patch/187476/ .

Changes for v2:
- Since this patch will go to /next, extend the original patch with the mxc boards newly added to this branch: mx6qsabreauto and mx6qsabresd.

 .../board/esg/ima3-mx53/ima3-mx53.c                |    1 +
 .../board/freescale/mx35pdk/mx35pdk.c              |    2 ++
 .../board/freescale/mx51evk/mx51evk.c              |    4 ++++
 .../board/freescale/mx53ard/mx53ard.c              |    4 ++++
 .../board/freescale/mx53evk/mx53evk.c              |    4 ++++
 .../board/freescale/mx53loco/mx53loco.c            |    3 +++
 .../board/freescale/mx53smd/mx53smd.c              |    3 +++
 .../board/freescale/mx6qarm2/mx6qarm2.c            |    4 ++++
 .../board/freescale/mx6qsabreauto/mx6qsabreauto.c  |    1 +
 .../board/freescale/mx6qsabrelite/mx6qsabrelite.c  |    3 +++
 .../board/freescale/mx6qsabresd/mx6qsabresd.c      |    1 +
 .../board/genesi/mx51_efikamx/efikamx.c            |    4 ++++
 .../board/ttcontrol/vision2/vision2.c              |    2 ++
 .../drivers/mmc/fsl_esdhc.c                        |    5 +++--
 .../include/fsl_esdhc.h                            |    1 +
 15 files changed, 40 insertions(+), 2 deletions(-)

board/esg/ima3-mx53/ima3-mx53.c +1 -0

index e947330..41d6bb6 100644
@@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
 		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
 		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif

board/freescale/mx35pdk/mx35pdk.c +2 -0

index 7cb6b30..a12531f 100644
@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/mx35_pins.h>
 #include <asm/arch/iomux.h>
 #include <i2c.h>

@@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
 	mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }

board/freescale/mx51evk/mx51evk.c +4 -0

index a94701c..3412952 100644
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
 			index++) {
 		switch (index) {

board/freescale/mx53ard/mx53ard.c +4 -0

index 08c7795..2fc8570 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53evk/mx53evk.c +4 -0

index b11a94c..bb4621d 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>

@@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53loco/mx53loco.c +3 -0

index 6543209..20569a5 100644
@@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx53smd/mx53smd.c +3 -0

index 7f35ddd..761f727 100644
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>

@@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
 	u32 index;
 	s32 status = 0;
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 		switch (index) {
 		case 0:

board/freescale/mx6qarm2/mx6qarm2.c +4 -0

index d43b327..dad4b95 100644
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>

@@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
 	s32 status = 0;
 	u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 		switch (index) {
 		case 0:

board/freescale/mx6qsabreauto/mx6qsabreauto.c +1 -0

index 8913b21..1309fca 100644
@@ -85,6 +85,7 @@ int board_mmc_init(bd_t *bis)
 {
 	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif

board/freescale/mx6qsabrelite/mx6qsabrelite.c +3 -0

index d274d8c..23f1719 100644
@@ -269,6 +269,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 	       switch (index) {
 	       case 0:

board/freescale/mx6qsabresd/mx6qsabresd.c +1 -0

index 03a6857..e02daa4 100644
@@ -120,6 +120,7 @@ int board_mmc_init(bd_t *bis)
 {
 	imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif

board/genesi/mx51_efikamx/efikamx.c +4 -0

index cfd2e93..e334c01 100644
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>

@@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
 		gpio_direction_input(EFIKASB_SDHC1_CD);
 	}
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
 	ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 
 	if (machine_is_efikasb()) {

board/ttcontrol/vision2/vision2.c +2 -0

index f28eab0..ba3307b 100644
@@ -28,6 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>

@@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
 	mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 		PAD_CTL_HYS_ENABLE);
 
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif

drivers/mmc/fsl_esdhc.c +3 -2

index 3f8d30d..aa6a9f1 100644
@@ -410,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 	return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-	int sdhc_clk = gd->sdhc_clk;
 	int div, pre_div;
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+	int sdhc_clk = cfg->sdhc_clk;
 	uint clk;
 
 	if (clock < mmc->f_min)

@@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
 	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
 	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->sdhc_clk;
 	return fsl_esdhc_initialize(bis, cfg);
 }

include/fsl_esdhc.h +1 -0

index 4e321e7..47d2fe4 100644
@@ -167,6 +167,7 @@
 
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
+	u32	sdhc_clk;
 };
 
 /* Select the correct accessors depending on endianess */

Benoît Thébaudeau

author

2012-10-09 10:35 UTC #3 lore raw

PATCH v2 1/1 mxc: Fix SDHC multi-instance clock

Hi Stefano,

Quoted 24 lines · Beno?t Th?baudeau

On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Eric B?nard <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Jason Liu <[email protected]>
Cc Matt Sealey <[email protected]>
Cc Andy Fleming <[email protected]>
---
This patch should be applied after (series of series...):
http://patchwork.ozlabs.org/patch/187467/
http://patchwork.ozlabs.org/patch/187468/
http://patchwork.ozlabs.org/patch/187475/

Quoted 6 lines

This patch supersedes http://patchwork.ozlabs.org/patch/187476/ .
Changes for v2:
- Since this patch will go to /next, extend the original patch with the mxc
boards newly added to this branch: mx6qsabreauto and mx6qsabresd.

Did you forget to apply this patch (and
http://patchwork.ozlabs.org/patch/187468/ before it) when you applied my mx5 and mx25 clock series, or is it just still in your TODO list?

If you could apply them before the Nitrogen6X series (in order to avoid a v3 of this patch), I'd be grateful ;) . But if you need more review/test time, of course no problem if this is not possible.

Best regards,
Beno?t

Stefano Babic

2012-10-09 10:58 UTC #4 lore raw

PATCH v2 1/1 mxc: Fix SDHC multi-instance clock

Quoted 29 lines · Beno?t Th?baudeau

Hi Stefano,
Quoted 26 lines · Beno?t Th?baudeau
On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not
suitable for the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
This patch fixes this issue by adding a configuration field for the SDHC input
clock frequency.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Eric B?nard <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Jason Liu <[email protected]>
Cc Matt Sealey <[email protected]>
Cc Andy Fleming <[email protected]>
---
This patch should be applied after (series of series...):
http://patchwork.ozlabs.org/patch/187467/
http://patchwork.ozlabs.org/patch/187468/
http://patchwork.ozlabs.org/patch/187475/
This patch supersedes http://patchwork.ozlabs.org/patch/187476/ .

Quoted 8 lines

Quoted 4 lines
Changes for v2:
- Since this patch will go to /next, extend the original patch with the mxc
boards newly added to this branch: mx6qsabreauto and mx6qsabresd.
Did you forget to apply this patch (and
http://patchwork.ozlabs.org/patch/187468/ before it) when you applied my mx5 and mx25 clock series, or is it just still in your TODO list?

No, I did not forget. There are two patches for ESDHC. I wanted to be sure that PowerPC boards are not broken and I have rechecked it this morning. They are both ready in my queue to be merged.

Quoted 3 lines

If you could apply them before the Nitrogen6X series (in order to avoid a v3 of this patch), I'd be grateful ;) . But if you need more review/test time, of course no problem if this is not possible.

I have some patches ready to be merged, but I sent also a pull request for the -next branch, and it is not yet merged into arm-next. Anyway, I can modify my pull request including further patches, too.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-10-10 11:29 UTC #5 lore raw

PATCH v2 1/1 mxc: Fix SDHC multi-instance clock

In reply to Benoît Thébaudeau

Quoted 15 lines · Beno?t Th?baudeau

On mxc, each SDHC instance has a dedicated clock, so gd->sdhc_clk is not suitable for the multi-instance use case (initialization made directly with fsl_esdhc_initialize()).
This patch fixes this issue by adding a configuration field for the SDHC input clock frequency.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Eric B?nard <[email protected]>
Cc Otavio Salvador <[email protected]>
Cc Fabio Estevam <[email protected]>
Cc Jason Liu <[email protected]>
Cc Matt Sealey <[email protected]>
Cc Andy Fleming <[email protected]>

Quoted 1 line

---

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================